From nobody Fri Dec 19 11:52:30 2025 Received: from inva021.nxp.com (inva021.nxp.com [92.121.34.21]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id F297C157480; Sun, 7 Dec 2025 13:32:01 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=92.121.34.21 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1765114323; cv=none; b=QW3jyVSZTkvZcPd/xt6ZkPp2nj8oLAfJeBUFIGOdt+BiSC0QgBVR/UQx8PMCplPJJWFguZ6rZejYtHzYtEugAtj0C7o8NbFYI7/hJqOXjiib/Rp2yA+YPt1oDoAENVi1uLVP/yrmAd30xMpjys3V6DsOnz94mdUjooWbdS4kCeE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1765114323; c=relaxed/simple; bh=Ms1VMn38PurnYbLCOaj8g6RLXsCv4SE/y4RWiYGa0xI=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=MSkFvjEVDFmfXllq+ZkCw7rgLLm/LXk5rfNgaGkR8KtEmxnZxXMoA4qyMN5IlnBvM5puyNzq6a/F1Nk9Geu1NsK3kmLafSviacS+YJxV6LIejLlEImkeLycMmqIh5ph7WYrzmguU7Ni+kFbx/Rh8AquYdoU1e4OhYU2lJ77LvNA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=nxp.com; spf=pass smtp.mailfrom=nxp.com; arc=none smtp.client-ip=92.121.34.21 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=nxp.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=nxp.com Received: from inva021.nxp.com (localhost [127.0.0.1]) by inva021.eu-rdc02.nxp.com (Postfix) with ESMTP id 20C08200181; Sun, 7 Dec 2025 14:26:09 +0100 (CET) Received: from usswic1srsp001v.us-swic1.nxp.com (unknown [10.114.8.222]) by inva021.eu-rdc02.nxp.com (Postfix) with ESMTP id E5F382001B9; Sun, 7 Dec 2025 14:26:08 +0100 (CET) Received: from lsvm07u0000156.swis.us-west-2.aws.nxp.com (lsvm07u0000156.swis.us-west-2.aws.nxp.com [10.45.140.59]) by usswic1srsp001v.us-swic1.nxp.com (Postfix) with ESMTP id D3A641800303; Sun, 7 Dec 2025 05:26:07 -0800 (PST) From: Lei Xu Date: Sun, 07 Dec 2025 05:26:05 -0800 Subject: [PATCH 1/2] dt-bindings: arm: fsl: Add compatible for i.MX95 15x15 FRDM board Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251207-127-v1-1-5a2eeb69f150@nxp.com> References: <20251207-127-v1-0-5a2eeb69f150@nxp.com> In-Reply-To: <20251207-127-v1-0-5a2eeb69f150@nxp.com> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org, justin.jiang@nxp.com, qijian.guo@nxp.com, lei.xu@nxp.com X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1765113967; l=980; i=lei.xu@nxp.com; s=20251205; h=from:subject:message-id; bh=Ms1VMn38PurnYbLCOaj8g6RLXsCv4SE/y4RWiYGa0xI=; b=3Qpr8GhKWzvDuemhut+WgqOIj7zL9qH2FK9sbgCY+K3m4Y2qxQoOztfYK8RrHhlvo5Ipcvfbi X1CNChqqGX7AoMi1CrvZCNnPOgsj4opSsiFJ0qNuUu+esq1MT+xhYcx X-Developer-Key: i=lei.xu@nxp.com; a=ed25519; pk=faUN/3jfazJOPNYhE9pN+nzvk+lrEm64ZRf42Yeum6U= X-Virus-Scanned: ClamAV using ClamSMTP Introduce a new DT compatible string for the NXP i.MX95 15x15 FRDM development board, a compact and cost-effective platform based on the i.MX95 applications processor. Signed-off-by: Lei Xu Acked-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/arm/fsl.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation= /devicetree/bindings/arm/fsl.yaml index 68a2d5fecc43..4b6188d39be6 100644 --- a/Documentation/devicetree/bindings/arm/fsl.yaml +++ b/Documentation/devicetree/bindings/arm/fsl.yaml @@ -1432,6 +1432,7 @@ properties: items: - enum: - fsl,imx95-15x15-evk # i.MX95 15x15 EVK Board + - fsl,imx95-15x15-frdm # i.MX95 15x15 FRDM Board - fsl,imx95-19x19-evk # i.MX95 19x19 EVK Board - toradex,verdin-imx95-19x19-evk # i.MX95 Verdin Evaluation= Kit (EVK) - const: fsl,imx95 --=20 2.34.1 From nobody Fri Dec 19 11:52:30 2025 Received: from inva020.nxp.com (inva020.nxp.com [92.121.34.13]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7D43A2F3636; Sun, 7 Dec 2025 13:26:17 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=92.121.34.13 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1765113980; cv=none; b=oK4LVPnYUgTDcQjD2WFArhH1yMr4LrBA9dasnS1V5yj6Qaq6AVa0lzwVocS0DGS3RTEDXoghlIUM/eVZ79l0TzAskEb7/duj6DVnTFDDgpg/KmjzIMphJMUNHZNO1V/LinFcNri3yTjGaJqAwCp922v/+QEvG1z5qxWTMImPojE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1765113980; c=relaxed/simple; bh=IOJl+JfSXS5lnL0ImibyIqAi/Yhyv2NE9gbSS1H3u2A=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=tJzEBrejoFeD5eb583I/Fs/sgPoDLB5/OgtZftih6csLGUjE69VCiBPC9IkfiT4ylkuLFsu0z+n+LEg5wckbAI6skJvNwHBzRPixCbN4KuX0zAF9TyyVdt2bjnlsNcwRQAnLm1FxgyuUvna1emCb0wblOugkfKzgFYNQXtpmpsA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=nxp.com; spf=pass smtp.mailfrom=nxp.com; arc=none smtp.client-ip=92.121.34.13 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=nxp.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=nxp.com Received: from inva020.nxp.com (localhost [127.0.0.1]) by inva020.eu-rdc02.nxp.com (Postfix) with ESMTP id A6BE71A02AB; Sun, 7 Dec 2025 14:26:09 +0100 (CET) Received: from usswic1srsp001v.us-swic1.nxp.com (unknown [10.114.8.222]) by inva020.eu-rdc02.nxp.com (Postfix) with ESMTP id 54E5E1A02A5; Sun, 7 Dec 2025 14:26:09 +0100 (CET) Received: from lsvm07u0000156.swis.us-west-2.aws.nxp.com (lsvm07u0000156.swis.us-west-2.aws.nxp.com [10.45.140.59]) by usswic1srsp001v.us-swic1.nxp.com (Postfix) with ESMTP id 7E51E1800317; Sun, 7 Dec 2025 05:26:08 -0800 (PST) From: Lei Xu Date: Sun, 07 Dec 2025 05:26:06 -0800 Subject: [PATCH 2/2] arm64: dts: freescale: imx95: Add support for i.MX95 15x15 FRDM board Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251207-127-v1-2-5a2eeb69f150@nxp.com> References: <20251207-127-v1-0-5a2eeb69f150@nxp.com> In-Reply-To: <20251207-127-v1-0-5a2eeb69f150@nxp.com> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org, justin.jiang@nxp.com, qijian.guo@nxp.com, lei.xu@nxp.com X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1765113967; l=25999; i=lei.xu@nxp.com; s=20251205; h=from:subject:message-id; bh=IOJl+JfSXS5lnL0ImibyIqAi/Yhyv2NE9gbSS1H3u2A=; b=KcR0suB8r5QE4nzXjgwiiIncmKBi+9Ntey1bH1olOHiv8EKwx5Yd90/iOFuOD31jrS+FOxidF R6uEpNgpDAqAUMtQE9+6GJ1lXjr/TyoGTTp+N6vG798rSEkkjZYGe/l X-Developer-Key: i=lei.xu@nxp.com; a=ed25519; pk=faUN/3jfazJOPNYhE9pN+nzvk+lrEm64ZRf42Yeum6U= X-Virus-Scanned: ClamAV using ClamSMTP The i.MX95 15x15 FRDM board is a compact and cost-effective development platform based on the i.MX95 applications processor. Add device tree support for this board, including: - LPUART1 and LPUART5 - NETC - USB - PCIe - uSDHC1, uSDHC2 and uSDHC3 - FlexCAN2 and FlexCAN5 - LPI2C2, LPI2C3, LPI2C4 and their child nodes - Watchdog3 Signed-off-by: Lei Xu --- arch/arm64/boot/dts/freescale/Makefile | 1 + arch/arm64/boot/dts/freescale/imx95-15x15-frdm.dts | 955 +++++++++++++++++= ++++ 2 files changed, 956 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/f= reescale/Makefile index f30d3fd724d0..71308d19d35e 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -400,6 +400,7 @@ dtb-$(CONFIG_ARCH_MXC) +=3D imx93-tqma9352-mba93xxla.dtb dtb-$(CONFIG_ARCH_MXC) +=3D imx93-var-som-symphony.dtb dtb-$(CONFIG_ARCH_MXC) +=3D imx943-evk.dtb dtb-$(CONFIG_ARCH_MXC) +=3D imx95-15x15-evk.dtb +dtb-$(CONFIG_ARCH_MXC) +=3D imx95-15x15-frdm.dtb dtb-$(CONFIG_ARCH_MXC) +=3D imx95-19x19-evk.dtb dtb-$(CONFIG_ARCH_MXC) +=3D imx95-19x19-evk-sof.dtb dtb-$(CONFIG_ARCH_MXC) +=3D imx95-toradex-smarc-dev.dtb diff --git a/arch/arm64/boot/dts/freescale/imx95-15x15-frdm.dts b/arch/arm6= 4/boot/dts/freescale/imx95-15x15-frdm.dts new file mode 100644 index 000000000000..61e815c858b8 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx95-15x15-frdm.dts @@ -0,0 +1,955 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2025 NXP + */ + +/dts-v1/; + +#include +#include +#include +#include +#include "imx95.dtsi" + +#define BRD_SM_CTRL_SD3_WAKE 0x8000 /*!< PCAL6408A-0 */ +#define BRD_SM_CTRL_PCIE1_WAKE 0x8001 /*!< PCAL6408A-4 */ +#define BRD_SM_CTRL_BT_WAKE 0x8002 /*!< PCAL6408A-5 */ +#define BRD_SM_CTRL_PCIE2_WAKE 0x8003 /*!< PCAL6408A-6 */ +#define BRD_SM_CTRL_BUTTON 0x8004 /*!< PCAL6408A-7 */ + +/ { + compatible =3D "fsl,imx95-15x15-frdm", "fsl,imx95"; + model =3D "NXP i.MX95 15X15 FRDM board"; + + aliases { + ethernet0 =3D &enetc_port0; + ethernet1 =3D &enetc_port1; + gpio0 =3D &gpio1; + gpio1 =3D &gpio2; + gpio2 =3D &gpio3; + gpio3 =3D &gpio4; + gpio4 =3D &gpio5; + i2c0 =3D &lpi2c1; + i2c1 =3D &lpi2c2; + i2c2 =3D &lpi2c3; + i2c3 =3D &lpi2c4; + i2c4 =3D &lpi2c5; + i2c5 =3D &lpi2c6; + i2c6 =3D &lpi2c7; + i2c7 =3D &lpi2c8; + mmc0 =3D &usdhc1; + mmc1 =3D &usdhc2; + mmc2 =3D &usdhc3; + serial0 =3D &lpuart1; + serial4 =3D &lpuart5; + }; + + chosen { + #address-cells =3D <2>; + #size-cells =3D <2>; + stdout-path =3D &lpuart1; + }; + + dmic: dmic { + compatible =3D "dmic-codec"; + #sound-dai-cells =3D <0>; + num-channels =3D <2>; + }; + + reg_1p8v: regulator-1p8v { + compatible =3D "regulator-fixed"; + regulator-max-microvolt =3D <1800000>; + regulator-min-microvolt =3D <1800000>; + regulator-name =3D "+V1.8_SW"; + }; + + reg_3p3v: regulator-3p3v { + compatible =3D "regulator-fixed"; + regulator-max-microvolt =3D <3300000>; + regulator-min-microvolt =3D <3300000>; + regulator-name =3D "+V3.3_SW"; + }; + + reg_5p0v: regulator-5p0v { + compatible =3D "regulator-fixed"; + regulator-max-microvolt =3D <5000000>; + regulator-min-microvolt =3D <5000000>; + regulator-name =3D "+V5.0_SW"; + }; + + reg_can_stby: regulator-can-stby { + compatible =3D "regulator-fixed"; + regulator-max-microvolt =3D <3300000>; + regulator-min-microvolt =3D <3300000>; + regulator-name =3D "can-stby"; + gpio =3D <&pcal6524 7 GPIO_ACTIVE_LOW>; + }; + + reg_ext_3v3: regulator-ext-3v3 { + compatible =3D "regulator-fixed"; + regulator-max-microvolt =3D <3300000>; + regulator-min-microvolt =3D <3300000>; + regulator-name =3D "VCCEXT_3V3"; + }; + + reg_ext_5v: regulator-ext-5v { + compatible =3D "regulator-fixed"; + regulator-always-on; + regulator-max-microvolt =3D <5000000>; + regulator-min-microvolt =3D <5000000>; + regulator-name =3D "VCCEXT_5V"; + gpio =3D <&pcal6524 12 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_m2_ekey_pwr: regulator-m2-pwr { + compatible =3D "regulator-fixed"; + regulator-max-microvolt =3D <3300000>; + regulator-min-microvolt =3D <3300000>; + regulator-name =3D "M.2-power-ekey"; + gpio =3D <&pcal6524 16 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_m2_mkey_pwr: regulator-m2-mkey-pwr { + compatible =3D "regulator-fixed"; + regulator-max-microvolt =3D <3300000>; + regulator-min-microvolt =3D <3300000>; + regulator-name =3D "M.2-mkey-power"; + gpio =3D <&pcal6524 14 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_usdhc2_vmmc: regulator-usdhc2 { + compatible =3D "regulator-fixed"; + off-on-delay-us =3D <12000>; + pinctrl-0 =3D <&pinctrl_reg_usdhc2_vmmc>; + pinctrl-names =3D "default"; + regulator-max-microvolt =3D <3300000>; + regulator-min-microvolt =3D <3300000>; + regulator-name =3D "VDD_SD2_3V3"; + gpio =3D <&gpio3 7 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_usdhc3_vmmc: regulator-usdhc3 { + compatible =3D "regulator-fixed"; + regulator-max-microvolt =3D <3300000>; + regulator-min-microvolt =3D <3300000>; + regulator-name =3D "WLAN_EN"; + vin-supply =3D <®_m2_ekey_pwr>; + gpio =3D <&pcal6524 9 GPIO_ACTIVE_HIGH>; + enable-active-high; + /* + * IW612 wifi chip needs more delay than other wifi chips to complete + * the host interface initialization after power up, otherwise the + * internal state of IW612 may be unstable, resulting in the failure of + * the SDIO3.0 switch voltage. + */ + startup-delay-us =3D <20000>; + }; + + reg_usb_vbus: regulator-vbus { + compatible =3D "regulator-fixed"; + regulator-max-microvolt =3D <5000000>; + regulator-min-microvolt =3D <5000000>; + regulator-name =3D "USB_VBUS"; + gpio =3D <&pcal6524 15 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_vref_1v8: regulator-adc-vref { + compatible =3D "regulator-fixed"; + regulator-max-microvolt =3D <1800000>; + regulator-min-microvolt =3D <1800000>; + regulator-name =3D "vref_1v8"; + }; + + reserved-memory { + ranges; + #address-cells =3D <2>; + #size-cells =3D <2>; + + linux_cma: linux,cma { + compatible =3D "shared-dma-pool"; + alloc-ranges =3D <0 0x80000000 0 0x7F000000>; + reusable; + size =3D <0 0x3c000000>; + linux,cma-default; + }; + + vdev0vring0: memory@88000000 { + reg =3D <0 0x88000000 0 0x8000>; + no-map; + }; + + vdev0vring1: memory@88008000 { + reg =3D <0 0x88008000 0 0x8000>; + no-map; + }; + + vdev1vring0: memory@88010000 { + reg =3D <0 0x88010000 0 0x8000>; + no-map; + }; + + vdev1vring1: memory@88018000 { + reg =3D <0 0x88018000 0 0x8000>; + no-map; + }; + + vdevbuffer: memory@88020000 { + compatible =3D "shared-dma-pool"; + reg =3D <0 0x88020000 0 0x100000>; + no-map; + }; + + rsc_table: memory@88220000 { + reg =3D <0 0x88220000 0 0x1000>; + no-map; + }; + + vpu_boot: memory@a0000000 { + reg =3D <0 0xa0000000 0 0x100000>; + no-map; + }; + }; + + sound-micfil { + compatible =3D "fsl,imx-audio-card"; + model =3D "micfil-audio"; + + pri-dai-link { + link-name =3D "micfil hifi"; + format =3D "i2s"; + + cpu { + sound-dai =3D <&micfil>; + }; + codec { + sound-dai =3D <&dmic>; + }; + }; + }; + + usdhc3_pwrseq: usdhc3-pwrseq { + compatible =3D "mmc-pwrseq-simple"; + reset-gpios =3D <&pcal6524 8 GPIO_ACTIVE_LOW>; + }; + + memory@80000000 { + reg =3D <0x0 0x80000000 0 0x80000000>; + device_type =3D "memory"; + }; +}; + +&adc1 { + vref-supply =3D <®_vref_1v8>; + status =3D "okay"; +}; + +&enetc_port0 { + phy-handle =3D <ðphy0>; + phy-mode =3D "rgmii-id"; + pinctrl-0 =3D <&pinctrl_enetc0>; + pinctrl-names =3D "default"; + status =3D "okay"; +}; + +&enetc_port1 { + phy-handle =3D <ðphy1>; + phy-mode =3D "rgmii-id"; + pinctrl-0 =3D <&pinctrl_enetc1>; + pinctrl-names =3D "default"; + status =3D "okay"; +}; + +&flexcan2 { + pinctrl-0 =3D <&pinctrl_flexcan2>; + pinctrl-names =3D "default"; + xceiver-supply =3D <®_can_stby>; + status =3D "okay"; +}; + +&flexcan5 { + pinctrl-0 =3D <&pinctrl_flexcan5>; + pinctrl-names =3D "default"; + xceiver-supply =3D <®_can_stby>; + status =3D "okay"; +}; + +&lpi2c2 { + clock-frequency =3D <400000>; + pinctrl-0 =3D <&pinctrl_lpi2c2>; + pinctrl-names =3D "default"; + status =3D "okay"; + + pcal6524: gpio@22 { + compatible =3D "nxp,pcal6524"; + reg =3D <0x22>; + #interrupt-cells =3D <2>; + interrupt-controller; + interrupt-parent =3D <&gpio5>; + interrupts =3D <14 IRQ_TYPE_LEVEL_LOW>; + #gpio-cells =3D <2>; + gpio-controller; + pinctrl-0 =3D <&pinctrl_pcal6524>; + pinctrl-names =3D "default"; + gpio-line-names =3D "ENET1 PHY reset", + "ENET2 PHY reset", + "SPI3/GPIO select", + "UART3/GPIO select", + "CAN2&5/GPIO select", + "PWM/GPIO select", + "Watch dog enable", + "CAN1&2&5 silent", + "SDIO_nRST", + "WL_nDISABLE1", + "WL_nDISABLE2", + "M.2 Mkey NC06", + "EXT_5V0_PWR_EN", + "EXT_3V3_PWR_EN", + "Mkey power control", + "USB2 power control", + "Ekey power control", + "MIPI-DSICSI reset", + "MIPI-DSI IO2", + "MIPI-CSI reset", + "LVDS TP reset", + "LVDS BL enable", + "LVDS BL power enable", + "IT6263 reset"; + + lpspi-gpio-sel-hog { + gpio-hog; + gpios =3D <2 GPIO_ACTIVE_HIGH>; + output-low; + }; + + lpuart-gpio-sel-hog { + gpio-hog; + gpios =3D <3 GPIO_ACTIVE_HIGH>; + output-low; + }; + + can-gpio-sel-hog { + gpio-hog; + gpios =3D <4 GPIO_ACTIVE_HIGH>; + output-low; + }; + + pwm-gpio-sel-hog { + gpio-hog; + gpios =3D <5 GPIO_ACTIVE_HIGH>; + output-high; + }; + }; +}; + +&lpi2c3 { + clock-frequency =3D <400000>; + pinctrl-0 =3D <&pinctrl_lpi2c3>; + pinctrl-names =3D "default"; + status =3D "okay"; + + ptn5110: tcpc@50 { + compatible =3D "nxp,ptn5110", "tcpci"; + reg =3D <0x50>; + interrupt-parent =3D <&gpio5>; + interrupts =3D <3 IRQ_TYPE_LEVEL_LOW>; + pinctrl-0 =3D <&pinctrl_ptn5110>; + pinctrl-names =3D "default"; + + typec_con: connector { + compatible =3D "usb-c-connector"; + data-role =3D "dual"; + label =3D "USB-C"; + op-sink-microwatt =3D <15000000>; + power-role =3D "dual"; + self-powered; + sink-pdos =3D ; + source-pdos =3D ; + try-power-role =3D "sink"; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + + typec_con_hs: endpoint { + remote-endpoint =3D <&usb3_data_hs>; + }; + }; + + port@1 { + reg =3D <1>; + + typec_con_ss: endpoint { + remote-endpoint =3D <&usb3_data_ss>; + }; + }; + }; + }; + }; +}; + +&lpi2c4 { + clock-frequency =3D <400000>; + pinctrl-0 =3D <&pinctrl_lpi2c4>; + pinctrl-names =3D "default"; + status =3D "okay"; + + pca9632: led-controller@62 { + compatible =3D "nxp,pca9632"; + reg =3D <0x62>; + #address-cells =3D <1>; + #size-cells =3D <0>; + nxp,inverted-out; + + led_backlight0: led@0 { + reg =3D <0>; + color =3D ; + function =3D LED_FUNCTION_BACKLIGHT; + function-enumerator =3D <0>; + }; + + led_backlight1: led@1 { + reg =3D <1>; + color =3D ; + function =3D LED_FUNCTION_BACKLIGHT; + function-enumerator =3D <1>; + }; + }; +}; + +&lpuart1 { + pinctrl-0 =3D <&pinctrl_uart1>; + pinctrl-names =3D "default"; + status =3D "okay"; +}; + +&lpuart5 { + pinctrl-0 =3D <&pinctrl_uart5>; + pinctrl-names =3D "default"; + status =3D "okay"; + + bluetooth { + compatible =3D "nxp,88w8987-bt"; + }; +}; + +&micfil { + assigned-clocks =3D <&scmi_clk IMX95_CLK_AUDIOPLL1_VCO>, + <&scmi_clk IMX95_CLK_AUDIOPLL2_VCO>, + <&scmi_clk IMX95_CLK_AUDIOPLL1>, + <&scmi_clk IMX95_CLK_AUDIOPLL2>, + <&scmi_clk IMX95_CLK_PDM>; + assigned-clock-parents =3D <0>, <0>, <0>, <0>, + <&scmi_clk IMX95_CLK_AUDIOPLL1>; + assigned-clock-rates =3D <3932160000>, + <3612672000>, <393216000>, + <361267200>, <49152000>; + #sound-dai-cells =3D <0>; + pinctrl-0 =3D <&pinctrl_pdm>; + pinctrl-names =3D "default"; + status =3D "okay"; +}; + +&mu7 { + status =3D "okay"; +}; + +&netc_blk_ctrl { + status =3D "okay"; +}; + +/* Default settings in i.mx95.dtsi are for i.MX95 19x19 package. + * Override here for the i.MX95 15x15 package. + */ +&netc_bus0 { + msi-map =3D <0x0 &its 0x60 0x1>, //ENETC0 PF + <0x10 &its 0x61 0x1>, //ENETC0 VF0 + <0x20 &its 0x62 0x1>, //ENETC0 VF1 + <0x40 &its 0x63 0x1>, //ENETC1 PF + <0x50 &its 0x65 0x1>, //ENETC1 VF0 + <0x60 &its 0x66 0x1>, //ENETC1 VF1 + <0x80 &its 0x64 0x1>, //ENETC2 PF + <0xc0 &its 0x67 0x1>; //NETC Timer + iommu-map =3D <0x0 &smmu 0x20 0x1>, + <0x10 &smmu 0x21 0x1>, + <0x20 &smmu 0x22 0x1>, + <0x40 &smmu 0x23 0x1>, + <0x50 &smmu 0x25 0x1>, + <0x60 &smmu 0x26 0x1>, + <0x80 &smmu 0x24 0x1>, + <0xc0 &smmu 0x27 0x1>; +}; + +&netc_emdio { + pinctrl-0 =3D <&pinctrl_emdio>; + pinctrl-names =3D "default"; + status =3D "okay"; + + ethphy0: ethernet-phy@1 { + reg =3D <1>; + reset-assert-us =3D <10000>; + reset-deassert-us =3D <80000>; + reset-gpios =3D <&pcal6524 0 GPIO_ACTIVE_LOW>; + }; + + ethphy1: ethernet-phy@2 { + reg =3D <2>; + reset-assert-us =3D <10000>; + reset-deassert-us =3D <80000>; + reset-gpios =3D <&pcal6524 1 GPIO_ACTIVE_LOW>; + }; +}; + +&netc_timer { + status =3D "okay"; +}; + +&netcmix_blk_ctrl { + status =3D "okay"; +}; + +&pcie0 { + pinctrl-0 =3D <&pinctrl_pcie0>; + pinctrl-names =3D "default"; + reset-gpio =3D <&gpio5 13 GPIO_ACTIVE_LOW>; + supports-clkreq; + vpcie-supply =3D <®_m2_mkey_pwr>; + status =3D "okay"; +}; + +&scmi_iomuxc { + pinctrl_emdio: emdiogrp { + fsl,pins =3D < + IMX95_PAD_ENET2_MDC__NETCMIX_TOP_NETC_MDC 0x50e + IMX95_PAD_ENET2_MDIO__NETCMIX_TOP_NETC_MDIO 0x90e + >; + }; + + pinctrl_enetc0: enetc0grp { + fsl,pins =3D < + IMX95_PAD_ENET1_TD3__NETCMIX_TOP_ETH0_RGMII_TD3 0x50e + IMX95_PAD_ENET1_TD2__NETCMIX_TOP_ETH0_RGMII_TD2 0x50e + IMX95_PAD_ENET1_TD1__NETCMIX_TOP_ETH0_RGMII_TD1 0x50e + IMX95_PAD_ENET1_TD0__NETCMIX_TOP_ETH0_RGMII_TD0 0x50e + IMX95_PAD_ENET1_TX_CTL__NETCMIX_TOP_ETH0_RGMII_TX_CTL 0x57e + IMX95_PAD_ENET1_TXC__NETCMIX_TOP_ETH0_RGMII_TX_CLK 0x58e + IMX95_PAD_ENET1_RX_CTL__NETCMIX_TOP_ETH0_RGMII_RX_CTL 0x57e + IMX95_PAD_ENET1_RXC__NETCMIX_TOP_ETH0_RGMII_RX_CLK 0x58e + IMX95_PAD_ENET1_RD0__NETCMIX_TOP_ETH0_RGMII_RD0 0x57e + IMX95_PAD_ENET1_RD1__NETCMIX_TOP_ETH0_RGMII_RD1 0x57e + IMX95_PAD_ENET1_RD2__NETCMIX_TOP_ETH0_RGMII_RD2 0x57e + IMX95_PAD_ENET1_RD3__NETCMIX_TOP_ETH0_RGMII_RD3 0x57e + >; + }; + + pinctrl_enetc1: enetc1grp { + fsl,pins =3D < + IMX95_PAD_ENET2_TD3__NETCMIX_TOP_ETH1_RGMII_TD3 0x50e + IMX95_PAD_ENET2_TD2__NETCMIX_TOP_ETH1_RGMII_TD2 0x50e + IMX95_PAD_ENET2_TD1__NETCMIX_TOP_ETH1_RGMII_TD1 0x50e + IMX95_PAD_ENET2_TD0__NETCMIX_TOP_ETH1_RGMII_TD0 0x50e + IMX95_PAD_ENET2_TX_CTL__NETCMIX_TOP_ETH1_RGMII_TX_CTL 0x57e + IMX95_PAD_ENET2_TXC__NETCMIX_TOP_ETH1_RGMII_TX_CLK 0x58e + IMX95_PAD_ENET2_RX_CTL__NETCMIX_TOP_ETH1_RGMII_RX_CTL 0x57e + IMX95_PAD_ENET2_RXC__NETCMIX_TOP_ETH1_RGMII_RX_CLK 0x58e + IMX95_PAD_ENET2_RD0__NETCMIX_TOP_ETH1_RGMII_RD0 0x57e + IMX95_PAD_ENET2_RD1__NETCMIX_TOP_ETH1_RGMII_RD1 0x57e + IMX95_PAD_ENET2_RD2__NETCMIX_TOP_ETH1_RGMII_RD2 0x57e + IMX95_PAD_ENET2_RD3__NETCMIX_TOP_ETH1_RGMII_RD3 0x57e + >; + }; + + pinctrl_flexcan2: flexcan2grp { + fsl,pins =3D < + IMX95_PAD_GPIO_IO25__CAN2_TX 0x39e + IMX95_PAD_GPIO_IO27__CAN2_RX 0x39e + >; + }; + + pinctrl_flexcan5: flexcan5grp { + fsl,pins =3D < + IMX95_PAD_GPIO_IO22__CAN5_TX 0x39e + IMX95_PAD_GPIO_IO23__CAN5_RX 0x39e + >; + }; + + pinctrl_lpi2c1: lpi2c1grp { + fsl,pins =3D < + IMX95_PAD_I2C1_SCL__AONMIX_TOP_LPI2C1_SCL 0x40000b9e + IMX95_PAD_I2C1_SDA__AONMIX_TOP_LPI2C1_SDA 0x40000b9e + >; + }; + + pinctrl_lpi2c2: lpi2c2grp { + fsl,pins =3D < + IMX95_PAD_I2C2_SCL__AONMIX_TOP_LPI2C2_SCL 0x40000b9e + IMX95_PAD_I2C2_SDA__AONMIX_TOP_LPI2C2_SDA 0x40000b9e + >; + }; + + pinctrl_lpi2c3: lpi2c3grp { + fsl,pins =3D < + IMX95_PAD_GPIO_IO28__LPI2C3_SDA 0x40000b9e + IMX95_PAD_GPIO_IO29__LPI2C3_SCL 0x40000b9e + >; + }; + + pinctrl_lpi2c4: lpi2c4grp { + fsl,pins =3D < + IMX95_PAD_GPIO_IO30__LPI2C4_SDA 0x40000b9e + IMX95_PAD_GPIO_IO31__LPI2C4_SCL 0x40000b9e + >; + }; + + pinctrl_pcal6524: pcal6524grp { + fsl,pins =3D < + IMX95_PAD_GPIO_IO34__GPIO5_IO_BIT14 0x31e + >; + }; + + pinctrl_pcie0: pcie0grp { + fsl,pins =3D < + IMX95_PAD_GPIO_IO32__HSIOMIX_TOP_PCIE1_CLKREQ_B 0x40000b1e + IMX95_PAD_GPIO_IO33__GPIO5_IO_BIT13 0x31e + >; + }; + + pinctrl_pdm: pdmgrp { + fsl,pins =3D < + IMX95_PAD_PDM_CLK__AONMIX_TOP_PDM_CLK 0x31e + IMX95_PAD_PDM_BIT_STREAM0__AONMIX_TOP_PDM_BIT_STREAM_BIT0 0x31e + >; + }; + + pinctrl_ptn5110: ptn5110grp { + fsl,pins =3D < + IMX95_PAD_XSPI1_DATA3__GPIO5_IO_BIT3 0x31e + >; + }; + + pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { + fsl,pins =3D < + IMX95_PAD_SD2_RESET_B__GPIO3_IO_BIT7 0x31e + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins =3D < + IMX95_PAD_UART1_RXD__AONMIX_TOP_LPUART1_RX 0x31e + IMX95_PAD_UART1_TXD__AONMIX_TOP_LPUART1_TX 0x31e + >; + }; + + pinctrl_uart5: uart5grp { + fsl,pins =3D < + IMX95_PAD_DAP_TDO_TRACESWO__LPUART5_TX 0x31e + IMX95_PAD_DAP_TDI__LPUART5_RX 0x31e + IMX95_PAD_DAP_TMS_SWDIO__LPUART5_RTS_B 0x31e + IMX95_PAD_DAP_TCLK_SWCLK__LPUART5_CTS_B 0x31e + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins =3D < + IMX95_PAD_SD1_CLK__USDHC1_CLK 0x158e + IMX95_PAD_SD1_CMD__USDHC1_CMD 0x138e + IMX95_PAD_SD1_DATA0__USDHC1_DATA0 0x138e + IMX95_PAD_SD1_DATA1__USDHC1_DATA1 0x138e + IMX95_PAD_SD1_DATA2__USDHC1_DATA2 0x138e + IMX95_PAD_SD1_DATA3__USDHC1_DATA3 0x138e + IMX95_PAD_SD1_DATA4__USDHC1_DATA4 0x138e + IMX95_PAD_SD1_DATA5__USDHC1_DATA5 0x138e + IMX95_PAD_SD1_DATA6__USDHC1_DATA6 0x138e + IMX95_PAD_SD1_DATA7__USDHC1_DATA7 0x138e + IMX95_PAD_SD1_STROBE__USDHC1_STROBE 0x158e + >; + }; + + pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { + fsl,pins =3D < + IMX95_PAD_SD1_CLK__USDHC1_CLK 0x158e + IMX95_PAD_SD1_CMD__USDHC1_CMD 0x138e + IMX95_PAD_SD1_DATA0__USDHC1_DATA0 0x138e + IMX95_PAD_SD1_DATA1__USDHC1_DATA1 0x138e + IMX95_PAD_SD1_DATA2__USDHC1_DATA2 0x138e + IMX95_PAD_SD1_DATA3__USDHC1_DATA3 0x138e + IMX95_PAD_SD1_DATA4__USDHC1_DATA4 0x138e + IMX95_PAD_SD1_DATA5__USDHC1_DATA5 0x138e + IMX95_PAD_SD1_DATA6__USDHC1_DATA6 0x138e + IMX95_PAD_SD1_DATA7__USDHC1_DATA7 0x138e + IMX95_PAD_SD1_STROBE__USDHC1_STROBE 0x158e + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { + fsl,pins =3D < + IMX95_PAD_SD1_CLK__USDHC1_CLK 0x15fe + IMX95_PAD_SD1_CMD__USDHC1_CMD 0x13fe + IMX95_PAD_SD1_DATA0__USDHC1_DATA0 0x13fe + IMX95_PAD_SD1_DATA1__USDHC1_DATA1 0x13fe + IMX95_PAD_SD1_DATA2__USDHC1_DATA2 0x13fe + IMX95_PAD_SD1_DATA3__USDHC1_DATA3 0x13fe + IMX95_PAD_SD1_DATA4__USDHC1_DATA4 0x13fe + IMX95_PAD_SD1_DATA5__USDHC1_DATA5 0x13fe + IMX95_PAD_SD1_DATA6__USDHC1_DATA6 0x13fe + IMX95_PAD_SD1_DATA7__USDHC1_DATA7 0x13fe + IMX95_PAD_SD1_STROBE__USDHC1_STROBE 0x15fe + >; + }; + + pinctrl_usdhc2_gpio: usdhc2gpiogrp { + fsl,pins =3D < + IMX95_PAD_SD2_CD_B__GPIO3_IO_BIT0 0x31e + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins =3D < + IMX95_PAD_SD2_CLK__USDHC2_CLK 0x158e + IMX95_PAD_SD2_CMD__USDHC2_CMD 0x138e + IMX95_PAD_SD2_DATA0__USDHC2_DATA0 0x138e + IMX95_PAD_SD2_DATA1__USDHC2_DATA1 0x138e + IMX95_PAD_SD2_DATA2__USDHC2_DATA2 0x138e + IMX95_PAD_SD2_DATA3__USDHC2_DATA3 0x138e + IMX95_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { + fsl,pins =3D < + IMX95_PAD_SD2_CLK__USDHC2_CLK 0x158e + IMX95_PAD_SD2_CMD__USDHC2_CMD 0x138e + IMX95_PAD_SD2_DATA0__USDHC2_DATA0 0x138e + IMX95_PAD_SD2_DATA1__USDHC2_DATA1 0x138e + IMX95_PAD_SD2_DATA2__USDHC2_DATA2 0x138e + IMX95_PAD_SD2_DATA3__USDHC2_DATA3 0x138e + IMX95_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { + fsl,pins =3D < + IMX95_PAD_SD2_CLK__USDHC2_CLK 0x158e + IMX95_PAD_SD2_CMD__USDHC2_CMD 0x138e + IMX95_PAD_SD2_DATA0__USDHC2_DATA0 0x138e + IMX95_PAD_SD2_DATA1__USDHC2_DATA1 0x138e + IMX95_PAD_SD2_DATA2__USDHC2_DATA2 0x138e + IMX95_PAD_SD2_DATA3__USDHC2_DATA3 0x138e + IMX95_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins =3D < + IMX95_PAD_SD3_CLK__USDHC3_CLK 0x158e + IMX95_PAD_SD3_CMD__USDHC3_CMD 0x138e + IMX95_PAD_SD3_DATA0__USDHC3_DATA0 0x138e + IMX95_PAD_SD3_DATA1__USDHC3_DATA1 0x138e + IMX95_PAD_SD3_DATA2__USDHC3_DATA2 0x138e + IMX95_PAD_SD3_DATA3__USDHC3_DATA3 0x138e + >; + }; + + pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { + fsl,pins =3D < + IMX95_PAD_SD3_CLK__USDHC3_CLK 0x158e + IMX95_PAD_SD3_CMD__USDHC3_CMD 0x138e + IMX95_PAD_SD3_DATA0__USDHC3_DATA0 0x138e + IMX95_PAD_SD3_DATA1__USDHC3_DATA1 0x138e + IMX95_PAD_SD3_DATA2__USDHC3_DATA2 0x138e + IMX95_PAD_SD3_DATA3__USDHC3_DATA3 0x138e + >; + }; + + pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { + fsl,pins =3D < + IMX95_PAD_SD3_CLK__USDHC3_CLK 0x15fe + IMX95_PAD_SD3_CMD__USDHC3_CMD 0x13fe + IMX95_PAD_SD3_DATA0__USDHC3_DATA0 0x13fe + IMX95_PAD_SD3_DATA1__USDHC3_DATA1 0x13fe + IMX95_PAD_SD3_DATA2__USDHC3_DATA2 0x13fe + IMX95_PAD_SD3_DATA3__USDHC3_DATA3 0x13fe + >; + }; +}; + +&scmi_misc { + nxp,ctrl-ids =3D ; +}; + +&thermal_zones { + pf09-thermal { + polling-delay =3D <2000>; + polling-delay-passive =3D <250>; + thermal-sensors =3D <&scmi_sensor 2>; + + trips { + pf09_alert: trip0 { + hysteresis =3D <2000>; + temperature =3D <140000>; + type =3D "passive"; + }; + + pf09_crit: trip1 { + hysteresis =3D <2000>; + temperature =3D <155000>; + type =3D "critical"; + }; + }; + }; + + pf53arm-thermal { + polling-delay =3D <2000>; + polling-delay-passive =3D <250>; + thermal-sensors =3D <&scmi_sensor 4>; + + cooling-maps { + map0 { + cooling-device =3D <&A55_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&A55_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&A55_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&A55_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&A55_4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&A55_5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + trip =3D <&pf5301_alert>; + }; + }; + + trips { + pf5301_alert: trip0 { + hysteresis =3D <2000>; + temperature =3D <140000>; + type =3D "passive"; + }; + + pf5301_crit: trip1 { + hysteresis =3D <2000>; + temperature =3D <155000>; + type =3D "critical"; + }; + }; + }; + + pf53soc-thermal { + polling-delay =3D <2000>; + polling-delay-passive =3D <250>; + thermal-sensors =3D <&scmi_sensor 3>; + + trips { + pf5302_alert: trip0 { + hysteresis =3D <2000>; + temperature =3D <140000>; + type =3D "passive"; + }; + + pf5302_crit: trip1 { + hysteresis =3D <2000>; + temperature =3D <155000>; + type =3D "critical"; + }; + }; + }; +}; + +&usb2 { + disable-over-current; + dr_mode =3D "host"; + vbus-supply =3D <®_usb_vbus>; + status =3D "okay"; +}; + +&usb3 { + status =3D "okay"; +}; + +&usb3_dwc3 { + adp-disable; + dr_mode =3D "otg"; + hnp-disable; + role-switch-default-mode =3D "peripheral"; + srp-disable; + usb-role-switch; + snps,dis-u1-entry-quirk; + snps,dis-u2-entry-quirk; + status =3D "okay"; + + port { + usb3_data_hs: endpoint { + remote-endpoint =3D <&typec_con_hs>; + }; + }; +}; + +&usb3_phy { + orientation-switch; + fsl,phy-pcs-tx-deemph-3p5db-attenuation-db =3D <17>; + fsl,phy-pcs-tx-swing-full-percent =3D <100>; + fsl,phy-tx-preemp-amp-tune-microamp =3D <600>; + fsl,phy-tx-vboost-level-microvolt =3D <1156>; + fsl,phy-tx-vref-tune-percent =3D <100>; + status =3D "okay"; + + port { + usb3_data_ss: endpoint { + remote-endpoint =3D <&typec_con_ss>; + }; + }; +}; + +&usdhc1 { + bus-width =3D <8>; + non-removable; + no-sd; + no-sdio; + pinctrl-0 =3D <&pinctrl_usdhc1>; + pinctrl-1 =3D <&pinctrl_usdhc1_100mhz>; + pinctrl-2 =3D <&pinctrl_usdhc1_200mhz>; + pinctrl-3 =3D <&pinctrl_usdhc1>; + pinctrl-names =3D "default", "state_100mhz", "state_200mhz", "sleep"; + fsl,tuning-step =3D <1>; + status =3D "okay"; +}; + +&usdhc2 { + bus-width =3D <4>; + cd-gpios =3D <&gpio3 00 GPIO_ACTIVE_LOW>; + pinctrl-0 =3D <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 =3D <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 =3D <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-3 =3D <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-names =3D "default", "state_100mhz", "state_200mhz", "sleep"; + vmmc-supply =3D <®_usdhc2_vmmc>; + fsl,tuning-step =3D <1>; + status =3D "okay"; +}; + +&usdhc3 { + bus-width =3D <4>; + keep-power-in-suspend; + mmc-pwrseq =3D <&usdhc3_pwrseq>; + non-removable; + pinctrl-0 =3D <&pinctrl_usdhc3>; + pinctrl-1 =3D <&pinctrl_usdhc3_100mhz>; + pinctrl-2 =3D <&pinctrl_usdhc3_200mhz>; + pinctrl-3 =3D <&pinctrl_usdhc3>; + pinctrl-names =3D "default", "state_100mhz", "state_200mhz", "sleep"; + vmmc-supply =3D <®_usdhc3_vmmc>; + wakeup-source; + status =3D "okay"; +}; + +&wdog3 { + status =3D "okay"; +}; --=20 2.34.1