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Sat, 6 Dec 2025 04:42:12 -0800 From: Zhi Wang To: , , , CC: , , , , , , , , , , , , , , , , , , , , , , , , , , Zhi Wang Subject: [RFC 4/7] gpu: nova-core: populate GSP_VF_INFO when vGPU is enabled Date: Sat, 6 Dec 2025 12:42:05 +0000 Message-ID: <20251206124208.305963-5-zhiw@nvidia.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20251206124208.305963-1-zhiw@nvidia.com> References: <20251206124208.305963-1-zhiw@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: MWH0EPF000971E2:EE_|CH3PR12MB9342:EE_ X-MS-Office365-Filtering-Correlation-Id: d5e7374e-d1bd-4590-cd2c-08de34c4e7b8 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700013|82310400026|376014|1800799024|7416014; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?t6hnWEZk1l1Zbur0JyxlRwTgGV/6icYPapM7SNWKPlKZNnzDWfj+7m2mF+p2?= =?us-ascii?Q?MwOOK/LtKr9tRnWZAmUZbS3gaHx4NmrOs/TyJuAnWPE9Ez8NKa14uQRfRfr6?= =?us-ascii?Q?YkEiKAzeTizghic4bWn5X4aY93JhQD3/qsuGUmdhz0p9sJXeodB+kdXfyjW8?= =?us-ascii?Q?qGsAYbisaKjE7ZgmGTlEkbZo+JutqtOlJyiLznsmye6tktLjG8dACi4o3WVg?= =?us-ascii?Q?yqDwwmB39hY1jYZUq4/f0rdQpsdXjFV1c62TouX78HtWlGtntRrg18uFxW0i?= =?us-ascii?Q?fF8E+QPw0+YCQoFNaj0evQrVXQq+Sor9WoJZqw8o4v2NmehS2tM/2QIfowJo?= =?us-ascii?Q?D23FosGWstVHmayzEmcI7sidAk+wsWfdEWLMOLU7mEHz+Svwlp02w03CO6v9?= =?us-ascii?Q?Bw0e3cjz8IwBtEVl9XQrbPXeKHo1VRzagWnfZ7mbHeFP/9+UeghSYSMRSc+J?= =?us-ascii?Q?r2fkCxVnrrninjO+mYyoMGxyCTzM6WNIxi1ilLwXREk2tsIqxTPuwBCX9O80?= =?us-ascii?Q?h1vs6k2P9e4qVbuDpm7GFVg9P9olUsEa90I6/YDnQtLHj93bPhbWA2M3EyV8?= =?us-ascii?Q?/TMzrbPvTKg23ozCwZJWeTJt9L4UX8h0uj8swCBaAbn8DB26Gkzb1NATFkFL?= =?us-ascii?Q?QYSAY91tMS7/4H0ruZX2bHVXnfdMSbpBSJ2xt6bRSUXmRD5ZDHfX1U1G4AJ7?= =?us-ascii?Q?TbIru+2p3PRKOsc1bf2tiLoDGi/fXc+nnEJn8pZt/jM9tr04lmO9vuYJKlFj?= =?us-ascii?Q?4d90MzsQ1O7zFptAE+aXH/ENcoC+57k9JDjmSwcaXcVXPbXUiH3Or8s7iCMf?= =?us-ascii?Q?GCIsVFok8315hrt5YKlCcytlxLpbgEsBmP5/H6mBQqtVw/dHGainCeJl6lQl?= =?us-ascii?Q?iLtaTRDXNBstv9/dxuPb9wgAd27Ge9zenwohLjq1um0AXQXANwivqd8D38td?= =?us-ascii?Q?F5CC3l7i3eeu11cXqJn9gGL0tSPbxKyVRUbo1NdNRydHUHjo34vLZBbZdj47?= =?us-ascii?Q?OCqy2BxEOl0Yfm2gaT0uNKQ4GJefKlC0zC51RKXvaiax4ttPlgXAUWCCEtVh?= =?us-ascii?Q?3Hd4oHadwx6/+E8iW9byKiXoRPTVorNbJBOdFxUKzhMakwA9b8HEBe9gY19K?= =?us-ascii?Q?hucyQXtimwQhGihxSxCzvfufKzOIQ57beY65oyNihNdZdbUkJZVEeZSrI2Vb?= =?us-ascii?Q?h9kUIAkTlTUw4b1aR/BQFANk48Yrk97ujjDt9Ui91KTeBmI2EcrX51SiQP6W?= =?us-ascii?Q?a4DlbJia7JWnm8oWUnwh10E6bxzLoaUUtgb4iYC3V5N7jGVNTYEvqqtIil9J?= =?us-ascii?Q?66eSf5Gee5jCuGEPOJW60Lf2GAD8HS+niw1gdqhIw+1qaQryGumVn6oPLbLo?= =?us-ascii?Q?DiEcsAJ1RsygonK56VqB2r14T7NX5fvV3nOTh1tYfNWflDyNtFMgn4D3DV1k?= =?us-ascii?Q?cIC5KHHI5OwqH6kKM2dzozkVXUHLubS/Lgqicca+UfnQmBJ2wVRVa2JRVzqW?= =?us-ascii?Q?8uNY5pWS9NDR+yHx8cf2fJdXDZ4vBNwFGX+Tdl3qTUHsya8duIyj57Mw66GN?= =?us-ascii?Q?fJqy+rm26p8cwjs6uQA=3D?= X-Forefront-Antispam-Report: CIP:216.228.118.232;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge1.nvidia.com;CAT:NONE;SFS:(13230040)(36860700013)(82310400026)(376014)(1800799024)(7416014);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 06 Dec 2025 12:42:23.8188 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: d5e7374e-d1bd-4590-cd2c-08de34c4e7b8 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.232];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: MWH0EPF000971E2.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH3PR12MB9342 Content-Type: text/plain; charset="utf-8" GSP firmware needs to know the VF BAR offsets to correctly calculate the VF events. The VF BAR information is stored in GSP_VF_INFO, which needs to be initialized and uploaded together with the GSP_SYSTEM_INFO. Populate GSP_VF_INFO when nova-core uploads the GSP_SYSTEM_INFO if NVIDIA vGPU is enabled. Signed-off-by: Zhi Wang --- drivers/gpu/nova-core/gpu.rs | 2 +- drivers/gpu/nova-core/gsp.rs | 8 ++- drivers/gpu/nova-core/gsp/boot.rs | 6 +- drivers/gpu/nova-core/gsp/commands.rs | 8 ++- drivers/gpu/nova-core/gsp/fw.rs | 75 ++++++++++++++++++++++++ drivers/gpu/nova-core/gsp/fw/commands.rs | 11 +++- 6 files changed, 102 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/nova-core/gpu.rs b/drivers/gpu/nova-core/gpu.rs index 10c5ae07a891..08a41e7bd982 100644 --- a/drivers/gpu/nova-core/gpu.rs +++ b/drivers/gpu/nova-core/gpu.rs @@ -285,7 +285,7 @@ pub(crate) fn new<'a>( =20 sec2_falcon: Falcon::new(pdev.as_ref(), spec.chipset)?, =20 - gsp <- Gsp::new(pdev)?, + gsp <- Gsp::new(pdev, vgpu.vgpu_support)?, =20 _: { gsp.boot(pdev, bar, spec.chipset, gsp_falcon, sec2_falcon= )? }, =20 diff --git a/drivers/gpu/nova-core/gsp.rs b/drivers/gpu/nova-core/gsp.rs index fb6f74797178..2d9352740c28 100644 --- a/drivers/gpu/nova-core/gsp.rs +++ b/drivers/gpu/nova-core/gsp.rs @@ -115,11 +115,16 @@ pub(crate) struct Gsp { pub(crate) cmdq: Cmdq, /// RM arguments. rmargs: CoherentAllocation, + /// Support vGPU. + vgpu_support: bool, } =20 impl Gsp { // Creates an in-place initializer for a `Gsp` manager for `pdev`. - pub(crate) fn new(pdev: &pci::Device) -> Result> { + pub(crate) fn new( + pdev: &pci::Device, + vgpu_support: bool, + ) -> Result> { let dev =3D pdev.as_ref(); let libos =3D CoherentAllocation:::= :alloc_coherent( dev, @@ -156,6 +161,7 @@ pub(crate) fn new(pdev: &pci::Device) ->= Result, ) -> Result { let dev =3D pdev.as_ref(); + let vgpu_support =3D self.vgpu_support; =20 let bios =3D Vbios::new(dev, bar)?; =20 @@ -162,8 +164,10 @@ pub(crate) fn boot( CoherentAllocation::::alloc_coherent(dev, 1, GFP= _KERNEL | __GFP_ZERO)?; dma_write!(wpr_meta[0] =3D GspFwWprMeta::new(&gsp_fw, &fb_layout))= ?; =20 + let vf_info =3D GspVfInfo::new(pdev, bar, vgpu_support)?; + self.cmdq - .send_command(bar, commands::SetSystemInfo::new(pdev))?; + .send_command(bar, commands::SetSystemInfo::new(pdev, vf_info)= )?; self.cmdq.send_command(bar, commands::SetRegistry::new())?; =20 gsp_falcon.reset(bar)?; diff --git a/drivers/gpu/nova-core/gsp/commands.rs b/drivers/gpu/nova-core/= gsp/commands.rs index 0425c65b5d6f..1d519c4ed232 100644 --- a/drivers/gpu/nova-core/gsp/commands.rs +++ b/drivers/gpu/nova-core/gsp/commands.rs @@ -26,6 +26,7 @@ }, fw::{ commands::*, + GspVfInfo, MsgFunction, // }, }, @@ -36,12 +37,13 @@ /// The `GspSetSystemInfo` command. pub(crate) struct SetSystemInfo<'a> { pdev: &'a pci::Device, + vf_info: GspVfInfo, } =20 impl<'a> SetSystemInfo<'a> { /// Creates a new `GspSetSystemInfo` command using the parameters of `= pdev`. - pub(crate) fn new(pdev: &'a pci::Device) -> Self { - Self { pdev } + pub(crate) fn new(pdev: &'a pci::Device, vf_info: GspVf= Info) -> Self { + Self { pdev, vf_info } } } =20 @@ -51,7 +53,7 @@ impl<'a> CommandToGsp for SetSystemInfo<'a> { type InitError =3D Error; =20 fn init(&self) -> impl Init { - GspSetSystemInfo::init(self.pdev) + GspSetSystemInfo::init(self.pdev, self.vf_info) } } =20 diff --git a/drivers/gpu/nova-core/gsp/fw.rs b/drivers/gpu/nova-core/gsp/fw= .rs index abffd6beec65..a0581ac34586 100644 --- a/drivers/gpu/nova-core/gsp/fw.rs +++ b/drivers/gpu/nova-core/gsp/fw.rs @@ -9,8 +9,10 @@ use core::ops::Range; =20 use kernel::{ + device, dma::CoherentAllocation, fmt, + pci, prelude::*, ptr::{ Alignable, @@ -27,6 +29,7 @@ }; =20 use crate::{ + driver::Bar0, fb::FbLayout, firmware::gsp::GspFirmware, gpu::Chipset, @@ -926,3 +929,75 @@ fn new(cmdq: &Cmdq) -> Self { }) } } + +/// VF information - gspVFInfo in SetSystemInfo. +#[derive(Clone, Copy, Zeroable)] +#[repr(transparent)] +pub(crate) struct GspVfInfo { + inner: bindings::GSP_VF_INFO, +} + +impl GspVfInfo { + /// Creates a new GspVfInfo structure. + pub(crate) fn new<'a>( + pdev: &'a pci::Device, + bar: &Bar0, + vgpu_support: bool, + ) -> Result { + let mut vf_info =3D GspVfInfo::zeroed(); + let info =3D &mut vf_info.inner; + + if vgpu_support { + let val =3D pdev.sriov_get_totalvfs()?; + info.totalVFs =3D u32::try_from(val)?; + + let pos =3D pdev + .find_ext_capability(kernel::bindings::PCI_EXT_CAP_ID_SRIO= V as i32) + .ok_or(ENODEV)?; + + let val =3D pdev.config_read_word( + i32::from(pos) + i32::from(kernel::bindings::PCI_SRIOV_VF_= OFFSET as i32), + )?; + info.firstVFOffset =3D u32::from(val); + + let val =3D pdev.config_read_dword( + i32::from(pos) + i32::from(kernel::bindings::PCI_SRIOV_BAR= as i32), + )?; + info.FirstVFBar0Address =3D u64::from(val); + + let bar1_lo =3D pdev.config_read_dword( + i32::from(pos) + i32::from(kernel::bindings::PCI_SRIOV_BAR= as i32 + 4), + )?; + let bar1_hi =3D pdev.config_read_dword( + i32::from(pos) + i32::from(kernel::bindings::PCI_SRIOV_BAR= as i32 + 8), + )?; + + let addr_mask =3D u64::try_from(kernel::bindings::PCI_BASE_ADD= RESS_MEM_MASK)?; + + info.FirstVFBar1Address =3D + (u64::from(bar1_hi) << 32) | ((u64::from(bar1_lo)) & addr_= mask); + + let bar2_lo =3D pdev.config_read_dword( + i32::from(pos) + i32::from(kernel::bindings::PCI_SRIOV_BAR= as i32 + 12), + )?; + let bar2_hi =3D pdev.config_read_dword( + i32::from(pos) + i32::from(kernel::bindings::PCI_SRIOV_BAR= as i32 + 16), + )?; + + info.FirstVFBar2Address =3D (u64::from(bar2_hi) << 32) | (u64:= :from(bar2_lo) & addr_mask); + + let val =3D bar.read32(0x88000 + 0xbf4); + info.b64bitBar1 =3D u8::from((val & 0x00000006) =3D=3D 0x00000= 004); + + let val =3D bar.read32(0x88000 + 0xbfc); + info.b64bitBar2 =3D u8::from((val & 0x00000006) =3D=3D 0x00000= 004); + } + Ok(vf_info) + } +} + +// SAFETY: Padding is explicit and does not contain uninitialized data. +unsafe impl AsBytes for GspVfInfo {} + +// SAFETY: This struct only contains integer types for which all bit patte= rns are valid. +unsafe impl FromBytes for GspVfInfo {} diff --git a/drivers/gpu/nova-core/gsp/fw/commands.rs b/drivers/gpu/nova-co= re/gsp/fw/commands.rs index 21be44199693..3b5c05704b2d 100644 --- a/drivers/gpu/nova-core/gsp/fw/commands.rs +++ b/drivers/gpu/nova-core/gsp/fw/commands.rs @@ -4,7 +4,10 @@ use kernel::transmute::{AsBytes, FromBytes}; use kernel::{device, pci}; =20 -use crate::gsp::GSP_PAGE_SIZE; +use crate::gsp::{ + fw::GspVfInfo, + GSP_PAGE_SIZE, // +}; =20 use super::bindings; =20 @@ -18,7 +21,10 @@ pub(crate) struct GspSetSystemInfo { impl GspSetSystemInfo { /// Returns an in-place initializer for the `GspSetSystemInfo` command. #[allow(non_snake_case)] - pub(crate) fn init<'a>(dev: &'a pci::Device) -> impl In= it + 'a { + pub(crate) fn init<'a>( + dev: &'a pci::Device, + info: GspVfInfo, + ) -> impl Init + 'a { type InnerGspSystemInfo =3D bindings::GspSystemInfo; let init_inner =3D try_init!(InnerGspSystemInfo { gpuPhysAddr: dev.resource_start(0)?, @@ -38,6 +44,7 @@ pub(crate) fn init<'a>(dev: &'a pci::Device) -> impl Init