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Sat, 6 Dec 2025 04:42:12 -0800 From: Zhi Wang To: , , , CC: , , , , , , , , , , , , , , , , , , , , , , , , , , Zhi Wang Subject: [RFC 2/7] [!UPSTREAM] rust: pci: support configuration space access Date: Sat, 6 Dec 2025 12:42:03 +0000 Message-ID: <20251206124208.305963-3-zhiw@nvidia.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20251206124208.305963-1-zhiw@nvidia.com> References: <20251206124208.305963-1-zhiw@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH1PEPF0000AD7F:EE_|MW6PR12MB7069:EE_ X-MS-Office365-Filtering-Correlation-Id: 86b8f347-5297-4302-e022-08de34c4e577 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700013|1800799024|82310400026|7416014|376014|13003099007; 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 06 Dec 2025 12:42:19.9882 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 86b8f347-5297-4302-e022-08de34c4e577 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.233];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CH1PEPF0000AD7F.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MW6PR12MB7069 Content-Type: text/plain; charset="utf-8" The work is WIP at [1]. Link: https://lore.kernel.org/all/20251119112117.116979-1-zhiw@nvidia.com/ = [1] Signed-off-by: Zhi Wang --- rust/kernel/pci.rs | 34 ++++++++++++++++++++++++++++++++++ 1 file changed, 34 insertions(+) diff --git a/rust/kernel/pci.rs b/rust/kernel/pci.rs index 9a82e83dfd30..e7fdded9d746 100644 --- a/rust/kernel/pci.rs +++ b/rust/kernel/pci.rs @@ -526,6 +526,40 @@ pub fn sriov_get_totalvfs(&self) -> Result { Err(ENODEV) } } + + /// Find the extended capability + pub fn find_ext_capability(&self, cap: i32) -> Option { + // SAFETY: `self.as_raw()` is a valid pointer to a `struct pci_dev= `. + let offset =3D unsafe { bindings::pci_find_ext_capability(self.as_= raw(), cap) }; + if offset !=3D 0 { + Some(offset as u16) + } else { + None + } + } + + /// Read configuration space by word + pub fn config_read_word(&self, where_: i32) -> Result { + let mut val: u16 =3D 0; + + // SAFETY: `self.as_raw()` is a valid pointer to `struct pci_dev`, + // and `&mut val` is a valid pointer to writable memory. + to_result(unsafe { + bindings::pci_read_config_word(self.as_raw(), where_, &mut val) + })?; + + Ok(val) + } + + /// Read configuration space by dword + pub fn config_read_dword(&self, where_: i32) -> Result { + let mut val: u32 =3D 0; + // SAFETY: `self.as_raw()` is a valid pointer to `struct pci_dev`, + // and `&mut val` is a valid pointer to writable memory. + to_result(unsafe { bindings::pci_read_config_dword(self.as_raw(), = where_, &mut val) })?; + + Ok(val) + } } =20 impl Device { --=20 2.51.0