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(unknown [58.22.7.114]) by smtp.qiye.163.com (Hmail) with ESMTP id 2c3493a70; Sat, 6 Dec 2025 13:08:55 +0800 (GMT+08:00) From: Ye Zhang To: Ye Zhang , Linus Walleij , Heiko Stuebner Cc: Bartosz Golaszewski , Rob Herring , Krzysztof Kozlowski , Conor Dooley , linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, tao.huang@rock-chips.com Subject: [PATCH v2 7/8] dt-bindings: pinctrl: rockchip: Add RMIO controller binding Date: Sat, 6 Dec 2025 13:08:43 +0800 Message-Id: <20251206050844.402958-8-ye.zhang@rock-chips.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20251206050844.402958-1-ye.zhang@rock-chips.com> References: <20251206050844.402958-1-ye.zhang@rock-chips.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-HM-Tid: 0a9af210229409d8kunmae94618c4ed3f36 X-HM-MType: 1 X-HM-Spam-Status: e1kfGhgUHx5ZQUpXWQgPGg8OCBgUHx5ZQUlOS1dZFg8aDwILHllBWSg2Ly tZV1koWUFDSUNOT01LS0k3V1ktWUFJV1kPCRoVCBIfWUFZGhkaS1ZIHUxPTBlKTBhITB1WFRQJFh oXVRMBExYaEhckFA4PWVdZGBILWUFZTkNVSUlVTFVKSk9ZV1kWGg8SFR0UWUFZT0tIVUpLSU9PT0 hVSktLVUpCS0tZBg++ DKIM-Signature: a=rsa-sha256; b=Nahoi33a9W7LKo9zBZsKTBZmqp6NoX79vHrjDvTS7bhW0RXV/xE8MzpUWWK+x16thFH0Zj18qnxkaLMNOZfwhCz89tX4j4xtL4hcnuIidmUY9ytLTBlXBE81klggfepXLlIUgBmyWi9mQHQQSOPAByDC4et3+FZrW1EKeuJS0NU=; s=default; c=relaxed/relaxed; d=rock-chips.com; v=1; bh=B8Pv8F+oXHHjCE0zxtFanqIKrinBiYf5cSRDVL4WFrI=; h=date:mime-version:subject:message-id:from; Content-Type: text/plain; charset="utf-8" Add device tree binding for the RMIO (Rockchip Matrix I/O) controller which is a sub-device of the main pinctrl on some Rockchip SoCs. Signed-off-by: Ye Zhang --- .../bindings/pinctrl/rockchip,pinctrl.yaml | 9 ++ .../bindings/pinctrl/rockchip,rmio.yaml | 130 ++++++++++++++++++ 2 files changed, 139 insertions(+) create mode 100644 Documentation/devicetree/bindings/pinctrl/rockchip,rmio= .yaml diff --git a/Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.yam= l b/Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.yaml index 93bf8f352e48..01df0a51ff83 100644 --- a/Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.yaml @@ -83,6 +83,15 @@ required: - rockchip,grf =20 patternProperties: + "rmio[0-9]*$": + type: object + + $ref: "/schemas/pinctrl/rockchip,rmio.yaml#" + + description: + The RMIO (Rockchip Matrix I/O) controller node which functions as a + sub-device of the main pinctrl to handle flexible function routing. + "gpio@[0-9a-f]+$": type: object =20 diff --git a/Documentation/devicetree/bindings/pinctrl/rockchip,rmio.yaml b= /Documentation/devicetree/bindings/pinctrl/rockchip,rmio.yaml new file mode 100644 index 000000000000..28ec5ad62061 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/rockchip,rmio.yaml @@ -0,0 +1,130 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/rockchip,rmio.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: RMIO (Rockchip Matrix I/O) Controller + +maintainers: + - Heiko Stuebner + +description: | + The RMIO controller provides a flexible routing matrix that allows mappi= ng + various internal peripheral functions (UART, SPI, PWM, etc.) to specific + physical pins. This block is typically a sub-block of the GRF + (General Register Files). + +properties: + compatible: + enum: + - rockchip,rmio + + rockchip,grf: + $ref: /schemas/types.yaml#/definitions/phandle + description: + The phandle of the syscon node for the GRF registers. + + rockchip,offset: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + The offset of the RMIO configuration registers within the GRF. + + rockchip,pins-num: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + The number of physical pins supported by this RMIO instance. + Used for boundary checking and driver initialization. + +additionalProperties: + type: object + additionalProperties: + type: object + properties: + rockchip,rmio: + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" + description: | + A list of pin-function pairs. The format is . + - pin_id: The index of the RMIO pin (0 to pins-num - 1). + - function_id: The mux value selecting the peripheral function. + minItems: 1 + items: + items: + - minimum: 0 + maximum: 31 + description: + RMIO Pin ID. + - minimum: 0 + maximum: 98 + description: + Function ID. + + required: + - rockchip,rmio + + additionalProperties: false + + additionalProperties: false + +required: + - compatible + - rockchip,grf + - rockchip,offset + - rockchip,pins-num + +additionalProperties: false + +examples: + - | + #include + #include + #include + + pinctrl { + #address-cells =3D <1>; + #size-cells =3D <1>; + ranges; + + rmio { + compatible =3D "rockchip,rmio"; + rockchip,grf =3D <&grf_pmu>; + rockchip,offset =3D <0x80>; + rockchip,pins-num =3D <32>; + + rmio-uart { + rmio_pin27_uart1_tx: rmio-pin27-uart1-tx { + rockchip,rmio =3D ; + }; + + rmio_pin28_uart1_rx: rmio-pin28-uart1-rx { + rockchip,rmio =3D ; + }; + }; + }; + + pcfg_pull_default: pcfg-pull-default { + bias-pull-pin-default; + }; + + rm { + rmio_pin27_pins: rmio-pin27-pins { + rockchip,pins =3D <1 RK_PC2 7 &pcfg-pull-default>; + }; + + rmio_pin28_pins: rmio-pin28-pins { + rockchip,pins =3D <1 RK_PC3 7 &pcfg-pull-default>; + }; + }; + }; + + uart1: serial@20064000 { + compatible =3D "snps,dw-apb-uart"; + reg =3D <0x20064000 0x400>; + interrupts =3D ; + clocks =3D <&mux_uart2>; + pinctrl-0 =3D <&rmio_pin27_pins &rmio_pin27_uart1_tx + &rmio_pin28_pins &rmio_pin28_uart1_rx>; + pinctrl-names =3D "default"; + reg-io-width =3D <1>; + reg-shift =3D <2>; + }; --=20 2.34.1