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(unknown [58.22.7.114]) by smtp.qiye.163.com (Hmail) with ESMTP id 2c3493a61; Sat, 6 Dec 2025 13:08:47 +0800 (GMT+08:00) From: Ye Zhang To: Ye Zhang , Linus Walleij , Heiko Stuebner Cc: Bartosz Golaszewski , Rob Herring , Krzysztof Kozlowski , Conor Dooley , linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, tao.huang@rock-chips.com, Krzysztof Kozlowski Subject: [PATCH v2 1/8] dt-bindings: pinctrl: Add rk3506 pinctrl support Date: Sat, 6 Dec 2025 13:08:37 +0800 Message-Id: <20251206050844.402958-2-ye.zhang@rock-chips.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20251206050844.402958-1-ye.zhang@rock-chips.com> References: <20251206050844.402958-1-ye.zhang@rock-chips.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-HM-Tid: 0a9af21006a009d8kunmae94618c4ed3ae7 X-HM-MType: 1 X-HM-Spam-Status: e1kfGhgUHx5ZQUpXWQgPGg8OCBgUHx5ZQUlOS1dZFg8aDwILHllBWSg2Ly tZV1koWUFDSUNOT01LS0k3V1ktWUFJV1kPCRoVCBIfWUFZGRkdHVZJGBhDGU9MQk1IGE5WFRQJFh oXVRMBExYaEhckFA4PWVdZGBILWUFZTkNVSUlVTFVKSk9ZV1kWGg8SFR0UWUFZT0tIVUpLSU9PT0 hVSktLVUpCS0tZBg++ DKIM-Signature: a=rsa-sha256; b=bG+/oVHC+FD2dNeKBHi7ZwwuxQRf9EpErKon41AD7ic+dUl+vm7z44dwS/EnRlYYtxLLGWyrErjWN0O2iH6pJ+20tb1tlfYNuJ+vVmIQRiQLQyYfZHHz3DK3JlhmWwr9ZleG1iyr1xA5+bDGNX0pRX5lXQurCrOCcBL+j292TRs=; s=default; c=relaxed/relaxed; d=rock-chips.com; v=1; bh=0Db2q6dT/j6RKhINW0J1Xu2aTYUEmZfbY9ZOLYGcFW8=; h=date:mime-version:subject:message-id:from; Content-Type: text/plain; charset="utf-8" Add the compatible string for the rk3506 SoC. Signed-off-by: Ye Zhang Reviewed-by: Heiko Stuebner Acked-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.yam= l b/Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.yaml index 125af766b992..76e607281716 100644 --- a/Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.yaml @@ -44,6 +44,7 @@ properties: - rockchip,rk3328-pinctrl - rockchip,rk3368-pinctrl - rockchip,rk3399-pinctrl + - rockchip,rk3506-pinctrl - rockchip,rk3528-pinctrl - rockchip,rk3562-pinctrl - rockchip,rk3568-pinctrl --=20 2.34.1 From nobody Fri Dec 19 13:27:15 2025 Received: from mail-m32105.qiye.163.com (mail-m32105.qiye.163.com [220.197.32.105]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DEDC4335BA; Sat, 6 Dec 2025 05:14:08 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=220.197.32.105 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764998054; cv=none; b=VSlTYLkrX7zA1FyVYfE8gEx9jjwgUK9aCC3+zMq8H2sfWOx7eRPlOoTWlnDnZeW0r0O1J+RYuuWGHXr6LKxhn8CB14FkhzRhaZw56PKNVgI106TGaglRinVyOXUUeU6zoRhWTJ/3dNClHd54KD/7KNxF0n0pVDCPIaXwKvn46pE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764998054; c=relaxed/simple; bh=XOexQ5hlnXdavhUJmYRHc7U1EauUvzEOVZSF0eROBHc=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=fI7sYUlDX5zD6EpsZfwS7LTDNvLQlSjZei1wA8GP8CI9rA9fSH7eIsrSsxBfMedm1ytDa/6ZaZlN/z5w1hVFt8nUcD6yM3A/Ca9/LmAt08tL0lhwowtGlMNPWO3EMJkNFReDC1liPuINaJMFgR2fAgdaZfNckOzV3EG7riuvhjc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=rock-chips.com; spf=pass smtp.mailfrom=rock-chips.com; dkim=pass (1024-bit key) header.d=rock-chips.com header.i=@rock-chips.com header.b=JiKSCcGS; arc=none smtp.client-ip=220.197.32.105 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=rock-chips.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=rock-chips.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=rock-chips.com header.i=@rock-chips.com header.b="JiKSCcGS" Received: from rockchip.. (unknown [58.22.7.114]) by smtp.qiye.163.com (Hmail) with ESMTP id 2c3493a66; Sat, 6 Dec 2025 13:08:49 +0800 (GMT+08:00) From: Ye Zhang To: Ye Zhang , Linus Walleij , Heiko Stuebner Cc: Bartosz Golaszewski , Rob Herring , Krzysztof Kozlowski , Conor Dooley , linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, tao.huang@rock-chips.com Subject: [PATCH v2 2/8] pinctrl: rockchip: Add rk3506 pinctrl support Date: Sat, 6 Dec 2025 13:08:38 +0800 Message-Id: <20251206050844.402958-3-ye.zhang@rock-chips.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20251206050844.402958-1-ye.zhang@rock-chips.com> References: <20251206050844.402958-1-ye.zhang@rock-chips.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-HM-Tid: 0a9af2100b2d09d8kunmae94618c4ed3b9c X-HM-MType: 1 X-HM-Spam-Status: e1kfGhgUHx5ZQUpXWQgPGg8OCBgUHx5ZQUlOS1dZFg8aDwILHllBWSg2Ly tZV1koWUFDSUNOT01LS0k3V1ktWUFJV1kPCRoVCBIfWUFZGhgZH1ZKSh5OT00dHUpMGE9WFRQJFh oXVRMBExYaEhckFA4PWVdZGBILWUFZTkNVSUlVTFVKSk9ZV1kWGg8SFR0UWUFZT0tIVUpLSU9PT0 hVSktLVUpCS0tZBg++ DKIM-Signature: a=rsa-sha256; b=JiKSCcGStRG94X8kMe2nkzxUNVc1Lvf79o3Dh0+y83fEgAugfRxe3pjV02uM2q3NkTIquqnaEQMG31OE4ZpoF/ou1rvU9DfzAv2kKRnKBxqnCgInpBEzaoAq2+FyCIoBRKj6GwbzOclrpLMfNkFSHG1o8TzrV7T+GzO2JLkBJZE=; s=default; c=relaxed/relaxed; d=rock-chips.com; v=1; bh=UhD05hwlid+LlXChcaogni/DiSxKRWXnvTa8XueHSaQ=; h=date:mime-version:subject:message-id:from; Content-Type: text/plain; charset="utf-8" Add support for the 5 rk3506 GPIO banks. Signed-off-by: Ye Zhang Reviewed-by: Heiko Stuebner --- drivers/pinctrl/pinctrl-rockchip.c | 442 ++++++++++++++++++++++++++++- drivers/pinctrl/pinctrl-rockchip.h | 4 + 2 files changed, 438 insertions(+), 8 deletions(-) diff --git a/drivers/pinctrl/pinctrl-rockchip.c b/drivers/pinctrl/pinctrl-r= ockchip.c index 7a68a6237649..e44ef262beec 100644 --- a/drivers/pinctrl/pinctrl-rockchip.c +++ b/drivers/pinctrl/pinctrl-rockchip.c @@ -105,6 +105,29 @@ .pull_type[3] =3D pull3, \ } =20 +#define PIN_BANK_IOMUX_FLAGS_OFFSET_DRV_FLAGS(id, pins, label, iom0, \ + iom1, iom2, iom3, \ + offset0, offset1, \ + offset2, offset3, drv0, \ + drv1, drv2, drv3) \ + { \ + .bank_num =3D id, \ + .nr_pins =3D pins, \ + .name =3D label, \ + .iomux =3D { \ + { .type =3D iom0, .offset =3D offset0 }, \ + { .type =3D iom1, .offset =3D offset1 }, \ + { .type =3D iom2, .offset =3D offset2 }, \ + { .type =3D iom3, .offset =3D offset3 }, \ + }, \ + .drv =3D { \ + { .drv_type =3D drv0, .offset =3D -1 }, \ + { .drv_type =3D drv1, .offset =3D -1 }, \ + { .drv_type =3D drv2, .offset =3D -1 }, \ + { .drv_type =3D drv3, .offset =3D -1 }, \ + }, \ + } + #define PIN_BANK_DRV_FLAGS(id, pins, label, type0, type1, type2, type3) \ { \ .bank_num =3D id, \ @@ -233,6 +256,35 @@ .pull_type[3] =3D pull3, \ } =20 +#define PIN_BANK_IOMUX_FLAGS_OFFSET_DRV_FLAGS_PULL_FLAGS(id, pins, \ + label, iom0, iom1, \ + iom2, iom3, offset0, \ + offset1, offset2, \ + offset3, drv0, drv1, \ + drv2, drv3, pull0, \ + pull1, pull2, pull3) \ + { \ + .bank_num =3D id, \ + .nr_pins =3D pins, \ + .name =3D label, \ + .iomux =3D { \ + { .type =3D iom0, .offset =3D offset0 }, \ + { .type =3D iom1, .offset =3D offset1 }, \ + { .type =3D iom2, .offset =3D offset2 }, \ + { .type =3D iom3, .offset =3D offset3 }, \ + }, \ + .drv =3D { \ + { .drv_type =3D drv0, .offset =3D -1 }, \ + { .drv_type =3D drv1, .offset =3D -1 }, \ + { .drv_type =3D drv2, .offset =3D -1 }, \ + { .drv_type =3D drv3, .offset =3D -1 }, \ + }, \ + .pull_type[0] =3D pull0, \ + .pull_type[1] =3D pull1, \ + .pull_type[2] =3D pull2, \ + .pull_type[3] =3D pull3, \ + } + #define PIN_BANK_MUX_ROUTE_FLAGS(ID, PIN, FUNC, REG, VAL, FLAG) \ { \ .bank_num =3D ID, \ @@ -1120,6 +1172,13 @@ static int rockchip_get_mux(struct rockchip_pin_bank= *bank, int pin) else regmap =3D info->regmap_base; =20 + if (ctrl->type =3D=3D RK3506) { + if (bank->bank_num =3D=3D 1) + regmap =3D info->regmap_ioc1; + else if (bank->bank_num =3D=3D 4) + return 0; + } + /* get basic quadrupel of mux registers and the correct reg inside */ mux_type =3D bank->iomux[iomux_num].type; reg =3D bank->iomux[iomux_num].offset; @@ -1239,6 +1298,13 @@ static int rockchip_set_mux(struct rockchip_pin_bank= *bank, int pin, int mux) else regmap =3D info->regmap_base; =20 + if (ctrl->type =3D=3D RK3506) { + if (bank->bank_num =3D=3D 1) + regmap =3D info->regmap_ioc1; + else if (bank->bank_num =3D=3D 4) + return 0; + } + /* get basic quadrupel of mux registers and the correct reg inside */ mux_type =3D bank->iomux[iomux_num].type; reg =3D bank->iomux[iomux_num].offset; @@ -2003,6 +2069,262 @@ static int rk3399_calc_drv_reg_and_bit(struct rockc= hip_pin_bank *bank, return 0; } =20 +#define RK3506_DRV_BITS_PER_PIN 8 +#define RK3506_DRV_PINS_PER_REG 2 +#define RK3506_DRV_GPIO0_A_OFFSET 0x100 +#define RK3506_DRV_GPIO0_D_OFFSET 0x830 +#define RK3506_DRV_GPIO1_OFFSET 0x140 +#define RK3506_DRV_GPIO2_OFFSET 0x180 +#define RK3506_DRV_GPIO3_OFFSET 0x1c0 +#define RK3506_DRV_GPIO4_OFFSET 0x840 + +static int rk3506_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, + int pin_num, struct regmap **regmap, + int *reg, u8 *bit) +{ + struct rockchip_pinctrl *info =3D bank->drvdata; + int ret =3D 0; + + switch (bank->bank_num) { + case 0: + *regmap =3D info->regmap_pmu; + if (pin_num > 24) { + ret =3D -EINVAL; + } else if (pin_num < 24) { + *reg =3D RK3506_DRV_GPIO0_A_OFFSET; + } else { + *reg =3D RK3506_DRV_GPIO0_D_OFFSET; + *bit =3D 3; + + return 0; + } + break; + + case 1: + *regmap =3D info->regmap_ioc1; + if (pin_num < 28) + *reg =3D RK3506_DRV_GPIO1_OFFSET; + else + ret =3D -EINVAL; + break; + + case 2: + *regmap =3D info->regmap_base; + if (pin_num < 17) + *reg =3D RK3506_DRV_GPIO2_OFFSET; + else + ret =3D -EINVAL; + break; + + case 3: + *regmap =3D info->regmap_base; + if (pin_num < 15) + *reg =3D RK3506_DRV_GPIO3_OFFSET; + else + ret =3D -EINVAL; + break; + + case 4: + *regmap =3D info->regmap_base; + if (pin_num < 8 || pin_num > 11) { + ret =3D -EINVAL; + } else { + *reg =3D RK3506_DRV_GPIO4_OFFSET; + *bit =3D 10; + + return 0; + } + break; + + default: + ret =3D -EINVAL; + break; + } + + if (ret) { + dev_err(info->dev, "unsupported bank_num %d pin_num %d\n", bank->bank_nu= m, pin_num); + + return ret; + } + + *reg +=3D ((pin_num / RK3506_DRV_PINS_PER_REG) * 4); + *bit =3D pin_num % RK3506_DRV_PINS_PER_REG; + *bit *=3D RK3506_DRV_BITS_PER_PIN; + + return 0; +} + +#define RK3506_PULL_BITS_PER_PIN 2 +#define RK3506_PULL_PINS_PER_REG 8 +#define RK3506_PULL_GPIO0_A_OFFSET 0x200 +#define RK3506_PULL_GPIO0_D_OFFSET 0x830 +#define RK3506_PULL_GPIO1_OFFSET 0x210 +#define RK3506_PULL_GPIO2_OFFSET 0x220 +#define RK3506_PULL_GPIO3_OFFSET 0x230 +#define RK3506_PULL_GPIO4_OFFSET 0x840 + +static int rk3506_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, + int pin_num, struct regmap **regmap, + int *reg, u8 *bit) +{ + struct rockchip_pinctrl *info =3D bank->drvdata; + int ret =3D 0; + + switch (bank->bank_num) { + case 0: + *regmap =3D info->regmap_pmu; + if (pin_num > 24) { + ret =3D -EINVAL; + } else if (pin_num < 24) { + *reg =3D RK3506_PULL_GPIO0_A_OFFSET; + } else { + *reg =3D RK3506_PULL_GPIO0_D_OFFSET; + *bit =3D 5; + + return 0; + } + break; + + case 1: + *regmap =3D info->regmap_ioc1; + if (pin_num < 28) + *reg =3D RK3506_PULL_GPIO1_OFFSET; + else + ret =3D -EINVAL; + break; + + case 2: + *regmap =3D info->regmap_base; + if (pin_num < 17) + *reg =3D RK3506_PULL_GPIO2_OFFSET; + else + ret =3D -EINVAL; + break; + + case 3: + *regmap =3D info->regmap_base; + if (pin_num < 15) + *reg =3D RK3506_PULL_GPIO3_OFFSET; + else + ret =3D -EINVAL; + break; + + case 4: + *regmap =3D info->regmap_base; + if (pin_num < 8 || pin_num > 11) { + ret =3D -EINVAL; + } else { + *reg =3D RK3506_PULL_GPIO4_OFFSET; + *bit =3D 13; + + return 0; + } + break; + + default: + ret =3D -EINVAL; + break; + } + + if (ret) { + dev_err(info->dev, "unsupported bank_num %d pin_num %d\n", bank->bank_nu= m, pin_num); + + return ret; + } + + *reg +=3D ((pin_num / RK3506_PULL_PINS_PER_REG) * 4); + *bit =3D pin_num % RK3506_PULL_PINS_PER_REG; + *bit *=3D RK3506_PULL_BITS_PER_PIN; + + return 0; +} + +#define RK3506_SMT_BITS_PER_PIN 1 +#define RK3506_SMT_PINS_PER_REG 8 +#define RK3506_SMT_GPIO0_A_OFFSET 0x400 +#define RK3506_SMT_GPIO0_D_OFFSET 0x830 +#define RK3506_SMT_GPIO1_OFFSET 0x410 +#define RK3506_SMT_GPIO2_OFFSET 0x420 +#define RK3506_SMT_GPIO3_OFFSET 0x430 +#define RK3506_SMT_GPIO4_OFFSET 0x840 + +static int rk3506_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank, + int pin_num, + struct regmap **regmap, + int *reg, u8 *bit) +{ + struct rockchip_pinctrl *info =3D bank->drvdata; + int ret =3D 0; + + switch (bank->bank_num) { + case 0: + *regmap =3D info->regmap_pmu; + if (pin_num > 24) { + ret =3D -EINVAL; + } else if (pin_num < 24) { + *reg =3D RK3506_SMT_GPIO0_A_OFFSET; + } else { + *reg =3D RK3506_SMT_GPIO0_D_OFFSET; + *bit =3D 9; + + return 0; + } + break; + + case 1: + *regmap =3D info->regmap_ioc1; + if (pin_num < 28) + *reg =3D RK3506_SMT_GPIO1_OFFSET; + else + ret =3D -EINVAL; + break; + + case 2: + *regmap =3D info->regmap_base; + if (pin_num < 17) + *reg =3D RK3506_SMT_GPIO2_OFFSET; + else + ret =3D -EINVAL; + break; + + case 3: + *regmap =3D info->regmap_base; + if (pin_num < 15) + *reg =3D RK3506_SMT_GPIO3_OFFSET; + else + ret =3D -EINVAL; + break; + + case 4: + *regmap =3D info->regmap_base; + if (pin_num < 8 || pin_num > 11) { + ret =3D -EINVAL; + } else { + *reg =3D RK3506_SMT_GPIO4_OFFSET; + *bit =3D 8; + + return 0; + } + break; + + default: + ret =3D -EINVAL; + break; + } + + if (ret) { + dev_err(info->dev, "unsupported bank_num %d pin_num %d\n", bank->bank_nu= m, pin_num); + + return ret; + } + + *reg +=3D ((pin_num / RK3506_SMT_PINS_PER_REG) * 4); + *bit =3D pin_num % RK3506_SMT_PINS_PER_REG; + *bit *=3D RK3506_SMT_BITS_PER_PIN; + + return 0; +} + #define RK3528_DRV_BITS_PER_PIN 8 #define RK3528_DRV_PINS_PER_REG 2 #define RK3528_DRV_GPIO0_OFFSET 0x100 @@ -2749,7 +3071,8 @@ static int rockchip_set_drive_perpin(struct rockchip_= pin_bank *bank, rmask_bits =3D RK3588_DRV_BITS_PER_PIN; ret =3D strength; goto config; - } else if (ctrl->type =3D=3D RK3528 || + } else if (ctrl->type =3D=3D RK3506 || + ctrl->type =3D=3D RK3528 || ctrl->type =3D=3D RK3562 || ctrl->type =3D=3D RK3568) { rmask_bits =3D RK3568_DRV_BITS_PER_PIN; @@ -2828,12 +3151,37 @@ static int rockchip_set_drive_perpin(struct rockchi= p_pin_bank *bank, case DRV_TYPE_IO_1V8_ONLY: rmask_bits =3D RK3288_DRV_BITS_PER_PIN; break; + case DRV_TYPE_IO_LEVEL_2_BIT: + ret =3D regmap_read(regmap, reg, &data); + if (ret) + return ret; + data >>=3D bit; + + return data & 0x3; + case DRV_TYPE_IO_LEVEL_8_BIT: + ret =3D regmap_read(regmap, reg, &data); + if (ret) + return ret; + data >>=3D bit; + data &=3D (1 << 8) - 1; + + ret =3D hweight8(data); + if (ret > 0) + return ret - 1; + else + return -EINVAL; default: dev_err(dev, "unsupported pinctrl drive type: %d\n", drv_type); return -EINVAL; } =20 config: + if (ctrl->type =3D=3D RK3506) { + if ((bank->bank_num =3D=3D 0 && pin_num =3D=3D 24) || bank->bank_num =3D= =3D 4) { + rmask_bits =3D 2; + ret =3D strength; + } + } /* enable the write to the equivalent lower bits */ data =3D ((1 << rmask_bits) - 1) << (bit + 16); rmask =3D data | (data >> 16); @@ -2957,6 +3305,7 @@ static int rockchip_set_pull(struct rockchip_pin_bank= *bank, case RK3328: case RK3368: case RK3399: + case RK3506: case RK3528: case RK3562: case RK3568: @@ -3077,6 +3426,10 @@ static int rockchip_get_schmitt(struct rockchip_pin_= bank *bank, int pin_num) break; } =20 + if (ctrl->type =3D=3D RK3506) + if ((bank->bank_num =3D=3D 0 && pin_num =3D=3D 24) || bank->bank_num = =3D=3D 4) + return data & 0x3; + return data & 0x1; } =20 @@ -3112,6 +3465,14 @@ static int rockchip_set_schmitt(struct rockchip_pin_= bank *bank, break; } =20 + if (ctrl->type =3D=3D RK3506) { + if ((bank->bank_num =3D=3D 0 && pin_num =3D=3D 24) || bank->bank_num =3D= =3D 4) { + data =3D 0x3 << (bit + 16); + rmask =3D data | (data >> 16); + data |=3D ((enable ? 0x3 : 0) << bit); + } + } + return regmap_update_bits(regmap, reg, rmask, data); } =20 @@ -3227,6 +3588,7 @@ static bool rockchip_pinconf_pull_valid(struct rockch= ip_pin_ctrl *ctrl, case RK3328: case RK3368: case RK3399: + case RK3506: case RK3528: case RK3562: case RK3568: @@ -3880,13 +4242,10 @@ static int rockchip_pinctrl_probe(struct platform_d= evice *pdev) } =20 /* try to find the optional reference to the pmu syscon */ - node =3D of_parse_phandle(np, "rockchip,pmu", 0); - if (node) { - info->regmap_pmu =3D syscon_node_to_regmap(node); - of_node_put(node); - if (IS_ERR(info->regmap_pmu)) - return PTR_ERR(info->regmap_pmu); - } + info->regmap_pmu =3D syscon_regmap_lookup_by_phandle_optional(np, "rockch= ip,pmu"); + + /* try to find the optional reference to the ioc1 syscon */ + info->regmap_ioc1 =3D syscon_regmap_lookup_by_phandle_optional(np, "rockc= hip,ioc1"); =20 ret =3D rockchip_pinctrl_register(pdev, info); if (ret) @@ -4350,6 +4709,71 @@ static struct rockchip_pin_ctrl rk3399_pin_ctrl =3D { .drv_calc_reg =3D rk3399_calc_drv_reg_and_bit, }; =20 +static struct rockchip_pin_bank rk3506_pin_banks[] =3D { + PIN_BANK_IOMUX_FLAGS_OFFSET_DRV_FLAGS_PULL_FLAGS(0, 32, "gpio0", + IOMUX_WIDTH_4BIT | IOMUX_SOURCE_PMU, + IOMUX_WIDTH_4BIT | IOMUX_SOURCE_PMU, + IOMUX_WIDTH_4BIT | IOMUX_SOURCE_PMU, + IOMUX_WIDTH_2BIT | IOMUX_SOURCE_PMU, + 0x0, 0x8, 0x10, 0x830, + DRV_TYPE_IO_LEVEL_8_BIT, + DRV_TYPE_IO_LEVEL_8_BIT, + DRV_TYPE_IO_LEVEL_8_BIT, + DRV_TYPE_IO_LEVEL_2_BIT, + 0, 0, 0, 1), + PIN_BANK_IOMUX_FLAGS_OFFSET_DRV_FLAGS(1, 32, "gpio1", + IOMUX_WIDTH_4BIT, + IOMUX_WIDTH_4BIT, + IOMUX_WIDTH_4BIT, + IOMUX_WIDTH_4BIT, + 0x20, 0x28, 0x30, 0x38, + DRV_TYPE_IO_LEVEL_8_BIT, + DRV_TYPE_IO_LEVEL_8_BIT, + DRV_TYPE_IO_LEVEL_8_BIT, + DRV_TYPE_IO_LEVEL_8_BIT), + PIN_BANK_IOMUX_FLAGS_OFFSET_DRV_FLAGS(2, 32, "gpio2", + IOMUX_WIDTH_4BIT, + IOMUX_WIDTH_4BIT, + IOMUX_WIDTH_4BIT, + IOMUX_WIDTH_4BIT, + 0x40, 0x48, 0x50, 0x58, + DRV_TYPE_IO_LEVEL_8_BIT, + DRV_TYPE_IO_LEVEL_8_BIT, + DRV_TYPE_IO_LEVEL_8_BIT, + DRV_TYPE_IO_LEVEL_8_BIT), + PIN_BANK_IOMUX_FLAGS_OFFSET_DRV_FLAGS(3, 32, "gpio3", + IOMUX_WIDTH_4BIT, + IOMUX_WIDTH_4BIT, + IOMUX_WIDTH_4BIT, + IOMUX_WIDTH_4BIT, + 0x60, 0x68, 0x70, 0x78, + DRV_TYPE_IO_LEVEL_8_BIT, + DRV_TYPE_IO_LEVEL_8_BIT, + DRV_TYPE_IO_LEVEL_8_BIT, + DRV_TYPE_IO_LEVEL_8_BIT), + PIN_BANK_IOMUX_FLAGS_OFFSET_DRV_FLAGS_PULL_FLAGS(4, 32, "gpio4", + IOMUX_WIDTH_4BIT, + IOMUX_WIDTH_4BIT, + IOMUX_WIDTH_4BIT, + IOMUX_WIDTH_4BIT, + 0x80, 0x88, 0x90, 0x98, + DRV_TYPE_IO_LEVEL_2_BIT, + DRV_TYPE_IO_LEVEL_2_BIT, + DRV_TYPE_IO_LEVEL_2_BIT, + DRV_TYPE_IO_LEVEL_2_BIT, + 1, 1, 1, 1), +}; + +static struct rockchip_pin_ctrl rk3506_pin_ctrl __maybe_unused =3D { + .pin_banks =3D rk3506_pin_banks, + .nr_banks =3D ARRAY_SIZE(rk3506_pin_banks), + .label =3D "RK3506-GPIO", + .type =3D RK3506, + .pull_calc_reg =3D rk3506_calc_pull_reg_and_bit, + .drv_calc_reg =3D rk3506_calc_drv_reg_and_bit, + .schmitt_calc_reg =3D rk3506_calc_schmitt_reg_and_bit, +}; + static struct rockchip_pin_bank rk3528_pin_banks[] =3D { PIN_BANK_IOMUX_FLAGS_OFFSET(0, 32, "gpio0", IOMUX_WIDTH_4BIT, @@ -4560,6 +4984,8 @@ static const struct of_device_id rockchip_pinctrl_dt_= match[] =3D { .data =3D &rk3368_pin_ctrl }, { .compatible =3D "rockchip,rk3399-pinctrl", .data =3D &rk3399_pin_ctrl }, + { .compatible =3D "rockchip,rk3506-pinctrl", + .data =3D &rk3506_pin_ctrl }, { .compatible =3D "rockchip,rk3528-pinctrl", .data =3D &rk3528_pin_ctrl }, { .compatible =3D "rockchip,rk3562-pinctrl", diff --git a/drivers/pinctrl/pinctrl-rockchip.h b/drivers/pinctrl/pinctrl-r= ockchip.h index 35cd38079d1e..4f4aff42a80a 100644 --- a/drivers/pinctrl/pinctrl-rockchip.h +++ b/drivers/pinctrl/pinctrl-rockchip.h @@ -196,6 +196,7 @@ enum rockchip_pinctrl_type { RK3328, RK3368, RK3399, + RK3506, RK3528, RK3562, RK3568, @@ -260,6 +261,8 @@ enum rockchip_pin_drv_type { DRV_TYPE_IO_1V8_ONLY, DRV_TYPE_IO_1V8_3V0_AUTO, DRV_TYPE_IO_3V3_ONLY, + DRV_TYPE_IO_LEVEL_2_BIT, + DRV_TYPE_IO_LEVEL_8_BIT, DRV_TYPE_MAX }; =20 @@ -458,6 +461,7 @@ struct rockchip_pinctrl { int reg_size; struct regmap *regmap_pull; struct regmap *regmap_pmu; + struct regmap *regmap_ioc1; struct device *dev; struct rockchip_pin_ctrl *ctrl; struct pinctrl_desc pctl; --=20 2.34.1 From nobody Fri Dec 19 13:27:15 2025 Received: from mail-m49229.qiye.163.com (mail-m49229.qiye.163.com [45.254.49.229]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 08E4E22D4DC; Sat, 6 Dec 2025 05:09:05 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=45.254.49.229 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764997749; cv=none; b=kr3DlkW6MwkXBxdwwHOspHMpVqtYNSqwsPUovolHfvlc8XPU5CqIvP6OCMKIC4GVhXhidtQqnGaYT/8Vv3TO+hJTEOCghSiyMi93Qw+op+jzHREG9036x5O3fW7xvMvqgAYjCp4heIKgYwYXtEchbEzW2UiCxyp8PTXOdxeIJmE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; 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(unknown [58.22.7.114]) by smtp.qiye.163.com (Hmail) with ESMTP id 2c3493a67; Sat, 6 Dec 2025 13:08:50 +0800 (GMT+08:00) From: Ye Zhang To: Ye Zhang , Linus Walleij , Heiko Stuebner Cc: Bartosz Golaszewski , Rob Herring , Krzysztof Kozlowski , Conor Dooley , linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, tao.huang@rock-chips.com Subject: [PATCH v2 3/8] dt-bindings: pinctrl: Add rv1126b pinctrl support Date: Sat, 6 Dec 2025 13:08:39 +0800 Message-Id: <20251206050844.402958-4-ye.zhang@rock-chips.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20251206050844.402958-1-ye.zhang@rock-chips.com> References: <20251206050844.402958-1-ye.zhang@rock-chips.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-HM-Tid: 0a9af2100fed09d8kunmae94618c4ed3c65 X-HM-MType: 1 X-HM-Spam-Status: e1kfGhgUHx5ZQUpXWQgPGg8OCBgUHx5ZQUlOS1dZFg8aDwILHllBWSg2Ly tZV1koWUFDSUNOT01LS0k3V1ktWUFJV1kPCRoVCBIfWUFZGRoaHlYaShgfSh8ZSk5OTx1WFRQJFh oXVRMBExYaEhckFA4PWVdZGBILWUFZTkNVSUlVTFVKSk9ZV1kWGg8SFR0UWUFZT0tIVUpLSU9PT0 hVSktLVUpCS0tZBg++ DKIM-Signature: a=rsa-sha256; b=j0DLJk/ldHyUNN1Lze38fkhfQWx2G4XeWPjZ5OjSM0RYbHcXbX4h3Ij3/bceXUt8wxI41y2S0+XQM1sjkgk9ol1pH+noROEq8YtQ1h+S0BnBqRAtpFI2PB+9PAO3HDlDQzpZxLABrV2vYPFl/6FJnxYbU34cM+D5ou7UgzKWSBE=; s=default; c=relaxed/relaxed; d=rock-chips.com; v=1; bh=peBVdRDCYMluVzoh6VCOVP/33y4SVuD35nSziJTXUi8=; h=date:mime-version:subject:message-id:from; Content-Type: text/plain; charset="utf-8" Add the compatible string for the rv1126b SoC. Signed-off-by: Ye Zhang --- Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.yam= l b/Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.yaml index 76e607281716..93bf8f352e48 100644 --- a/Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.yaml @@ -52,6 +52,7 @@ properties: - rockchip,rk3588-pinctrl - rockchip,rv1108-pinctrl - rockchip,rv1126-pinctrl + - rockchip,rv1126b-pinctrl =20 rockchip,grf: $ref: /schemas/types.yaml#/definitions/phandle --=20 2.34.1 From nobody Fri Dec 19 13:27:15 2025 Received: from mail-m32116.qiye.163.com (mail-m32116.qiye.163.com [220.197.32.116]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BD87F2853E9; Sat, 6 Dec 2025 05:14:10 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=220.197.32.116 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764998057; cv=none; b=WXN8ECyWzyiQvsPCmsCSHbGaMLT5qCakDAA8hF7E9V6B4wn5n6cZ9wJHCDtySIJgHww96w4eKvYnFjW07bfBXEWYlHqmKkoWlnPjxXALxBi/R7+YdwEzVZb6LEQ2C2rTAwN4nLAaZSPB56BeiLsj7lRW55PowH9ah9M9k+y1jWE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764998057; c=relaxed/simple; bh=L5eJbYiV28fd0iaOGM850WW/6o3EvqLqvtLjiUvlWXg=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=eXpHoRkYoXQS182xHoTBr42s1MHoMJAJoQNEqXYkpc8yL+M9kHY8+2CW+IpLULzJQNVAkAMZWyIsPut4EsvsO0FtLb+7Aecqts/262PZf/g/qUHWI7ffH6GsFs2xvn8VLiu90M/Sc+tHt1+idkbzbIYkgiqLxnSHwLzbDZOuICo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=rock-chips.com; spf=pass smtp.mailfrom=rock-chips.com; dkim=pass (1024-bit key) header.d=rock-chips.com header.i=@rock-chips.com header.b=H43ZHYD8; arc=none smtp.client-ip=220.197.32.116 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=rock-chips.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=rock-chips.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=rock-chips.com header.i=@rock-chips.com header.b="H43ZHYD8" Received: from rockchip.. (unknown [58.22.7.114]) by smtp.qiye.163.com (Hmail) with ESMTP id 2c3493a69; Sat, 6 Dec 2025 13:08:51 +0800 (GMT+08:00) From: Ye Zhang To: Ye Zhang , Linus Walleij , Heiko Stuebner Cc: Bartosz Golaszewski , Rob Herring , Krzysztof Kozlowski , Conor Dooley , linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, tao.huang@rock-chips.com Subject: [PATCH v2 4/8] pinctrl: rockchip: Add rv1126b pinctrl support Date: Sat, 6 Dec 2025 13:08:40 +0800 Message-Id: <20251206050844.402958-5-ye.zhang@rock-chips.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20251206050844.402958-1-ye.zhang@rock-chips.com> References: <20251206050844.402958-1-ye.zhang@rock-chips.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-HM-Tid: 0a9af210147c09d8kunmae94618c4ed3d4a X-HM-MType: 1 X-HM-Spam-Status: e1kfGhgUHx5ZQUpXWQgPGg8OCBgUHx5ZQUlOS1dZFg8aDwILHllBWSg2Ly tZV1koWUFDSUNOT01LS0k3V1ktWUFJV1kPCRoVCBIfWUFZQk1PTlZDS01OGB1OQkNMGU1WFRQJFh oXVRMBExYaEhckFA4PWVdZGBILWUFZTkNVSUlVTFVKSk9ZV1kWGg8SFR0UWUFZT0tIVUpLSU9PT0 hVSktLVUpCS0tZBg++ DKIM-Signature: a=rsa-sha256; b=H43ZHYD8fDk8kT50ItKRRNdKbWNyX2JIKe+arOzPfrT3kU63TSEyoJfnjKb7KREfiJ1uYgNFvWh0iRLa54HP7EGpnhHiQmEaUXsivTL+LFzeH8p1rjTuoQn8S9yDHLwrxeLvBsw7fCRZpIQY96sKS5viKWKwKjd38LZC9eMwIyc=; s=default; c=relaxed/relaxed; d=rock-chips.com; v=1; bh=DZ6xry1g/zBse0eKoeaEsKtLVjuDD8R4dy+lNZCkoC8=; h=date:mime-version:subject:message-id:from; Content-Type: text/plain; charset="utf-8" Add support for the 8 rv1126b GPIO banks. Signed-off-by: Ye Zhang --- drivers/pinctrl/pinctrl-rockchip.c | 181 ++++++++++++++++++++++++++++- drivers/pinctrl/pinctrl-rockchip.h | 1 + 2 files changed, 181 insertions(+), 1 deletion(-) diff --git a/drivers/pinctrl/pinctrl-rockchip.c b/drivers/pinctrl/pinctrl-r= ockchip.c index e44ef262beec..dc7ef12dfcb0 100644 --- a/drivers/pinctrl/pinctrl-rockchip.c +++ b/drivers/pinctrl/pinctrl-rockchip.c @@ -307,6 +307,20 @@ #define RK3588_PIN_BANK_FLAGS(ID, PIN, LABEL, M, P) \ PIN_BANK_IOMUX_FLAGS_PULL_FLAGS(ID, PIN, LABEL, M, M, M, M, P, P, P, P) =20 +#define PIN_BANK_IOMUX_4_OFFSET_DRV_8(id, pins, label, offset0, \ + offset1, offset2, offset3) \ + PIN_BANK_IOMUX_FLAGS_OFFSET_DRV_FLAGS(id, pins, label, \ + IOMUX_WIDTH_4BIT, \ + IOMUX_WIDTH_4BIT, \ + IOMUX_WIDTH_4BIT, \ + IOMUX_WIDTH_4BIT, \ + offset0, offset1, \ + offset2, offset3, \ + DRV_TYPE_IO_LEVEL_8_BIT, \ + DRV_TYPE_IO_LEVEL_8_BIT, \ + DRV_TYPE_IO_LEVEL_8_BIT, \ + DRV_TYPE_IO_LEVEL_8_BIT) + static struct regmap_config rockchip_regmap_config =3D { .reg_bits =3D 32, .val_bits =3D 32, @@ -1701,6 +1715,136 @@ static int rv1126_calc_schmitt_reg_and_bit(struct r= ockchip_pin_bank *bank, return 0; } =20 +#define RV1126B_DRV_BITS_PER_PIN 8 +#define RV1126B_DRV_PINS_PER_REG 2 +#define RV1126B_DRV_GPIO0_A_OFFSET 0x100 +#define RV1126B_DRV_GPIO0_C_OFFSET 0x8120 +#define RV1126B_DRV_GPIO_OFFSET(GPION) (0x8100 + GPION * 0x8040) + +static int rv1126b_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, + int pin_num, struct regmap **regmap, + int *reg, u8 *bit) +{ + struct rockchip_pinctrl *info =3D bank->drvdata; + + *regmap =3D info->regmap_base; + switch (bank->bank_num) { + case 0: + if (pin_num < 16) + *reg =3D RV1126B_DRV_GPIO0_A_OFFSET; + else + *reg =3D RV1126B_DRV_GPIO0_C_OFFSET - 0x20; + break; + + case 1: + case 2: + case 3: + case 4: + case 5: + case 6: + case 7: + *reg =3D RV1126B_DRV_GPIO_OFFSET(bank->bank_num); + break; + + default: + dev_err(info->dev, "unsupported bank_num %d\n", bank->bank_num); + break; + } + + *reg +=3D ((pin_num / RV1126B_DRV_PINS_PER_REG) * 4); + *bit =3D pin_num % RV1126B_DRV_PINS_PER_REG; + *bit *=3D RV1126B_DRV_BITS_PER_PIN; + + return 0; +} + +#define RV1126B_PULL_BITS_PER_PIN 2 +#define RV1126B_PULL_PINS_PER_REG 8 +#define RV1126B_PULL_GPIO0_A_OFFSET 0x300 +#define RV1126B_PULL_GPIO0_C_OFFSET 0x8308 +#define RV1126B_PULL_GPIO_OFFSET(GPION) (0x8300 + GPION * 0x8010) + +static int rv1126b_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, + int pin_num, struct regmap **regmap, + int *reg, u8 *bit) +{ + struct rockchip_pinctrl *info =3D bank->drvdata; + + *regmap =3D info->regmap_base; + switch (bank->bank_num) { + case 0: + if (pin_num < 16) + *reg =3D RV1126B_PULL_GPIO0_A_OFFSET; + else + *reg =3D RV1126B_PULL_GPIO0_C_OFFSET - 0x8; + break; + + case 1: + case 2: + case 3: + case 4: + case 5: + case 6: + case 7: + *reg =3D RV1126B_PULL_GPIO_OFFSET(bank->bank_num); + break; + + default: + dev_err(info->dev, "unsupported bank_num %d\n", bank->bank_num); + break; + } + + *reg +=3D ((pin_num / RV1126B_PULL_PINS_PER_REG) * 4); + *bit =3D pin_num % RV1126B_PULL_PINS_PER_REG; + *bit *=3D RV1126B_PULL_BITS_PER_PIN; + + return 0; +} + +#define RV1126B_SMT_BITS_PER_PIN 1 +#define RV1126B_SMT_PINS_PER_REG 8 +#define RV1126B_SMT_GPIO0_A_OFFSET 0x500 +#define RV1126B_SMT_GPIO0_C_OFFSET 0x8508 +#define RV1126B_SMT_GPIO_OFFSET(GPION) (0x8500 + GPION * 0x8010) + +static int rv1126b_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank, + int pin_num, + struct regmap **regmap, + int *reg, u8 *bit) +{ + struct rockchip_pinctrl *info =3D bank->drvdata; + + *regmap =3D info->regmap_base; + switch (bank->bank_num) { + case 0: + if (pin_num < 16) + *reg =3D RV1126B_SMT_GPIO0_A_OFFSET; + else + *reg =3D RV1126B_SMT_GPIO0_C_OFFSET - 0x8; + break; + + case 1: + case 2: + case 3: + case 4: + case 5: + case 6: + case 7: + *reg =3D RV1126B_SMT_GPIO_OFFSET(bank->bank_num); + break; + + default: + dev_err(info->dev, "unsupported bank_num %d\n", bank->bank_num); + break; + } + + *reg +=3D ((pin_num / RV1126B_SMT_PINS_PER_REG) * 4); + *bit =3D pin_num % RV1126B_SMT_PINS_PER_REG; + *bit *=3D RV1126B_SMT_BITS_PER_PIN; + + return 0; +} + #define RK3308_SCHMITT_PINS_PER_REG 8 #define RK3308_SCHMITT_BANK_STRIDE 16 #define RK3308_SCHMITT_GRF_OFFSET 0x1a0 @@ -3071,7 +3215,8 @@ static int rockchip_set_drive_perpin(struct rockchip_= pin_bank *bank, rmask_bits =3D RK3588_DRV_BITS_PER_PIN; ret =3D strength; goto config; - } else if (ctrl->type =3D=3D RK3506 || + } else if (ctrl->type =3D=3D RV1126B || + ctrl->type =3D=3D RK3506 || ctrl->type =3D=3D RK3528 || ctrl->type =3D=3D RK3562 || ctrl->type =3D=3D RK3568) { @@ -3237,6 +3382,7 @@ static int rockchip_get_pull(struct rockchip_pin_bank= *bank, int pin_num) : PIN_CONFIG_BIAS_DISABLE; case PX30: case RV1108: + case RV1126B: case RK3188: case RK3288: case RK3308: @@ -3299,6 +3445,7 @@ static int rockchip_set_pull(struct rockchip_pin_bank= *bank, case PX30: case RV1108: case RV1126: + case RV1126B: case RK3188: case RK3288: case RK3308: @@ -3582,6 +3729,7 @@ static bool rockchip_pinconf_pull_valid(struct rockch= ip_pin_ctrl *ctrl, case PX30: case RV1108: case RV1126: + case RV1126B: case RK3188: case RK3288: case RK3308: @@ -4386,6 +4534,35 @@ static struct rockchip_pin_ctrl rv1126_pin_ctrl =3D { .schmitt_calc_reg =3D rv1126_calc_schmitt_reg_and_bit, }; =20 +static struct rockchip_pin_bank rv1126b_pin_banks[] =3D { + PIN_BANK_IOMUX_4_OFFSET_DRV_8(0, 32, "gpio0", + 0x0, 0x8, 0x8010, 0x8018), + PIN_BANK_IOMUX_4_OFFSET_DRV_8(1, 32, "gpio1", + 0x10020, 0x10028, 0x10030, 0x10038), + PIN_BANK_IOMUX_4_OFFSET_DRV_8(2, 32, "gpio2", + 0x18040, 0x18048, 0x18050, 0x18058), + PIN_BANK_IOMUX_4_OFFSET_DRV_8(3, 32, "gpio3", + 0x20060, 0x20068, 0x20070, 0x20078), + PIN_BANK_IOMUX_4_OFFSET_DRV_8(4, 32, "gpio4", + 0x28080, 0x28088, 0x28090, 0x28098), + PIN_BANK_IOMUX_4_OFFSET_DRV_8(5, 32, "gpio5", + 0x300a0, 0x300a8, 0x300b0, 0x300b8), + PIN_BANK_IOMUX_4_OFFSET_DRV_8(6, 32, "gpio6", + 0x380c0, 0x380c8, 0x380d0, 0x380d8), + PIN_BANK_IOMUX_4_OFFSET_DRV_8(7, 32, "gpio7", + 0x400e0, 0x400e8, 0x400f0, 0x400f8), +}; + +static struct rockchip_pin_ctrl rv1126b_pin_ctrl __maybe_unused =3D { + .pin_banks =3D rv1126b_pin_banks, + .nr_banks =3D ARRAY_SIZE(rv1126b_pin_banks), + .label =3D "RV1126B-GPIO", + .type =3D RV1126B, + .pull_calc_reg =3D rv1126b_calc_pull_reg_and_bit, + .drv_calc_reg =3D rv1126b_calc_drv_reg_and_bit, + .schmitt_calc_reg =3D rv1126b_calc_schmitt_reg_and_bit, +}; + static struct rockchip_pin_bank rk2928_pin_banks[] =3D { PIN_BANK(0, 32, "gpio0"), PIN_BANK(1, 32, "gpio1"), @@ -4960,6 +5137,8 @@ static const struct of_device_id rockchip_pinctrl_dt_= match[] =3D { .data =3D &rv1108_pin_ctrl }, { .compatible =3D "rockchip,rv1126-pinctrl", .data =3D &rv1126_pin_ctrl }, + { .compatible =3D "rockchip,rv1126b-pinctrl", + .data =3D &rv1126b_pin_ctrl }, { .compatible =3D "rockchip,rk2928-pinctrl", .data =3D &rk2928_pin_ctrl }, { .compatible =3D "rockchip,rk3036-pinctrl", diff --git a/drivers/pinctrl/pinctrl-rockchip.h b/drivers/pinctrl/pinctrl-r= ockchip.h index 4f4aff42a80a..fe18b62ed994 100644 --- a/drivers/pinctrl/pinctrl-rockchip.h +++ b/drivers/pinctrl/pinctrl-rockchip.h @@ -187,6 +187,7 @@ enum rockchip_pinctrl_type { PX30, RV1108, RV1126, + RV1126B, RK2928, RK3066B, RK3128, --=20 2.34.1 From nobody Fri Dec 19 13:27:15 2025 Received: from mail-m49200.qiye.163.com (mail-m49200.qiye.163.com [45.254.49.200]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 126941E00B4; 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(unknown [58.22.7.114]) by smtp.qiye.163.com (Hmail) with ESMTP id 2c3493a6c; Sat, 6 Dec 2025 13:08:52 +0800 (GMT+08:00) From: Ye Zhang To: Ye Zhang , Linus Walleij , Heiko Stuebner Cc: Bartosz Golaszewski , Rob Herring , Krzysztof Kozlowski , Conor Dooley , linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, tao.huang@rock-chips.com Subject: [PATCH v2 5/8] gpio: rockchip: support new version GPIO Date: Sat, 6 Dec 2025 13:08:41 +0800 Message-Id: <20251206050844.402958-6-ye.zhang@rock-chips.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20251206050844.402958-1-ye.zhang@rock-chips.com> References: <20251206050844.402958-1-ye.zhang@rock-chips.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-HM-Tid: 0a9af210198909d8kunmae94618c4ed3e1c X-HM-MType: 1 X-HM-Spam-Status: e1kfGhgUHx5ZQUpXWQgPGg8OCBgUHx5ZQUlOS1dZFg8aDwILHllBWSg2Ly tZV1koWUFDSUNOT01LS0k3V1ktWUFJV1kPCRoVCBIfWUFZGkgaGFZNGkseHk4YQk1MSE1WFRQJFh oXVRMBExYaEhckFA4PWVdZGBILWUFZTkNVSUlVTFVKSk9ZV1kWGg8SFR0UWUFZT0tIVUpLSU9PT0 hVSktLVUpCS0tZBg++ DKIM-Signature: a=rsa-sha256; b=eSBTQEehL+XEEjHghtm6V9xG0iVxILE7KBCG/nUDdW8E5C8pQblXuIA1FRJM6BzuTgSSnG/TWLe9rpGVfGe0xCIQrAmFotPbOGM6YM3KuzP8Wp+qWRfXeVUih/1eQSLqL4MeROFQMQR0IMNMR1VjOBxju5HpGnt/evWRWOTtImM=; s=default; c=relaxed/relaxed; d=rock-chips.com; v=1; bh=hROdXb99JYSlT3iQf+bnbcYEmk90Jd765fZkjU+c7DU=; h=date:mime-version:subject:message-id:from; Content-Type: text/plain; charset="utf-8" Support the next version GPIO controller on SoCs like rv1126b. Signed-off-by: Ye Zhang Acked-by: Bartosz Golaszewski --- drivers/gpio/gpio-rockchip.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpio/gpio-rockchip.c b/drivers/gpio/gpio-rockchip.c index 47174eb3ba76..c3e831c6bcf1 100644 --- a/drivers/gpio/gpio-rockchip.c +++ b/drivers/gpio/gpio-rockchip.c @@ -36,6 +36,7 @@ #define GPIO_TYPE_V2 (0x01000C2B) #define GPIO_TYPE_V2_1 (0x0101157C) #define GPIO_TYPE_V2_2 (0x010219C8) +#define GPIO_TYPE_V2_6 (0x01063F6E) =20 static const struct rockchip_gpio_regs gpio_regs_v1 =3D { .port_dr =3D 0x00, @@ -674,6 +675,7 @@ static int rockchip_get_bank_data(struct rockchip_pin_b= ank *bank) case GPIO_TYPE_V2: case GPIO_TYPE_V2_1: case GPIO_TYPE_V2_2: + case GPIO_TYPE_V2_6: bank->gpio_regs =3D &gpio_regs_v2; bank->gpio_type =3D GPIO_TYPE_V2; bank->db_clk =3D of_clk_get(bank->of_node, 1); --=20 2.34.1 From nobody Fri Dec 19 13:27:15 2025 Received: from mail-m3268.qiye.163.com (mail-m3268.qiye.163.com [220.197.32.68]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A9C6A22D4DC; Sat, 6 Dec 2025 05:09:16 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=220.197.32.68 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764997760; cv=none; b=bMx3IiNDNvSgZpDJxApTKghrjOP5egYCRirr5HwvFahci8vKs7Bz1UoVOKb9BzB8JatwZCqAt7Ll2RGwCW1ywduH1KzdYwBMJULsD5PEJDY3XaMvdEDE9ynLHRtgctNGTWjqld3iVGWf89ryCQWFKdUbIAPWiGmjHWS7SdHm6LM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764997760; c=relaxed/simple; bh=RSP3DNGJ65CGbPW/5yypw/A+V/F+cH1ZIH3QoPwJKro=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=qSH0i5wJTTi3ftA0jAcYdRrBcS5dWCpbucPwa3O5DYzUJ6Qe35YFuHqNRMB7KX/2TQ7vGHGi+0t74AxBkqDBmV77rEXWFvv2zUTvU5jgzAxrXDRAZuZcruEEwQAhGwEaIr8K+QBoP72ybnm2/kB8lYC3v1/A5MdMuayGsP+QHOY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=rock-chips.com; spf=pass smtp.mailfrom=rock-chips.com; dkim=pass (1024-bit key) header.d=rock-chips.com header.i=@rock-chips.com header.b=Kb8TLkq1; arc=none smtp.client-ip=220.197.32.68 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=rock-chips.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=rock-chips.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=rock-chips.com header.i=@rock-chips.com header.b="Kb8TLkq1" Received: from rockchip.. (unknown [58.22.7.114]) by smtp.qiye.163.com (Hmail) with ESMTP id 2c3493a6f; Sat, 6 Dec 2025 13:08:53 +0800 (GMT+08:00) From: Ye Zhang To: Ye Zhang , Linus Walleij , Heiko Stuebner Cc: Bartosz Golaszewski , Rob Herring , Krzysztof Kozlowski , Conor Dooley , linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, tao.huang@rock-chips.com Subject: [PATCH v2 6/8] dt-bindings: pinctrl: Add header for Rockchip RK3506 RMIO Date: Sat, 6 Dec 2025 13:08:42 +0800 Message-Id: <20251206050844.402958-7-ye.zhang@rock-chips.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20251206050844.402958-1-ye.zhang@rock-chips.com> References: <20251206050844.402958-1-ye.zhang@rock-chips.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-HM-Tid: 0a9af2101e1a09d8kunmae94618c4ed3eaf X-HM-MType: 1 X-HM-Spam-Status: e1kfGhgUHx5ZQUpXWQgPGg8OCBgUHx5ZQUlOS1dZFg8aDwILHllBWSg2Ly tZV1koWUFDSUNOT01LS0k3V1ktWUFJV1kPCRoVCBIfWUFZGhhNTlZMGh1MSEJCTk9NTUxWFRQJFh oXVRMBExYaEhckFA4PWVdZGBILWUFZTkNVSUlVTFVKSk9ZV1kWGg8SFR0UWUFZT0tIVUpLSU9PT0 hVSktLVUpCS0tZBg++ DKIM-Signature: a=rsa-sha256; b=Kb8TLkq1VYYEi5HZUftNqJWCUIeHSXocCTRrgo8kcUJ0OpwF42usAMDns9nwJ/LsXGWVpHG2x3YiSO+pnYkQ6tKDBJ429orJhIlDs7P7ohrsj93ll0A7qWNm0eaUXUWTKb6ru02BJQCMh0Blxc0zvTgFAMdWsdbsTd2FvxbPJWY=; s=default; c=relaxed/relaxed; d=rock-chips.com; v=1; bh=gcDxCT/vnr2dTxZ7y5r6e88qG/0XM0v8Hk5zok5szB8=; h=date:mime-version:subject:message-id:from; Content-Type: text/plain; charset="utf-8" Add header file with constants for RMIO pin and function IDs for the Rockchip RK3506 SoC. Signed-off-by: Ye Zhang --- .../pinctrl/rockchip,rk3506-rmio.h | 143 ++++++++++++++++++ 1 file changed, 143 insertions(+) create mode 100644 include/dt-bindings/pinctrl/rockchip,rk3506-rmio.h diff --git a/include/dt-bindings/pinctrl/rockchip,rk3506-rmio.h b/include/d= t-bindings/pinctrl/rockchip,rk3506-rmio.h new file mode 100644 index 000000000000..5d39690a0b28 --- /dev/null +++ b/include/dt-bindings/pinctrl/rockchip,rk3506-rmio.h @@ -0,0 +1,143 @@ +/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */ +/* + * Copyright (c) 2025 Rockchip Electronics Co., Ltd. + */ + +#ifndef __DT_BINDINGS_PINCTRL_ROCKCHIP_RK3506_RMIO_H +#define __DT_BINDINGS_PINCTRL_ROCKCHIP_RK3506_RMIO_H + +/* RMIO pins definetion */ +#define RMIO_PIN0 0 +#define RMIO_PIN1 1 +#define RMIO_PIN2 2 +#define RMIO_PIN3 3 +#define RMIO_PIN4 4 +#define RMIO_PIN5 5 +#define RMIO_PIN6 6 +#define RMIO_PIN7 7 +#define RMIO_PIN8 8 +#define RMIO_PIN9 9 +#define RMIO_PIN10 10 +#define RMIO_PIN11 11 +#define RMIO_PIN12 12 +#define RMIO_PIN13 13 +#define RMIO_PIN14 14 +#define RMIO_PIN15 15 +#define RMIO_PIN16 16 +#define RMIO_PIN17 17 +#define RMIO_PIN18 18 +#define RMIO_PIN19 19 +#define RMIO_PIN20 20 +#define RMIO_PIN21 21 +#define RMIO_PIN22 22 +#define RMIO_PIN23 23 +#define RMIO_PIN24 24 +#define RMIO_PIN25 25 +#define RMIO_PIN26 26 +#define RMIO_PIN27 27 +#define RMIO_PIN28 28 +#define RMIO_PIN29 29 +#define RMIO_PIN30 30 +#define RMIO_PIN31 31 + +/* RMIO function definetion */ +#define RMIO_UART1_TX 1 +#define RMIO_UART1_RX 2 +#define RMIO_UART2_TX 3 +#define RMIO_UART2_RX 4 +#define RMIO_UART3_TX 5 +#define RMIO_UART3_RX 6 +#define RMIO_UART3_CTSN 7 +#define RMIO_UART3_RTSN 8 +#define RMIO_UART4_TX 9 +#define RMIO_UART4_RX 10 +#define RMIO_UART4_CTSN 11 +#define RMIO_UART4_RTSN 12 +#define RMIO_MIPITE 13 +#define RMIO_CLK_32K 14 +#define RMIO_I2C0_SCL 15 +#define RMIO_I2C0_SDA 16 +#define RMIO_I2C1_SCL 17 +#define RMIO_I2C1_SDA 18 +#define RMIO_I2C2_SCL 19 +#define RMIO_I2C2_SDA 20 +#define RMIO_PDM_CLK0 21 +#define RMIO_PDM_SDI0 22 +#define RMIO_PDM_SDI1 23 +#define RMIO_PDM_SDI2 24 +#define RMIO_PDM_SDI3 25 +#define RMIO_CAN1_TX 26 +#define RMIO_CAN1_RX 27 +#define RMIO_CAN0_TX 28 +#define RMIO_CAN0_RX 29 +#define RMIO_PWM0_CH0 30 +#define RMIO_PWM0_CH1 31 +#define RMIO_PWM0_CH2 32 +#define RMIO_PWM0_CH3 33 +#define RMIO_PWM1_CH0 34 +#define RMIO_PWM1_CH1 35 +#define RMIO_PWM1_CH2 36 +#define RMIO_PWM1_CH3 37 +#define RMIO_PWM1_CH4 38 +#define RMIO_PWM1_CH5 39 +#define RMIO_PWM1_CH6 40 +#define RMIO_PWM1_CH7 41 +#define RMIO_TOUCH_KEY_DRIVE 42 +#define RMIO_TOUCH_KEY_IN0 43 +#define RMIO_TOUCH_KEY_IN1 44 +#define RMIO_TOUCH_KEY_IN2 45 +#define RMIO_TOUCH_KEY_IN3 46 +#define RMIO_TOUCH_KEY_IN4 47 +#define RMIO_TOUCH_KEY_IN5 48 +#define RMIO_TOUCH_KEY_IN6 49 +#define RMIO_TOUCH_KEY_IN7 50 +#define RMIO_SAI0_MCLK 51 +#define RMIO_SAI0_SCLK 52 +#define RMIO_SAI0_LRCK 53 +#define RMIO_SAI0_SDI0 54 +#define RMIO_SAI0_SDI1 55 +#define RMIO_SAI0_SDI2 56 +#define RMIO_SAI0_SDI3 57 +#define RMIO_SAI0_SDO 58 +#define RMIO_SAI1_MCLK 59 +#define RMIO_SAI1_SCLK 60 +#define RMIO_SAI1_LRCK 61 +#define RMIO_SAI1_SDI 62 +#define RMIO_SAI1_SDO0 63 +#define RMIO_SAI1_SDO1 64 +#define RMIO_SAI1_SDO2 65 +#define RMIO_SAI1_SDO3 66 +#define RMIO_SPI0_CLK 67 +#define RMIO_SPI0_MOSI 68 +#define RMIO_SPI0_MISO 69 +#define RMIO_SPI0_CSN0 70 +#define RMIO_SPI0_CSN1 71 +#define RMIO_SPI1_CLK 72 +#define RMIO_SPI1_MOSI 73 +#define RMIO_SPI1_MISO 74 +#define RMIO_SPI1_CSN0 75 +#define RMIO_SPI1_CSN1 76 +#define RMIO_WDT_TSADC_SHUT 77 +#define RMIO_PMU_SLEEP 78 +#define RMIO_CORE_POWER_OFF 79 +#define RMIO_SPDIF_TX 80 +#define RMIO_SPDIF_RX 81 +#define RMIO_PWM1_BIP_CNTR_A0 82 +#define RMIO_PWM1_BIP_CNTR_A1 83 +#define RMIO_PWM1_BIP_CNTR_A2 84 +#define RMIO_PWM1_BIP_CNTR_A3 85 +#define RMIO_PWM1_BIP_CNTR_A4 86 +#define RMIO_PWM1_BIP_CNTR_A5 87 +#define RMIO_PWM1_BIP_CNTR_B0 88 +#define RMIO_PWM1_BIP_CNTR_B1 89 +#define RMIO_PWM1_BIP_CNTR_B2 90 +#define RMIO_PWM1_BIP_CNTR_B3 91 +#define RMIO_PWM1_BIP_CNTR_B4 92 +#define RMIO_PWM1_BIP_CNTR_B5 93 +#define RMIO_PDM_CLK1 94 +#define RMIO_ETH_RMII0_PPSCLK 95 +#define RMIO_ETH_RMII0_PPSTRIG 96 +#define RMIO_ETH_RMII1_PPSCLK 97 +#define RMIO_ETH_RMII1_PPSTRIG 98 + +#endif /* __DT_BINDINGS_PINCTRL_ROCKCHIP_RK3506_RMIO_H */ --=20 2.34.1 From nobody Fri Dec 19 13:27:15 2025 Received: from mail-m21470.qiye.163.com (mail-m21470.qiye.163.com [117.135.214.70]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4783B28725C; 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(unknown [58.22.7.114]) by smtp.qiye.163.com (Hmail) with ESMTP id 2c3493a70; Sat, 6 Dec 2025 13:08:55 +0800 (GMT+08:00) From: Ye Zhang To: Ye Zhang , Linus Walleij , Heiko Stuebner Cc: Bartosz Golaszewski , Rob Herring , Krzysztof Kozlowski , Conor Dooley , linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, tao.huang@rock-chips.com Subject: [PATCH v2 7/8] dt-bindings: pinctrl: rockchip: Add RMIO controller binding Date: Sat, 6 Dec 2025 13:08:43 +0800 Message-Id: <20251206050844.402958-8-ye.zhang@rock-chips.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20251206050844.402958-1-ye.zhang@rock-chips.com> References: <20251206050844.402958-1-ye.zhang@rock-chips.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-HM-Tid: 0a9af210229409d8kunmae94618c4ed3f36 X-HM-MType: 1 X-HM-Spam-Status: e1kfGhgUHx5ZQUpXWQgPGg8OCBgUHx5ZQUlOS1dZFg8aDwILHllBWSg2Ly tZV1koWUFDSUNOT01LS0k3V1ktWUFJV1kPCRoVCBIfWUFZGhkaS1ZIHUxPTBlKTBhITB1WFRQJFh oXVRMBExYaEhckFA4PWVdZGBILWUFZTkNVSUlVTFVKSk9ZV1kWGg8SFR0UWUFZT0tIVUpLSU9PT0 hVSktLVUpCS0tZBg++ DKIM-Signature: a=rsa-sha256; b=Nahoi33a9W7LKo9zBZsKTBZmqp6NoX79vHrjDvTS7bhW0RXV/xE8MzpUWWK+x16thFH0Zj18qnxkaLMNOZfwhCz89tX4j4xtL4hcnuIidmUY9ytLTBlXBE81klggfepXLlIUgBmyWi9mQHQQSOPAByDC4et3+FZrW1EKeuJS0NU=; s=default; c=relaxed/relaxed; d=rock-chips.com; v=1; bh=B8Pv8F+oXHHjCE0zxtFanqIKrinBiYf5cSRDVL4WFrI=; h=date:mime-version:subject:message-id:from; Content-Type: text/plain; charset="utf-8" Add device tree binding for the RMIO (Rockchip Matrix I/O) controller which is a sub-device of the main pinctrl on some Rockchip SoCs. Signed-off-by: Ye Zhang --- .../bindings/pinctrl/rockchip,pinctrl.yaml | 9 ++ .../bindings/pinctrl/rockchip,rmio.yaml | 130 ++++++++++++++++++ 2 files changed, 139 insertions(+) create mode 100644 Documentation/devicetree/bindings/pinctrl/rockchip,rmio= .yaml diff --git a/Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.yam= l b/Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.yaml index 93bf8f352e48..01df0a51ff83 100644 --- a/Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.yaml @@ -83,6 +83,15 @@ required: - rockchip,grf =20 patternProperties: + "rmio[0-9]*$": + type: object + + $ref: "/schemas/pinctrl/rockchip,rmio.yaml#" + + description: + The RMIO (Rockchip Matrix I/O) controller node which functions as a + sub-device of the main pinctrl to handle flexible function routing. + "gpio@[0-9a-f]+$": type: object =20 diff --git a/Documentation/devicetree/bindings/pinctrl/rockchip,rmio.yaml b= /Documentation/devicetree/bindings/pinctrl/rockchip,rmio.yaml new file mode 100644 index 000000000000..28ec5ad62061 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/rockchip,rmio.yaml @@ -0,0 +1,130 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/rockchip,rmio.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: RMIO (Rockchip Matrix I/O) Controller + +maintainers: + - Heiko Stuebner + +description: | + The RMIO controller provides a flexible routing matrix that allows mappi= ng + various internal peripheral functions (UART, SPI, PWM, etc.) to specific + physical pins. This block is typically a sub-block of the GRF + (General Register Files). + +properties: + compatible: + enum: + - rockchip,rmio + + rockchip,grf: + $ref: /schemas/types.yaml#/definitions/phandle + description: + The phandle of the syscon node for the GRF registers. + + rockchip,offset: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + The offset of the RMIO configuration registers within the GRF. + + rockchip,pins-num: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + The number of physical pins supported by this RMIO instance. + Used for boundary checking and driver initialization. + +additionalProperties: + type: object + additionalProperties: + type: object + properties: + rockchip,rmio: + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" + description: | + A list of pin-function pairs. The format is . + - pin_id: The index of the RMIO pin (0 to pins-num - 1). + - function_id: The mux value selecting the peripheral function. + minItems: 1 + items: + items: + - minimum: 0 + maximum: 31 + description: + RMIO Pin ID. + - minimum: 0 + maximum: 98 + description: + Function ID. + + required: + - rockchip,rmio + + additionalProperties: false + + additionalProperties: false + +required: + - compatible + - rockchip,grf + - rockchip,offset + - rockchip,pins-num + +additionalProperties: false + +examples: + - | + #include + #include + #include + + pinctrl { + #address-cells =3D <1>; + #size-cells =3D <1>; + ranges; + + rmio { + compatible =3D "rockchip,rmio"; + rockchip,grf =3D <&grf_pmu>; + rockchip,offset =3D <0x80>; + rockchip,pins-num =3D <32>; + + rmio-uart { + rmio_pin27_uart1_tx: rmio-pin27-uart1-tx { + rockchip,rmio =3D ; + }; + + rmio_pin28_uart1_rx: rmio-pin28-uart1-rx { + rockchip,rmio =3D ; + }; + }; + }; + + pcfg_pull_default: pcfg-pull-default { + bias-pull-pin-default; + }; + + rm { + rmio_pin27_pins: rmio-pin27-pins { + rockchip,pins =3D <1 RK_PC2 7 &pcfg-pull-default>; + }; + + rmio_pin28_pins: rmio-pin28-pins { + rockchip,pins =3D <1 RK_PC3 7 &pcfg-pull-default>; + }; + }; + }; + + uart1: serial@20064000 { + compatible =3D "snps,dw-apb-uart"; + reg =3D <0x20064000 0x400>; + interrupts =3D ; + clocks =3D <&mux_uart2>; + pinctrl-0 =3D <&rmio_pin27_pins &rmio_pin27_uart1_tx + &rmio_pin28_pins &rmio_pin28_uart1_rx>; + pinctrl-names =3D "default"; + reg-io-width =3D <1>; + reg-shift =3D <2>; + }; --=20 2.34.1 From nobody Fri Dec 19 13:27:15 2025 Received: from mail-m155115.qiye.163.com (mail-m155115.qiye.163.com [101.71.155.115]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 238002877CF; Sat, 6 Dec 2025 05:24:28 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=101.71.155.115 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764998673; cv=none; b=Q49SO2aX3X3zcsD8u8QQYSVbKOKmkG1jte7nHJcNB+EWVwSBb93Xi9TB9k26sde7HVHM2423iN+nhS3s+oMOBLLi1Rn17vhLaAYYaJxsXO8/ZgwXNwJY084qrNOVzhNiAWb/dI+LftZ0Itgd6f9B0tpWkBLGXpkKJDxMTVhhImg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764998673; c=relaxed/simple; bh=bu4Bjl8CBIuGS14M00Oy58tIuAnTouNPohb+z4oNjO4=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=pEEFA22G9h4jgM25eIaCMZcQ4+L5LSiwx1BE6YisTpgwDzrMh3sbujAMm4vGG4HywCzFLtCKA643IvRu8AhSE1FHm67BVYrd6XEeaHkbe8qQx0N4taBM6/3jCASGp5f6bwGvl7+vSGrPXr/HgOaJVC1wUXjuJoZQlIH2lHlWJPM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=rock-chips.com; spf=pass smtp.mailfrom=rock-chips.com; dkim=pass (1024-bit key) header.d=rock-chips.com header.i=@rock-chips.com header.b=dwJkpMXy; arc=none smtp.client-ip=101.71.155.115 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=rock-chips.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=rock-chips.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=rock-chips.com header.i=@rock-chips.com header.b="dwJkpMXy" Received: from rockchip.. (unknown [58.22.7.114]) by smtp.qiye.163.com (Hmail) with ESMTP id 2c3493a71; Sat, 6 Dec 2025 13:08:56 +0800 (GMT+08:00) From: Ye Zhang To: Ye Zhang , Linus Walleij , Heiko Stuebner Cc: Bartosz Golaszewski , Rob Herring , Krzysztof Kozlowski , Conor Dooley , linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, tao.huang@rock-chips.com Subject: [PATCH v2 8/8] pinctrl: rockchip: add rmio support Date: Sat, 6 Dec 2025 13:08:44 +0800 Message-Id: <20251206050844.402958-9-ye.zhang@rock-chips.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20251206050844.402958-1-ye.zhang@rock-chips.com> References: <20251206050844.402958-1-ye.zhang@rock-chips.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-HM-Tid: 0a9af210278f09d8kunmae94618c4ed3fbe X-HM-MType: 1 X-HM-Spam-Status: e1kfGhgUHx5ZQUpXWQgPGg8OCBgUHx5ZQUlOS1dZFg8aDwILHllBWSg2Ly tZV1koWUFDSUNOT01LS0k3V1ktWUFJV1kPCRoVCBIfWUFZQklOGlYYTUpLT09LGUgaT0NWFRQJFh oXVRMBExYaEhckFA4PWVdZGBILWUFZTkNVSUlVTFVKSk9ZV1kWGg8SFR0UWUFZT0tIVUpLSU9PT0 hVSktLVUpCS0tZBg++ DKIM-Signature: a=rsa-sha256; b=dwJkpMXyJBb4XIqrMDT0/ec+aFkwDUy15/zr0pDiI82JWy6zhi1WyrVnqnYw+u8igR3xgqpF9yk9pGoEbUI7VKvpesytkJyFETJqwZa1S+yDGcve5++ucI5qrKsS+jf1R1L3H1NHT9Xi91uVnrHeogQYvzC6OhzcmVqFkFunxVs=; s=default; c=relaxed/relaxed; d=rock-chips.com; v=1; bh=XB2+mXD6L2f+O1TNSUvMVZ7J8bMDiXM9ToZL/Hju3aU=; h=date:mime-version:subject:message-id:from; Content-Type: text/plain; charset="utf-8" Support rockchip matrix io Signed-off-by: Ye Zhang --- drivers/pinctrl/pinctrl-rockchip.c | 397 ++++++++++++++++++++++++++++- drivers/pinctrl/pinctrl-rockchip.h | 42 +++ 2 files changed, 438 insertions(+), 1 deletion(-) diff --git a/drivers/pinctrl/pinctrl-rockchip.c b/drivers/pinctrl/pinctrl-r= ockchip.c index dc7ef12dfcb0..66bd4a981f62 100644 --- a/drivers/pinctrl/pinctrl-rockchip.c +++ b/drivers/pinctrl/pinctrl-rockchip.c @@ -3961,6 +3961,11 @@ static const struct of_device_id rockchip_bank_match= [] =3D { {}, }; =20 +static const struct of_device_id rockchip_rmio_dt_match[] =3D { + { .compatible =3D "rockchip,rmio" }, + {}, +}; + static void rockchip_pinctrl_child_count(struct rockchip_pinctrl *info, struct device_node *np) { @@ -3969,6 +3974,8 @@ static void rockchip_pinctrl_child_count(struct rockc= hip_pinctrl *info, for_each_child_of_node(np, child) { if (of_match_node(rockchip_bank_match, child)) continue; + if (of_match_node(rockchip_rmio_dt_match, child)) + continue; =20 info->nfunctions++; info->ngroups +=3D of_get_child_count(child); @@ -4101,6 +4108,8 @@ static int rockchip_pinctrl_parse_dt(struct platform_= device *pdev, for_each_child_of_node_scoped(np, child) { if (of_match_node(rockchip_bank_match, child)) continue; + if (of_match_node(rockchip_rmio_dt_match, child)) + continue; =20 ret =3D rockchip_pinctrl_parse_functions(child, info, i++); if (ret) { @@ -4431,6 +4440,384 @@ static void rockchip_pinctrl_remove(struct platform= _device *pdev) } } =20 +static int rockchip_rmio_set_mux(struct rockchip_rmio *info, int id, int f= unc) +{ + struct device *dev =3D info->dev; + + if (id >=3D info->nr_pins) + return -EINVAL; + + dev_dbg(dev, "setting function of %s%d to %d\n", dev_name(dev), id, func); + + return regmap_write(info->regmap, info->offset + id * 4, + RK_RMIO_WRITE_ENABLE_MASK | func); +} + +static int rockchip_rmio_parse_groups(struct device_node *np, + struct rockchip_rmio_group *grp, + struct rockchip_rmio *info, + u32 index) +{ + struct device *dev =3D info->dev; + int count; + u32 *tmp; + int i; + + dev_dbg(dev, "group(%d): %pOFn\n", index, np); + + /* + * the binding format is rockchip,rmio =3D , + * do sanity check and calculate pins number + */ + count =3D of_property_count_u32_elems(np, "rockchip,rmio"); + if (count <=3D 0 || count % 2 !=3D 0) + return -EINVAL; + + tmp =3D kcalloc(count, sizeof(u32), GFP_KERNEL); + if (!tmp) + return -ENOMEM; + + of_property_read_u32_array(np, "rockchip,rmio", tmp, count); + + /* Initialise group */ + grp->name =3D np->name; + grp->npins =3D count / 2; + grp->pins =3D devm_kcalloc(dev, grp->npins, sizeof(*grp->pins), GFP_KERNE= L); + grp->func =3D devm_kcalloc(dev, grp->npins, sizeof(*grp->func), GFP_KERNE= L); + if (!grp->pins || !grp->func) + return -ENOMEM; + + for (i =3D 0; i < grp->npins; i++) { + grp->pins[i] =3D tmp[2 * i]; + grp->func[i] =3D tmp[2 * i + 1]; + } + kfree(tmp); + + return 0; +} + +static int rockchip_rmio_parse_functions(struct device_node *np, + struct rockchip_rmio *info, + u32 index) +{ + struct device *dev =3D info->dev; + struct device_node *child; + struct rockchip_rmio_func *func; + struct rockchip_rmio_group *grp; + int ret; + u32 i, grp_index =3D 0; + + dev_dbg(dev, "parse function(%d): %pOFn\n", index, np); + + for (i =3D 0, func =3D info->functions; i < index; i++, func++) + grp_index +=3D func->ngroups; + + func =3D &info->functions[index]; + + /* Initialise function */ + func->name =3D np->name; + func->ngroups =3D of_get_child_count(np); + if (func->ngroups <=3D 0) + return 0; + + func->groups =3D devm_kcalloc(dev, func->ngroups, sizeof(*func->groups), = GFP_KERNEL); + if (!func->groups) + return -ENOMEM; + + i =3D 0; + for_each_child_of_node(np, child) { + func->groups[i] =3D child->name; + grp =3D &info->groups[grp_index + i]; + ret =3D rockchip_rmio_parse_groups(child, grp, info, i++); + if (ret) { + of_node_put(child); + return ret; + } + } + + return 0; +} + +static int rockchip_rmio_parse_dt(struct platform_device *pdev, + struct rockchip_rmio *info) +{ + struct device *dev =3D &pdev->dev; + struct device_node *np =3D dev->of_node; + struct device_node *child; + int ret; + int i =3D 0; + + for_each_child_of_node(np, child) { + info->nfunctions++; + info->ngroups +=3D of_get_child_count(child); + } + + dev_dbg(dev, "nfunctions =3D %d\n", info->nfunctions); + dev_dbg(dev, "ngroups =3D %d\n", info->ngroups); + + info->functions =3D devm_kcalloc(dev, info->nfunctions, sizeof(*info->fun= ctions), GFP_KERNEL); + if (!info->functions) + return -ENOMEM; + + info->groups =3D devm_kcalloc(dev, info->ngroups, sizeof(*info->groups), = GFP_KERNEL); + if (!info->groups) + return -ENOMEM; + + for_each_child_of_node(np, child) { + ret =3D rockchip_rmio_parse_functions(child, info, i++); + if (ret) { + dev_err(dev, "failed to parse function, ret =3D %d\n", ret); + of_node_put(child); + return ret; + } + } + + return 0; +} + +static int rockchip_rmio_get_groups_count(struct pinctrl_dev *pctldev) +{ + struct rockchip_rmio *info =3D pinctrl_dev_get_drvdata(pctldev); + + return info->ngroups; +} + +static const char *rockchip_rmio_get_group_name(struct pinctrl_dev *pctlde= v, + unsigned int selector) +{ + struct rockchip_rmio *info =3D pinctrl_dev_get_drvdata(pctldev); + + return info->groups[selector].name; +} + +static int rockchip_rmio_get_group_pins(struct pinctrl_dev *pctldev, + unsigned int selector, + const unsigned int **pins, + unsigned int *npins) +{ + struct rockchip_rmio *info =3D pinctrl_dev_get_drvdata(pctldev); + + if (selector >=3D info->ngroups) + return -EINVAL; + + *pins =3D info->groups[selector].pins; + *npins =3D info->groups[selector].npins; + + return 0; +} + +static int rockchip_rmio_dt_node_to_map(struct pinctrl_dev *pctldev, + struct device_node *np, + struct pinctrl_map **map, + unsigned int *num_maps) +{ + struct rockchip_rmio *info =3D pinctrl_dev_get_drvdata(pctldev); + struct device *dev =3D info->dev; + struct pinctrl_map *new_map; + struct device_node *parent; + + new_map =3D kcalloc(1, sizeof(*new_map), GFP_KERNEL); + if (!new_map) + return -ENOMEM; + + *map =3D new_map; + *num_maps =3D 1; + + /* the rmio only need to create mux map */ + parent =3D of_get_parent(np); + if (!parent) { + kfree(new_map); + return -EINVAL; + } + new_map->type =3D PIN_MAP_TYPE_MUX_GROUP; + new_map->data.mux.function =3D parent->name; + new_map->data.mux.group =3D np->name; + of_node_put(parent); + + dev_dbg(dev, "maps: function %s group %s\n", + (*map)->data.mux.function, (*map)->data.mux.group); + + return 0; +} + +static void rockchip_rmio_dt_free_map(struct pinctrl_dev *pctldev, + struct pinctrl_map *map, + unsigned int num_maps) +{ + kfree(map); +} + +static const struct pinctrl_ops rockchip_rmio_pctrl_ops =3D { + .get_groups_count =3D rockchip_rmio_get_groups_count, + .get_group_name =3D rockchip_rmio_get_group_name, + .get_group_pins =3D rockchip_rmio_get_group_pins, + .dt_node_to_map =3D rockchip_rmio_dt_node_to_map, + .dt_free_map =3D rockchip_rmio_dt_free_map, +}; + +static int rockchip_rmio_get_funcs_count(struct pinctrl_dev *pctldev) +{ + struct rockchip_rmio *info =3D pinctrl_dev_get_drvdata(pctldev); + + return info->nfunctions; +} + +static const char *rockchip_rmio_get_func_name(struct pinctrl_dev *pctldev, + unsigned int selector) +{ + struct rockchip_rmio *info =3D pinctrl_dev_get_drvdata(pctldev); + + return info->functions[selector].name; +} + +static int rockchip_rmio_get_groups(struct pinctrl_dev *pctldev, + unsigned int selector, + const char * const **groups, + unsigned int * const num_groups) +{ + struct rockchip_rmio *info =3D pinctrl_dev_get_drvdata(pctldev); + + *groups =3D info->functions[selector].groups; + *num_groups =3D info->functions[selector].ngroups; + + return 0; +} + +static int rockchip_rmio_pmx_set(struct pinctrl_dev *pctldev, + unsigned int selector, + unsigned int group) +{ + struct rockchip_rmio *info =3D pinctrl_dev_get_drvdata(pctldev); + const unsigned int *pins =3D info->groups[group].pins; + const unsigned int *func =3D info->groups[group].func; + struct device *dev =3D info->dev; + int cnt, ret =3D 0; + + dev_dbg(dev, "enable function %s group %s\n", + info->functions[selector].name, info->groups[group].name); + + /* + * for each pin in the pin group selected, program the corresponding + * pin function number in the config register. + */ + for (cnt =3D 0; cnt < info->groups[group].npins; cnt++) { + ret =3D rockchip_rmio_set_mux(info, pins[cnt], func[cnt]); + if (ret) + break; + } + + if (ret && cnt) { + /* revert the already done pin settings */ + for (cnt--; cnt >=3D 0; cnt--) + rockchip_rmio_set_mux(info, pins[cnt], RK_RMIO_NC); + + return ret; + } + + return 0; +} + +static const struct pinmux_ops rockchip_rmio_pmx_ops =3D { + .get_functions_count =3D rockchip_rmio_get_funcs_count, + .get_function_name =3D rockchip_rmio_get_func_name, + .get_function_groups =3D rockchip_rmio_get_groups, + .set_mux =3D rockchip_rmio_pmx_set, +}; + +static int rockchip_rmio_register(struct platform_device *pdev, + struct rockchip_rmio *info) +{ + struct pinctrl_desc *ctrldesc =3D &info->pctl; + struct pinctrl_pin_desc *pindesc, *pdesc; + struct device *dev =3D &pdev->dev; + char **pin_names; + int ret; + int i; + int nr_pins =3D info->nr_pins; + + ctrldesc->name =3D dev_name(dev); + ctrldesc->owner =3D THIS_MODULE; + ctrldesc->pctlops =3D &rockchip_rmio_pctrl_ops; + ctrldesc->pmxops =3D &rockchip_rmio_pmx_ops; + + pindesc =3D devm_kcalloc(dev, nr_pins, sizeof(*pindesc), GFP_KERNEL); + if (!pindesc) + return -ENOMEM; + + ctrldesc->pins =3D pindesc; + ctrldesc->npins =3D nr_pins; + + pdesc =3D pindesc; + pin_names =3D devm_kasprintf_strarray(dev, dev_name(dev), nr_pins); + if (IS_ERR(pin_names)) + return PTR_ERR(pin_names); + for (i =3D 0; i < nr_pins; i++) { + pdesc->number =3D i; + pdesc->name =3D pin_names[i]; + pdesc++; + } + + ret =3D rockchip_rmio_parse_dt(pdev, info); + if (ret) + return ret; + + info->pctl_dev =3D devm_pinctrl_register(dev, ctrldesc, info); + if (IS_ERR(info->pctl_dev)) + return dev_err_probe(dev, PTR_ERR(info->pctl_dev), + "could not register pinctrl driver\n"); + + return 0; +} + +static int rockchip_rmio_probe(struct platform_device *pdev) +{ + struct rockchip_rmio *info; + struct device *dev =3D &pdev->dev; + struct device_node *np =3D pdev->dev.of_node; + int ret; + + info =3D devm_kzalloc(&pdev->dev, sizeof(*info), GFP_KERNEL); + if (!info) + return -ENOMEM; + + info->dev =3D dev; + + info->regmap =3D syscon_regmap_lookup_by_phandle(np, "rockchip,grf"); + if (IS_ERR(info->regmap)) { + dev_err(&pdev->dev, "missing rockchip,grf property\n"); + return PTR_ERR(info->regmap); + } + + ret =3D of_property_read_u32(np, "rockchip,offset", &info->offset); + if (ret < 0) { + dev_err(&pdev->dev, "missing rockchip,offset property\n"); + return ret; + } + + ret =3D of_property_read_u32(np, "rockchip,pins-num", &info->nr_pins); + if (ret < 0) { + dev_err(&pdev->dev, "missing rockchip,pins-num property\n"); + return ret; + } + + ret =3D rockchip_rmio_register(pdev, info); + if (ret) + return ret; + + platform_set_drvdata(pdev, info); + dev_info(dev, "probed %pfw\n", dev_fwnode(dev)); + + return 0; +} + +static struct platform_driver rockchip_rmio_driver =3D { + .probe =3D rockchip_rmio_probe, + .driver =3D { + .name =3D "rockchip-rmio", + .of_match_table =3D rockchip_rmio_dt_match, + }, +}; + static struct rockchip_pin_bank px30_pin_banks[] =3D { PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU, IOMUX_SOURCE_PMU, @@ -5190,12 +5577,19 @@ static struct platform_driver rockchip_pinctrl_driv= er =3D { =20 static int __init rockchip_pinctrl_drv_register(void) { - return platform_driver_register(&rockchip_pinctrl_driver); + int ret; + + ret =3D platform_driver_register(&rockchip_pinctrl_driver); + if (ret) + return ret; + + return platform_driver_register(&rockchip_rmio_driver); } postcore_initcall(rockchip_pinctrl_drv_register); =20 static void __exit rockchip_pinctrl_drv_unregister(void) { + platform_driver_unregister(&rockchip_rmio_driver); platform_driver_unregister(&rockchip_pinctrl_driver); } module_exit(rockchip_pinctrl_drv_unregister); @@ -5204,3 +5598,4 @@ MODULE_DESCRIPTION("ROCKCHIP Pin Controller Driver"); MODULE_LICENSE("GPL"); MODULE_ALIAS("platform:pinctrl-rockchip"); MODULE_DEVICE_TABLE(of, rockchip_pinctrl_dt_match); +MODULE_DEVICE_TABLE(of, rockchip_rmio_dt_match); diff --git a/drivers/pinctrl/pinctrl-rockchip.h b/drivers/pinctrl/pinctrl-r= ockchip.h index fe18b62ed994..db875f7a3d2f 100644 --- a/drivers/pinctrl/pinctrl-rockchip.h +++ b/drivers/pinctrl/pinctrl-rockchip.h @@ -183,6 +183,9 @@ #define RK_GPIO4_D6 158 #define RK_GPIO4_D7 159 =20 +#define RK_RMIO_NC 0 +#define RK_RMIO_WRITE_ENABLE_MASK 0xFFFF0000 + enum rockchip_pinctrl_type { PX30, RV1108, @@ -473,4 +476,43 @@ struct rockchip_pinctrl { unsigned int nfunctions; }; =20 +/** + * struct rockchip_rmio_group: represent a group of pins in RMIO controlle= r. + * @name: name of the pin group, used to lookup the group. + * @pins: array of pins included in this group. + * @npins: number of pins included in this group. + * @func: local pins function select + */ +struct rockchip_rmio_group { + const char *name; + unsigned int npins; + unsigned int *pins; + unsigned int *func; +}; + +/** + * struct rockchip_rmio_func: represent a RMIO pin function. + * @name: name of the RMIO function, used to lookup the function. + * @groups: array of group names that can provide this RMIO function. + * @ngroups: number of groups included in @groups. + */ +struct rockchip_rmio_func { + const char *name; + const char **groups; + u8 ngroups; +}; + +struct rockchip_rmio { + struct regmap *regmap; + u32 offset; + struct device *dev; + struct pinctrl_desc pctl; + struct pinctrl_dev *pctl_dev; + unsigned int nr_pins; + struct rockchip_rmio_group *groups; + unsigned int ngroups; + struct rockchip_rmio_func *functions; + unsigned int nfunctions; +}; + #endif --=20 2.34.1