From nobody Tue Dec 16 14:38:32 2025 Received: from mail-pj1-f74.google.com (mail-pj1-f74.google.com [209.85.216.74]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E556D30B524 for ; Sat, 6 Dec 2025 00:18:51 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.216.74 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764980333; cv=none; b=RTIeBgITZH9KteA1ZYcXpBuiXD7xUbahwCs2B9+ufuagVc8e12Sd+pQRz39h5CR023iSGBEaKsVhp5Gggae+/UGNx9BVB2wvo0e32mY4OHMnjnvcTcSYpfCj8pcxUyKFDfDblHBEUhctr6CkQhzC0Z141+dPfAsHNjtAua1XnLg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764980333; c=relaxed/simple; bh=UVioe3cP1bYPqsGVmWsr21dHZMl8z/Ov/PsUa6Us+s0=; h=Date:In-Reply-To:Mime-Version:References:Message-ID:Subject:From: To:Cc:Content-Type; b=PmooQle+7gPttdYwagi+paRMvh1XAM/Sz3PESgvs4jO70+Ldw9IfNY1ZvUM91pEuGK5DFxCqTdoLjf1LMaAhezMeAeXQV26R2FTOVl0R9vybJNbXSFk/yst2E+xdVeqY/HczACtG/taOoTVfb0I9mKPP8c1fepFaJluJEQ2cZ+Q= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=google.com; spf=pass smtp.mailfrom=flex--seanjc.bounces.google.com; dkim=pass (2048-bit key) header.d=google.com header.i=@google.com header.b=1k/cmGSx; arc=none smtp.client-ip=209.85.216.74 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=google.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=flex--seanjc.bounces.google.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=google.com header.i=@google.com header.b="1k/cmGSx" Received: by mail-pj1-f74.google.com with SMTP id 98e67ed59e1d1-3438b1220bcso3062579a91.2 for ; Fri, 05 Dec 2025 16:18:51 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20230601; t=1764980331; x=1765585131; darn=vger.kernel.org; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:reply-to:from:to:cc:subject:date:message-id:reply-to; bh=igvZhN+qFglUKI0D9M5DwytuE53IkpoWDDVxPCMFY70=; b=1k/cmGSxnUJf9BbckwKdkvy4OZTsqwjslvKaZMhbHkKF7/PnxBUsgg8TcIxzOzOgbk aTw9rz8+Ej2wapUHCe+gocU+bEnJpqi7EKa/jjuyy0XeV1xI9U0b4u9aThcbA+BxdJyw h3jrreq2K+TgFdzGrbIu2WkxGbbVYiQYifhmF++CEm3vZuyUJoU60Q7Aza3O7XDfWIUO 54/g/7zQ5j9mPrCJYX1ZJsJ5gL74PuZGk9poeyo2jkFUgWmMxT0yweqfEG2fiNYUs9IB HzFgL0wZ7AIQdVTJTh1Uru6XXZN2zRfCBaicy1wIGiudjhN3Qs0jm4wtm1/h1dH7NHDP 91SQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1764980331; x=1765585131; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:reply-to:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=igvZhN+qFglUKI0D9M5DwytuE53IkpoWDDVxPCMFY70=; b=cKuYGYNLSGgdSwCyed7zOe/gb3xWOsOnZRyB+a4zvHFJKvBTn3tUTB9Qcm0+iV8at1 DKfLjd67INWEArfD0eISekzb8gCQWjRxz12/JziWsZ9ThghE3cfo+Dd6s+KOhGayEmg4 TYE+IHhp9ESoaW98saEXicyrsVdpAfsmU5kijIYgj7z/fmBdtOGYvQUS1sayOyfA9eKn ES4dLh0vQDEhzPNr5yuW5EXWtrh1HML5BMXoEeYDFOFw+JxGkxG9FJP5RfKJCSLiVm6Q 77M8WAkQ5k4MQrXu5NiYsNGWI9xtFucFU3YpVrqh2IrGTb4m4mHL8KwH60eAiUjo7S7j 3obg== X-Forwarded-Encrypted: i=1; AJvYcCVgAc7dP1iQr2E4B0wUhELQAZJXbw+zVGVr2RUH13MJcIMCxmZarllYa2meEMPxuGcu9VKrcjU5mtawUco=@vger.kernel.org X-Gm-Message-State: AOJu0YxT2LkYcroiflZk5/qw6Ko4WlT6SUJcOJ1hOE5sBNKuBU9CQLm8 vRibZ8V8yR/PhXgrSD+nLQ2TVxZ8ZIdNIXdvsKQznd7i0d+o6fabEGXiLQxNjqVLC8s/yb38uWt AqawGxA== X-Google-Smtp-Source: AGHT+IELoQ04EyxWWYOkaKJLtcnZ6DpPNmUnBZcM+48DKxRjXGIekKbShjkFhb2K5/ObBWXw0pAx2mabe98= X-Received: from pjbsk6.prod.google.com ([2002:a17:90b:2dc6:b0:340:a5c6:acc3]) (user=seanjc job=prod-delivery.src-stubby-dispatcher) by 2002:a17:90a:fc47:b0:343:d70e:bef0 with SMTP id 98e67ed59e1d1-349a267fbc8mr680584a91.21.1764980331409; Fri, 05 Dec 2025 16:18:51 -0800 (PST) Reply-To: Sean Christopherson Date: Fri, 5 Dec 2025 16:17:18 -0800 In-Reply-To: <20251206001720.468579-1-seanjc@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20251206001720.468579-1-seanjc@google.com> X-Mailer: git-send-email 2.52.0.223.gf5cc29aaa4-goog Message-ID: <20251206001720.468579-43-seanjc@google.com> Subject: [PATCH v6 42/44] KVM: VMX: Dedup code for adding MSR to VMCS's auto list From: Sean Christopherson To: Marc Zyngier , Oliver Upton , Tianrui Zhao , Bibo Mao , Huacai Chen , Anup Patel , Paul Walmsley , Palmer Dabbelt , Albert Ou , Xin Li , "H. Peter Anvin" , Andy Lutomirski , Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Sean Christopherson , Paolo Bonzini Cc: linux-arm-kernel@lists.infradead.org, kvmarm@lists.linux.dev, kvm@vger.kernel.org, loongarch@lists.linux.dev, kvm-riscv@lists.infradead.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, Mingwei Zhang , Xudong Hao , Sandipan Das , Dapeng Mi , Xiong Zhang , Manali Shukla , Jim Mattson Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add a helper to add an MSR to a VMCS's "auto" list to deduplicate the code in add_atomic_switch_msr(), and so that the functionality can be used in the future for managing the MSR auto-store list. No functional change intended. Signed-off-by: Sean Christopherson Reviewed-by: Dapeng Mi --- arch/x86/kvm/vmx/vmx.c | 41 +++++++++++++++++++---------------------- 1 file changed, 19 insertions(+), 22 deletions(-) diff --git a/arch/x86/kvm/vmx/vmx.c b/arch/x86/kvm/vmx/vmx.c index 018e01daab68..3f64d4b1b19c 100644 --- a/arch/x86/kvm/vmx/vmx.c +++ b/arch/x86/kvm/vmx/vmx.c @@ -1093,12 +1093,28 @@ static __always_inline void add_atomic_switch_msr_s= pecial(struct vcpu_vmx *vmx, vm_exit_controls_setbit(vmx, exit); } =20 +static void vmx_add_auto_msr(struct vmx_msrs *m, u32 msr, u64 value, + unsigned long vmcs_count_field, struct kvm *kvm) +{ + int i; + + i =3D vmx_find_loadstore_msr_slot(m, msr); + if (i < 0) { + if (KVM_BUG_ON(m->nr =3D=3D MAX_NR_LOADSTORE_MSRS, kvm)) + return; + + i =3D m->nr++; + m->val[i].index =3D msr; + vmcs_write32(vmcs_count_field, m->nr); + } + m->val[i].value =3D value; +} + static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr, u64 guest_val, u64 host_val) { struct msr_autoload *m =3D &vmx->msr_autoload; struct kvm *kvm =3D vmx->vcpu.kvm; - int i; =20 switch (msr) { case MSR_EFER: @@ -1132,27 +1148,8 @@ static void add_atomic_switch_msr(struct vcpu_vmx *v= mx, unsigned msr, wrmsrq(MSR_IA32_PEBS_ENABLE, 0); } =20 - i =3D vmx_find_loadstore_msr_slot(&m->guest, msr); - if (i < 0) { - if (KVM_BUG_ON(m->guest.nr =3D=3D MAX_NR_LOADSTORE_MSRS, kvm)) - return; - - i =3D m->guest.nr++; - m->guest.val[i].index =3D msr; - vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->guest.nr); - } - m->guest.val[i].value =3D guest_val; - - i =3D vmx_find_loadstore_msr_slot(&m->host, msr); - if (i < 0) { - if (KVM_BUG_ON(m->host.nr =3D=3D MAX_NR_LOADSTORE_MSRS, kvm)) - return; - - i =3D m->host.nr++; - m->host.val[i].index =3D msr; - vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->host.nr); - } - m->host.val[i].value =3D host_val; + vmx_add_auto_msr(&m->guest, msr, guest_val, VM_ENTRY_MSR_LOAD_COUNT, kvm); + vmx_add_auto_msr(&m->guest, msr, host_val, VM_EXIT_MSR_LOAD_COUNT, kvm); } =20 static bool update_transition_efer(struct vcpu_vmx *vmx) --=20 2.52.0.223.gf5cc29aaa4-goog