From nobody Tue Dec 16 14:43:32 2025 Received: from mail-pj1-f73.google.com (mail-pj1-f73.google.com [209.85.216.73]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E66AC2F7AD0 for ; Sat, 6 Dec 2025 00:18:28 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.216.73 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764980311; cv=none; b=GiTR/oYS3Y7lRN3q+xKBiyoSzwaPMcDHlQMoPz1fPmhVp1+ReJ0iuBfZy10v1my2eY0DvcUQajaPUbbDDXls3Vu5z3a0tM/frzJTP0DCWtceKYzIce1qPyrpzO2XZn/hfehG8GmWjWu5DXnN4Vy+r/zOKDTskebffBfUjfcRBZ4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764980311; c=relaxed/simple; bh=jnmh0698KpE63YRCvIEZAjn7c1Lr7TEaV4sjEsIEpYo=; h=Date:In-Reply-To:Mime-Version:References:Message-ID:Subject:From: To:Cc:Content-Type; b=qmaxf1tWcSeSXvShqyVNVKzKAgZrcr/NS2xqEHIqpvfUOd1AoIWX3LBvWoGqgFsVHZ/tTmk3DZzQ8MH90DvEMeA6DwbkLMPvIKrv+q1hTDcbQchiCa65MVFgzmRWaOTcpkLm+8BiMW48DP+epqDI1o1oe4Rn/8qmbk5N05/iGJY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=google.com; spf=pass smtp.mailfrom=flex--seanjc.bounces.google.com; dkim=pass (2048-bit key) header.d=google.com header.i=@google.com header.b=mnuXyLYd; arc=none smtp.client-ip=209.85.216.73 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=google.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=flex--seanjc.bounces.google.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=google.com header.i=@google.com header.b="mnuXyLYd" Received: by mail-pj1-f73.google.com with SMTP id 98e67ed59e1d1-34992a92fa0so1248623a91.3 for ; Fri, 05 Dec 2025 16:18:28 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20230601; t=1764980308; x=1765585108; darn=vger.kernel.org; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:reply-to:from:to:cc:subject:date:message-id:reply-to; bh=4OfoQfKEgZFjrirIuizJ077/M4GdZrVaenba/hcoG9w=; b=mnuXyLYdBe2SGIG4Me7eq8ECbaVCwn7YZGFmEadJqEzHa63nG8JsOYQqCoUXfpeCtJ +2goHxl5yet7efQwGGWxpFLbeW6OKD1J9HtcnskPpG/aVrvVIKRDyxbpZL6n8lAZqKTT SkMBkkHWWjfWHPJIWtM44x29J0Ei3HUnSL5LWczinPq7rVf1CNIznXS9mo9y3f3rQ7+1 QDei6BqZdyinngVDEO/rlSjfmHHFovbc8rfn/YF9+PqrkY5X2TDGW+4SKd1BAoBTYAiO 7btDvyrO3JoejuyKVYpvXqrLVTVE1yWizlOWpXAY2GxGCRyPHn1k+tGKF3Q4wG+/VNGk Kp2A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1764980308; x=1765585108; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:reply-to:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=4OfoQfKEgZFjrirIuizJ077/M4GdZrVaenba/hcoG9w=; b=JNtFmhiZjz48ryOo45+ZXgqhr3xq1qT+/kbvTFjLxT6wnPJ7oZFtTaplD1iYVDK0IM Ckl5xQz75cRUnjrzhI85oS2iqXjia3EqDRS7GxPY86EkUgtBY+idHoPi8aoVLf11B3G7 UTNoTrIr0DrzSlRNvlvT84R4y7BM7OETW6CansNv+WQ6BcpW7x1LTQ8RonNrTV6CFRLP 0XXnW5nzzojh6PDNwGt2QlVi73TiEVmgN82lPBjcPPauAS7i+QMJYNSB7TxN912uDmLo eehJQmxvyqONwblAaYH8+jaOPZ8I/nTuRfRUlrUH0rscIy9o8axZ5DaPVrzWnVrocImA fG4A== X-Forwarded-Encrypted: i=1; AJvYcCWFMQ72sLVHF9YzQ4VncNGnd39eGOpvXNoVQdIuWd9UqD3NIFX7wa6J73eOhu1zHvmLGls+oE9V9KFOta0=@vger.kernel.org X-Gm-Message-State: AOJu0YzBqMHzBhN2a0yUm0ksbzXEwG8OMuugwL8BEQDrVN4XRh6a70/a sVhIVKD/kG2hIJ1ZwZwsfdBwpEev/XvU6XXYJLTNSoBCsRdmZB4m/Gln5FiURiQHqSZSHpP7D81 4gIV/pg== X-Google-Smtp-Source: AGHT+IHbD7B9YeGH7Tmr7JOXchgVNBxwJK8eblPXJXnk4Y9Y/l53ndcM8z2+XQN6T6Xmq93leyEKMn8mhtA= X-Received: from pjbcc9.prod.google.com ([2002:a17:90a:f109:b0:340:3e18:b5c]) (user=seanjc job=prod-delivery.src-stubby-dispatcher) by 2002:a17:90b:3ec7:b0:32e:528c:60ee with SMTP id 98e67ed59e1d1-349a25b9531mr659960a91.24.1764980308336; Fri, 05 Dec 2025 16:18:28 -0800 (PST) Reply-To: Sean Christopherson Date: Fri, 5 Dec 2025 16:17:07 -0800 In-Reply-To: <20251206001720.468579-1-seanjc@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20251206001720.468579-1-seanjc@google.com> X-Mailer: git-send-email 2.52.0.223.gf5cc29aaa4-goog Message-ID: <20251206001720.468579-32-seanjc@google.com> Subject: [PATCH v6 31/44] KVM: nVMX: Disable PMU MSR interception as appropriate while running L2 From: Sean Christopherson To: Marc Zyngier , Oliver Upton , Tianrui Zhao , Bibo Mao , Huacai Chen , Anup Patel , Paul Walmsley , Palmer Dabbelt , Albert Ou , Xin Li , "H. Peter Anvin" , Andy Lutomirski , Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Sean Christopherson , Paolo Bonzini Cc: linux-arm-kernel@lists.infradead.org, kvmarm@lists.linux.dev, kvm@vger.kernel.org, loongarch@lists.linux.dev, kvm-riscv@lists.infradead.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, Mingwei Zhang , Xudong Hao , Sandipan Das , Dapeng Mi , Xiong Zhang , Manali Shukla , Jim Mattson Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Mingwei Zhang Merge KVM's PMU MSR interception bitmaps with those of L1, i.e. merge the bitmaps of vmcs01 and vmcs12, e.g. so that KVM doesn't interpose on MSR accesses unnecessarily if L1 exposes a mediated PMU (or equivalent) to L2. Signed-off-by: Mingwei Zhang Co-developed-by: Dapeng Mi Signed-off-by: Dapeng Mi [sean: rewrite changelog and comment, omit MSRs that are always intercepted] Tested-by: Xudong Hao Signed-off-by: Sean Christopherson --- arch/x86/kvm/vmx/nested.c | 30 ++++++++++++++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/arch/x86/kvm/vmx/nested.c b/arch/x86/kvm/vmx/nested.c index b56ed2b1ac67..729cc1f05ac8 100644 --- a/arch/x86/kvm/vmx/nested.c +++ b/arch/x86/kvm/vmx/nested.c @@ -630,6 +630,34 @@ static inline void nested_vmx_set_intercept_for_msr(st= ruct vcpu_vmx *vmx, #define nested_vmx_merge_msr_bitmaps_rw(msr) \ nested_vmx_merge_msr_bitmaps(msr, MSR_TYPE_RW) =20 +static void nested_vmx_merge_pmu_msr_bitmaps(struct kvm_vcpu *vcpu, + unsigned long *msr_bitmap_l1, + unsigned long *msr_bitmap_l0) +{ + struct kvm_pmu *pmu =3D vcpu_to_pmu(vcpu); + struct vcpu_vmx *vmx =3D to_vmx(vcpu); + int i; + + /* + * Skip the merges if the vCPU doesn't have a mediated PMU MSR, i.e. if + * none of the MSRs can possibly be passed through to L1. + */ + if (!kvm_vcpu_has_mediated_pmu(vcpu)) + return; + + for (i =3D 0; i < pmu->nr_arch_gp_counters; i++) { + nested_vmx_merge_msr_bitmaps_rw(MSR_IA32_PERFCTR0 + i); + nested_vmx_merge_msr_bitmaps_rw(MSR_IA32_PMC0 + i); + } + + for (i =3D 0; i < pmu->nr_arch_fixed_counters; i++) + nested_vmx_merge_msr_bitmaps_rw(MSR_CORE_PERF_FIXED_CTR0 + i); + + nested_vmx_merge_msr_bitmaps_rw(MSR_CORE_PERF_GLOBAL_CTRL); + nested_vmx_merge_msr_bitmaps_read(MSR_CORE_PERF_GLOBAL_STATUS); + nested_vmx_merge_msr_bitmaps_write(MSR_CORE_PERF_GLOBAL_OVF_CTRL); +} + /* * Merge L0's and L1's MSR bitmap, return false to indicate that * we do not use the hardware. @@ -745,6 +773,8 @@ static inline bool nested_vmx_prepare_msr_bitmap(struct= kvm_vcpu *vcpu, nested_vmx_set_intercept_for_msr(vmx, msr_bitmap_l1, msr_bitmap_l0, MSR_IA32_PL3_SSP, MSR_TYPE_RW); =20 + nested_vmx_merge_pmu_msr_bitmaps(vcpu, msr_bitmap_l1, msr_bitmap_l0); + kvm_vcpu_unmap(vcpu, &map); =20 vmx->nested.force_msr_bitmap_recalc =3D false; --=20 2.52.0.223.gf5cc29aaa4-goog