From nobody Tue Dec 16 14:43:31 2025 Received: from mail-pf1-f201.google.com (mail-pf1-f201.google.com [209.85.210.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 99F1926E6E1 for ; Sat, 6 Dec 2025 00:17:49 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.210.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764980271; cv=none; b=OvbiPxUzXa+EETRXNhxc0XneMvjIVe/7C7qRwXSym3bnN5P4PSIW+bC89IqZlyRWYWiH4HOM8XY3oq4K7GFeTajQDcLFfwTULc8rQf/2wp3Sl3a6UKwy1l/Qd6OWD+FUpuI0aURNZPgGhJhmO2fA2cjnaC09UhUFCcYmGfqBD4k= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764980271; c=relaxed/simple; bh=1cCrG4DCg3nVbAW9oH4QXbYa70u3YhFDXh9Xhmff200=; h=Date:In-Reply-To:Mime-Version:References:Message-ID:Subject:From: To:Cc:Content-Type; b=si1WUeTTUzh7jGMxZOPh+yMFvYcHVfUUe6CU2TsSjIqPCykq3Gd20kjKWuIM73Q0AIIbrqzXYG2BxxDYpKd4osn6eR9raOaNNR/XRFr6xYlP10wqqW0TWaktoY4N0e6SABpJ2PkqbAde2tuinRL3Bx8VE1svGxRX3jAIXXqd7Sc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=google.com; spf=pass smtp.mailfrom=flex--seanjc.bounces.google.com; dkim=pass (2048-bit key) header.d=google.com header.i=@google.com header.b=B8/Ao4CL; arc=none smtp.client-ip=209.85.210.201 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=google.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=flex--seanjc.bounces.google.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=google.com header.i=@google.com header.b="B8/Ao4CL" Received: by mail-pf1-f201.google.com with SMTP id d2e1a72fcca58-7b8973c4608so6532125b3a.3 for ; Fri, 05 Dec 2025 16:17:49 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20230601; t=1764980269; x=1765585069; darn=vger.kernel.org; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:reply-to:from:to:cc:subject:date:message-id:reply-to; bh=OFskCraMCAt1o1jXv8Q2cmHJ2OyK2yl9CAVs1/Lc01w=; b=B8/Ao4CLt3v5ehswAKCi138a1UFTPaFDajyIeBCnDnRvrwbScEDrmkI3ak6+RJV8Lh 80CnXuTlh4+5ZYJAaOzdImSgsWqRLStxnCXMmS9A4xyxCOHWv1OS7jGT88ma0iBdA2Qd 8JHjKoEHDcVBhrkaiudwxY9pDLovmxCqLonDllOzEpmV8rL398ugIlcWfR0eI2CFgPrg mb8PI+1OB7DUAGtGHkCNDEVq9ShAcRgsptAk9IRKpIaq5dIEobHgHCX4Sr9/gYJe+6Bl EMf6R2NWAQ1BVrHZYD+91KuUrqSH8l+IFLgy28p+uQusD6FZGMs3MA1WWwQVVUw0CLdT rO/g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1764980269; x=1765585069; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:reply-to:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=OFskCraMCAt1o1jXv8Q2cmHJ2OyK2yl9CAVs1/Lc01w=; b=YoVGO2lPqsjBD6RtUVGXS2UfzrZkdGZuJLbC9o5ALOAkM389xedjrlGgYXoQCNG9SV n27Hwgk4oVnWYfYemlkDRFbOITVLJYvYyU+6Nqr8PLT74KTFBSEy8zb3LP9xH52tWC4r oqDnhXeeU1cR8EaJdBriaJAMwLiQqYka8IBp9N9L2xVxUbu6WROdIEKdO3i0ERvXoaH6 HtnuqIUcJzVHOF1raMH9ld3xHmhx0qY3xZ50+yWERBTXWqp4G4xboFeqPwxAIORCTR96 y8W7tKLdt89hFoPyO98sx9azHG8pWPOQm+Wczx3mrYo6efN+ixQyePZRvkjLgptCmJtu mQBg== X-Forwarded-Encrypted: i=1; AJvYcCV7ivpWUdlezrax19mnuAOkx4KJZ3isM3mfsLVBwyP1SSFy17CqsgH92XbcwJkRbhjjtCZFc2Y/Qae/vRA=@vger.kernel.org X-Gm-Message-State: AOJu0YzT+BB7Vk66z8DTCCJAB6a1Fb6QH23TwQcoe29uEoEgnNrmrFrp AiCzdfzCFTL0Ee2SDlm0EV0zPe1x8ZrvTOD9hTiSGqwtc+ZHTZetQWHrLDYU15nl1Qr+QPu/EtW OeZoacQ== X-Google-Smtp-Source: AGHT+IFfI+s5eY5Nrz61icCfCwYv8IGUZBRQf6oh7KDogWUJprIuAF6nUR9g3xDsrE/LDxUvXG6Y79XK/ls= X-Received: from pfuf34.prod.google.com ([2002:a05:6a00:b22:b0:781:26f4:7855]) (user=seanjc job=prod-delivery.src-stubby-dispatcher) by 2002:a05:6a00:234c:b0:7e8:450c:6195 with SMTP id d2e1a72fcca58-7e8c6dac143mr767576b3a.44.1764980268965; Fri, 05 Dec 2025 16:17:48 -0800 (PST) Reply-To: Sean Christopherson Date: Fri, 5 Dec 2025 16:16:47 -0800 In-Reply-To: <20251206001720.468579-1-seanjc@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20251206001720.468579-1-seanjc@google.com> X-Mailer: git-send-email 2.52.0.223.gf5cc29aaa4-goog Message-ID: <20251206001720.468579-12-seanjc@google.com> Subject: [PATCH v6 11/44] perf/x86/core: Plumb mediated PMU capability from x86_pmu to x86_pmu_cap From: Sean Christopherson To: Marc Zyngier , Oliver Upton , Tianrui Zhao , Bibo Mao , Huacai Chen , Anup Patel , Paul Walmsley , Palmer Dabbelt , Albert Ou , Xin Li , "H. Peter Anvin" , Andy Lutomirski , Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Sean Christopherson , Paolo Bonzini Cc: linux-arm-kernel@lists.infradead.org, kvmarm@lists.linux.dev, kvm@vger.kernel.org, loongarch@lists.linux.dev, kvm-riscv@lists.infradead.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, Mingwei Zhang , Xudong Hao , Sandipan Das , Dapeng Mi , Xiong Zhang , Manali Shukla , Jim Mattson Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Mingwei Zhang Plumb mediated PMU capability to x86_pmu_cap in order to let any kernel entity such as KVM know that host PMU support mediated PMU mode and has the implementation. Signed-off-by: Mingwei Zhang Tested-by: Xudong Hao Signed-off-by: Sean Christopherson --- arch/x86/events/core.c | 1 + arch/x86/include/asm/perf_event.h | 1 + 2 files changed, 2 insertions(+) diff --git a/arch/x86/events/core.c b/arch/x86/events/core.c index bd9abe298469..1b50f0117876 100644 --- a/arch/x86/events/core.c +++ b/arch/x86/events/core.c @@ -3137,6 +3137,7 @@ void perf_get_x86_pmu_capability(struct x86_pmu_capab= ility *cap) cap->events_mask =3D (unsigned int)x86_pmu.events_maskl; cap->events_mask_len =3D x86_pmu.events_mask_len; cap->pebs_ept =3D x86_pmu.pebs_ept; + cap->mediated =3D !!(pmu.capabilities & PERF_PMU_CAP_MEDIATED_VPMU); } EXPORT_SYMBOL_GPL(perf_get_x86_pmu_capability); =20 diff --git a/arch/x86/include/asm/perf_event.h b/arch/x86/include/asm/perf_= event.h index 4cd38b9da0ba..4714bdee17b2 100644 --- a/arch/x86/include/asm/perf_event.h +++ b/arch/x86/include/asm/perf_event.h @@ -296,6 +296,7 @@ struct x86_pmu_capability { unsigned int events_mask; int events_mask_len; unsigned int pebs_ept :1; + unsigned int mediated :1; }; =20 /* --=20 2.52.0.223.gf5cc29aaa4-goog