From nobody Tue Dec 16 14:42:45 2025 Received: from mail-pj1-f74.google.com (mail-pj1-f74.google.com [209.85.216.74]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 13DD42288E3 for ; Sat, 6 Dec 2025 00:17:46 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.216.74 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764980270; cv=none; b=JMGzBo8FzLmGl24xq0mI8Pt5/n5hQNViWBFQsZa4BnqXa9Dst5Max4FwJFxygtq6Bwa4AB+/L8n16WOUXst5UE+lDNSM2S06lchAl9GazoqMfjLUZ4cbAwneePBpRcW6YdcfDyGuBYJCQjSh8mfR3C+dh64DSHL5LYyWHw8RxwE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764980270; c=relaxed/simple; bh=gw4FQTHE8SLlwJArBri42euAjtNSeNQ1byjalYji5b0=; h=Date:In-Reply-To:Mime-Version:References:Message-ID:Subject:From: To:Cc:Content-Type; b=Os4LMI7I0qqLMkREj4d2qw8KgSWcU5g52ZGH7qV5QyPzWVrC1om6ecQMwstT7YZ8LJwZX+NoX1umiRqwSAF9ytIe3DeMDU6soDy2s4Sb+rZNjSSX+odD7FNsxS0XaPIaOWQzXO8aCQ+p5BW4GsG1vGA4fAC6qb2gIMOSQzFa4po= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=google.com; spf=pass smtp.mailfrom=flex--seanjc.bounces.google.com; dkim=pass (2048-bit key) header.d=google.com header.i=@google.com header.b=qReMFqf8; arc=none smtp.client-ip=209.85.216.74 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=google.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=flex--seanjc.bounces.google.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=google.com header.i=@google.com header.b="qReMFqf8" Received: by mail-pj1-f74.google.com with SMTP id 98e67ed59e1d1-341616a6fb7so2792745a91.0 for ; Fri, 05 Dec 2025 16:17:46 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20230601; t=1764980266; x=1765585066; darn=vger.kernel.org; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:reply-to:from:to:cc:subject:date:message-id:reply-to; bh=CUuCYzCJ+7mOkcgENgUcVnWD5HNM+Ecxc29Wc5gu0a8=; b=qReMFqf83LKwpbNApAv433CETZlXKi85nOvIXeqkLijljWe8SrlpKQMFuMS1K3eMHA uNE9OqI2jDoLxzkjvHJml8htJx4gz/O9hcVherDcQ+8yPpmIsJKmdg5EoMPtIQGjP/KG kLpXtVYDOvmbQBD1udIXAAwI1ShLBq4DIkhFqyTCOakJJeJwSMyhEEKOKN3YkB8ZOI0d ziTBj0XV+LrC6suGn09PLuYjPdqYLLZTEedKbImmIBsyLzP6qyE+kcW0p1+IOhzeo7EQ +UVsYVMGlVOsWl/Z7KsbvCiLl0+dWVMXaaNWXP1SHRKIDWW8OZZbXxV4qsz8jpVFTBHs le5w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1764980266; x=1765585066; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:reply-to:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=CUuCYzCJ+7mOkcgENgUcVnWD5HNM+Ecxc29Wc5gu0a8=; b=NZjiY9UY5e3Xk6yaalgu6Oniop1FVzk9iefmwvC0jQtihTwvIzsJgMJYbMT7tE3pCB C8z9UnB8D+V1jo7BNPKTs+dtQ3kDW0C81Drlxhlj6PTp6p+Ao4NGu0JOWnGClaERPz1t Q0hycD+d8HIWChVxLVsGjDlcHsrAvF10QBBNvblpQePCK4ZNG43lOEzQpF5z5ClnuLMj W0ee63rP3dri9gxdhq7JQVXY4whTLqXR2bTJf5mApKVO+wX73ezA5fsSEefH2Z/jPSey Dcb74LKkcvRzSXbSubECW1jZzndwyowpYDC1HDsDHjk1XW69C5547TH0MH7TXQA7klLK 8sTA== X-Forwarded-Encrypted: i=1; AJvYcCUDafO5kcNTRRVq238fdJvOg5l8wpUOQ47WnfqFs6mgpZdoU6Mz20FwL3O57Ug4u1gYWK0cBJnaremPXYA=@vger.kernel.org X-Gm-Message-State: AOJu0Yz5JqWoRzZQugfgSItN4JBP4ETUHoGCfjeQEUotPj8xxaYnmwrY tWEMs8hpAvTxyk1av6NaIHv1CLplPkV5qdBrUXS+s3qVPVnF+aGJCrpAvyrv3fHmqUeyeA7L76j XBgZiTA== X-Google-Smtp-Source: AGHT+IEudAc+RtrsthgQd29i5TzWwClBzh0orawUsXJ6SsndAr08K8DVgHn3KuIiiMIFAwisOcz2YNtd49Q= X-Received: from pjqx1.prod.google.com ([2002:a17:90a:b001:b0:33b:5907:81cb]) (user=seanjc job=prod-delivery.src-stubby-dispatcher) by 2002:a17:90b:1d92:b0:340:b572:3b7d with SMTP id 98e67ed59e1d1-349a25fb840mr628818a91.19.1764980265902; Fri, 05 Dec 2025 16:17:45 -0800 (PST) Reply-To: Sean Christopherson Date: Fri, 5 Dec 2025 16:16:46 -0800 In-Reply-To: <20251206001720.468579-1-seanjc@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20251206001720.468579-1-seanjc@google.com> X-Mailer: git-send-email 2.52.0.223.gf5cc29aaa4-goog Message-ID: <20251206001720.468579-11-seanjc@google.com> Subject: [PATCH v6 10/44] perf/x86/core: Do not set bit width for unavailable counters From: Sean Christopherson To: Marc Zyngier , Oliver Upton , Tianrui Zhao , Bibo Mao , Huacai Chen , Anup Patel , Paul Walmsley , Palmer Dabbelt , Albert Ou , Xin Li , "H. Peter Anvin" , Andy Lutomirski , Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Sean Christopherson , Paolo Bonzini Cc: linux-arm-kernel@lists.infradead.org, kvmarm@lists.linux.dev, kvm@vger.kernel.org, loongarch@lists.linux.dev, kvm-riscv@lists.infradead.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, Mingwei Zhang , Xudong Hao , Sandipan Das , Dapeng Mi , Xiong Zhang , Manali Shukla , Jim Mattson Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Sandipan Das Not all x86 processors have fixed counters. It may also be the case that a processor has only fixed counters and no general-purpose counters. Set the bit widths corresponding to each counter type only if such counters are available. Fixes: b3d9468a8bd2 ("perf, x86: Expose perf capability to other modules") Signed-off-by: Sandipan Das Co-developed-by: Dapeng Mi Signed-off-by: Dapeng Mi Signed-off-by: Mingwei Zhang Tested-by: Xudong Hao Signed-off-by: Sean Christopherson --- arch/x86/events/core.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/x86/events/core.c b/arch/x86/events/core.c index abe6a129a87f..bd9abe298469 100644 --- a/arch/x86/events/core.c +++ b/arch/x86/events/core.c @@ -3132,8 +3132,8 @@ void perf_get_x86_pmu_capability(struct x86_pmu_capab= ility *cap) cap->version =3D x86_pmu.version; cap->num_counters_gp =3D x86_pmu_num_counters(NULL); cap->num_counters_fixed =3D x86_pmu_num_counters_fixed(NULL); - cap->bit_width_gp =3D x86_pmu.cntval_bits; - cap->bit_width_fixed =3D x86_pmu.cntval_bits; + cap->bit_width_gp =3D cap->num_counters_gp ? x86_pmu.cntval_bits : 0; + cap->bit_width_fixed =3D cap->num_counters_fixed ? x86_pmu.cntval_bits : = 0; cap->events_mask =3D (unsigned int)x86_pmu.events_maskl; cap->events_mask_len =3D x86_pmu.events_mask_len; cap->pebs_ept =3D x86_pmu.pebs_ept; --=20 2.52.0.223.gf5cc29aaa4-goog