From nobody Tue Dec 16 14:52:16 2025 Received: from mail-pf1-f202.google.com (mail-pf1-f202.google.com [209.85.210.202]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2D4F82DF128 for ; Fri, 5 Dec 2025 23:19:28 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.210.202 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764976771; cv=none; b=dYd6Y8SXO2yVj7z7kH59aHQgaPn/bm4Fe/0NSMz2oWUwUF1S7smoZt8fEOrUihCUYOaFOj+Z8Du8M/5sn8WTf9ze5y1exEqwk4+yiRvOi0m6/5CJvCGokuBed0XhrGQ15uk+Vv4Z2QBVY0QosJXNpHe2b+PSdYGNePYaxyzNuq0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764976771; c=relaxed/simple; bh=Iz/PdNNvwiToa3bILkudY0rFq88iIR9xc2DDP4kGkh8=; h=Date:In-Reply-To:Mime-Version:References:Message-ID:Subject:From: To:Cc:Content-Type; b=kWIr9hesw3f8FGTmz3M5FQ5dRtDjFGZfFO6GTJPwx83om/uhAbUiQkV4qISrSgu5m4HaTyFFwRDeHwv3Ja8pjhRcy0MP1npkSeW4MayHJmcGlwIcooPArSh8YBTy5uos1/B9oPc6NhcSq2VrWIQI9AfGHOlOeepHKDeoCKN5yI0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=google.com; spf=pass smtp.mailfrom=flex--seanjc.bounces.google.com; dkim=pass (2048-bit key) header.d=google.com header.i=@google.com header.b=gE/QjKne; arc=none smtp.client-ip=209.85.210.202 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=google.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=flex--seanjc.bounces.google.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=google.com header.i=@google.com header.b="gE/QjKne" Received: by mail-pf1-f202.google.com with SMTP id d2e1a72fcca58-7b89c1ce9cfso2633871b3a.2 for ; Fri, 05 Dec 2025 15:19:28 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20230601; t=1764976766; x=1765581566; darn=vger.kernel.org; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:reply-to:from:to:cc:subject:date:message-id:reply-to; bh=uei+FBCp6XSbN3s6wo1y2mN6ct0eKDDXjuxrLY/MXh4=; b=gE/QjKneIbRRLyCDWr1jewAjR3v0jgFyPultOww+DNkb7JHyCGhqT6L0XiHi64AO8e LOSfC0Oez+p6i/xUMOPDcj4s1zOTQf44Pl7oZuI78jQ7r4ymaCOyJMTiaOv9eNelo8ik 8ym3/jR/zRc3/2tC2V13s0ckUcDxtGrr/rkys6z/0Vrfbq17lWlqwaU4pQZ82wgpk5GR TL5VcIwujuXw2xTz/J97lS0XC6TmijWRwSpFSLXf7KcuasbzbQs3DcU/NrwVQ8bu5icx F5IO11Whe2CkgQGOY5z+Kjz5HWjDYuA6T48SoSAc0x1F46yrHhDpfLAZtmNc+YKnHPkD dRqA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1764976766; x=1765581566; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:reply-to:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=uei+FBCp6XSbN3s6wo1y2mN6ct0eKDDXjuxrLY/MXh4=; b=sgEcM96vg2Bkrpj00HPMF/ZoxvDl+RBQz3QWwXOoi6CJr4mVnQCnNREkxoI+jN3z+r kwqNIO6UVeT9prphKoxXTQUSvYfBJv5EHmOQlkkEo5iSQGbzD2MzeSm/BlDr0ZCQS2Ez wgyVyI01wtRCOLDQI4OviTyfS3OVZOsObzLpGg02kkBJDPnzK3Oi7NLDthvFyCbX45gM pwm9tS7nO0syhMiL05Y/3tLpwUhqKHPXFmgyHTsktG+1u6/tpSO+7K5QiAoc5pGIYy1l ZiL3V9JeAPCBvtbxMo/Q8SaHUfpAK9kLaqG1sODRis2dmI3Z+HdvlrNjM8DCkW5OMf34 QQLg== X-Forwarded-Encrypted: i=1; AJvYcCU/y+cxJ1TZC74Xb5lKSscfGmqb5X23lFVpCjB4LAA12eYmkTBaE/tTpx1Jdl8U1u+vPhZwB5RZcwbtGJ4=@vger.kernel.org X-Gm-Message-State: AOJu0YyL14Iwg7au6Hujh60ehBIadUsnNzH31whL7xm87xXAwpKFTYVP fxQN0bkbh5OTGuvM1yBM+Mmm30qqbB6qCrewMJmsAKlkdievNS4v19bgOv4MulbMwhfb58NJ6st LvfJCqg== X-Google-Smtp-Source: AGHT+IHvwjR/m6NdvCSTi9F88Nx4U6tu2ksUiv6cW14/aypzQz62E6H2QrvIw9QHUoJfvHKc1gUxiy78M6M= X-Received: from pfbfa36.prod.google.com ([2002:a05:6a00:2d24:b0:7dd:8bba:63a2]) (user=seanjc job=prod-delivery.src-stubby-dispatcher) by 2002:a05:6a00:1ace:b0:7b6:ebcb:51eb with SMTP id d2e1a72fcca58-7e8c02094c9mr708360b3a.17.1764976766283; Fri, 05 Dec 2025 15:19:26 -0800 (PST) Reply-To: Sean Christopherson Date: Fri, 5 Dec 2025 15:19:08 -0800 In-Reply-To: <20251205231913.441872-1-seanjc@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20251205231913.441872-1-seanjc@google.com> X-Mailer: git-send-email 2.52.0.223.gf5cc29aaa4-goog Message-ID: <20251205231913.441872-6-seanjc@google.com> Subject: [PATCH v3 05/10] KVM: nVMX: Switch to vmcs01 to update TPR threshold on-demand if L2 is active From: Sean Christopherson To: Sean Christopherson , Paolo Bonzini Cc: kvm@vger.kernel.org, linux-kernel@vger.kernel.org, Dongli Zhang , Chao Gao Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" If KVM updates L1's TPR Threshold while L2 is active, temporarily load vmcs01 and immediately update TPR_THRESHOLD instead of deferring the update until the next nested VM-Exit. Deferring the TPR Threshold update is relatively straightforward, but for several APICv related updates, deferring updates creates ordering and state consistency problems, e.g. KVM at-large thinks APICv is enabled, but vmcs01 is still running with stale (and effectively unknown) state. Signed-off-by: Sean Christopherson --- arch/x86/kvm/vmx/nested.c | 4 ---- arch/x86/kvm/vmx/vmx.c | 7 +++---- arch/x86/kvm/vmx/vmx.h | 3 --- 3 files changed, 3 insertions(+), 11 deletions(-) diff --git a/arch/x86/kvm/vmx/nested.c b/arch/x86/kvm/vmx/nested.c index 920a925bb46f..8efab1cf833f 100644 --- a/arch/x86/kvm/vmx/nested.c +++ b/arch/x86/kvm/vmx/nested.c @@ -2402,7 +2402,6 @@ static void prepare_vmcs02_early(struct vcpu_vmx *vmx= , struct loaded_vmcs *vmcs0 exec_control &=3D ~CPU_BASED_TPR_SHADOW; exec_control |=3D vmcs12->cpu_based_vm_exec_control; =20 - vmx->nested.l1_tpr_threshold =3D -1; if (exec_control & CPU_BASED_TPR_SHADOW) vmcs_write32(TPR_THRESHOLD, vmcs12->tpr_threshold); #ifdef CONFIG_X86_64 @@ -5144,9 +5143,6 @@ void __nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 v= m_exit_reason, if (kvm_caps.has_tsc_control) vmcs_write64(TSC_MULTIPLIER, vcpu->arch.tsc_scaling_ratio); =20 - if (vmx->nested.l1_tpr_threshold !=3D -1) - vmcs_write32(TPR_THRESHOLD, vmx->nested.l1_tpr_threshold); - if (vmx->nested.change_vmcs01_virtual_apic_mode) { vmx->nested.change_vmcs01_virtual_apic_mode =3D false; vmx_set_virtual_apic_mode(vcpu); diff --git a/arch/x86/kvm/vmx/vmx.c b/arch/x86/kvm/vmx/vmx.c index 1420665fbb66..3ee86665d8de 100644 --- a/arch/x86/kvm/vmx/vmx.c +++ b/arch/x86/kvm/vmx/vmx.c @@ -6827,11 +6827,10 @@ void vmx_update_cr8_intercept(struct kvm_vcpu *vcpu= , int tpr, int irr) nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW)) return; =20 + guard(vmx_vmcs01)(vcpu); + tpr_threshold =3D (irr =3D=3D -1 || tpr < irr) ? 0 : irr; - if (is_guest_mode(vcpu)) - to_vmx(vcpu)->nested.l1_tpr_threshold =3D tpr_threshold; - else - vmcs_write32(TPR_THRESHOLD, tpr_threshold); + vmcs_write32(TPR_THRESHOLD, tpr_threshold); } =20 void vmx_set_virtual_apic_mode(struct kvm_vcpu *vcpu) diff --git a/arch/x86/kvm/vmx/vmx.h b/arch/x86/kvm/vmx/vmx.h index b44eda6225f4..36f48c4b39c0 100644 --- a/arch/x86/kvm/vmx/vmx.h +++ b/arch/x86/kvm/vmx/vmx.h @@ -184,9 +184,6 @@ struct nested_vmx { u64 pre_vmenter_ssp; u64 pre_vmenter_ssp_tbl; =20 - /* to migrate it to L1 if L2 writes to L1's CR8 directly */ - int l1_tpr_threshold; - u16 vpid02; u16 last_vpid; =20 --=20 2.52.0.223.gf5cc29aaa4-goog