From nobody Tue Dec 16 15:08:43 2025 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 607C92D9493 for ; Fri, 5 Dec 2025 21:59:49 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764971992; cv=none; b=a6xyR+EP2dTdpFz87h7c9x4vQXRh3raDCb3peJoiSzHmQf0vSFXM8Z+LcipuFa+QwC0xjcqzF5j9t8wCW9kfUY5KgoVjPivaT/NOEsuXgtvlWkgJNKk9hXl9OB3YzRVDG8CPHYgTVjRynRi/F/kiRGmqjlIrSFsqQBg4cIxcNTI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764971992; c=relaxed/simple; bh=cSus2geGI3l9W46KiKllHlUOTMbq0pgEOL6GvtLBw+A=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=b+AiyGth7RrgMPh3lHFxaRLqC01LqOxiiL3l6IpljpwyS70eEyD9q3KHEbDtD9ExNR7MwHBNgusiUsExR8mZHhLA11PqxxzF9UzixRJ1cl2mrv2BIa8hudgCLW9uelWLX+IRH8wGe33NU8QWDo6y7mjxaq5h9uM9Ot2FCp2gYMI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 25C8A1AC1; Fri, 5 Dec 2025 13:59:41 -0800 (PST) Received: from merodach.members.linode.com (usa-sjc-mx-foss1.foss.arm.com [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 979FB3F740; Fri, 5 Dec 2025 13:59:44 -0800 (PST) From: James Morse To: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: James Morse , D Scott Phillips OS , carl@os.amperecomputing.com, lcherian@marvell.com, bobo.shaobowang@huawei.com, tan.shaopeng@fujitsu.com, baolin.wang@linux.alibaba.com, Jamie Iles , Xin Hao , peternewman@google.com, dfustini@baylibre.com, amitsinght@marvell.com, David Hildenbrand , Dave Martin , Koba Ko , Shanker Donthineni , fenghuay@nvidia.com, baisheng.gao@unisoc.com, Jonathan Cameron , Gavin Shan , Ben Horgan , rohit.mathew@arm.com, reinette.chatre@intel.com, Punit Agrawal , Dave Martin Subject: [RFC PATCH 05/38] arm64: mpam: Add helpers to change a task or cpu's MPAM PARTID/PMG values Date: Fri, 5 Dec 2025 21:58:28 +0000 Message-Id: <20251205215901.17772-6-james.morse@arm.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20251205215901.17772-1-james.morse@arm.com> References: <20251205215901.17772-1-james.morse@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Care must be taken when modifying the PARTID and PMG of a task in any per-task structure as writing these values may race with the task being scheduled in, and reading the modified values. Add helpers to set the task properties, and the CPU default value. These use WRITE_ONCE() that pairs with the READ_ONCE() in mpam_get_regval() to avoid causing torn values. CC: Dave Martin CC: Ben Horgan Signed-off-by: James Morse --- arch/arm64/include/asm/mpam.h | 30 ++++++++++++++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/arch/arm64/include/asm/mpam.h b/arch/arm64/include/asm/mpam.h index 86a55176f884..2960ffaf6574 100644 --- a/arch/arm64/include/asm/mpam.h +++ b/arch/arm64/include/asm/mpam.h @@ -5,6 +5,7 @@ #define __ASM__MPAM_H =20 #include +#include #include #include #include @@ -37,6 +38,35 @@ extern u64 arm64_mpam_global_default; * A value in struct thread_info is used instead of struct task_struct as = the * cpu's u64 register format is used, but struct task_struct has two u32'. */ +static inline void mpam_set_cpu_defaults(int cpu, u16 partid_d, u16 partid= _i, + u8 pmg_d, u8 pmg_i) +{ + u64 default_val; + + default_val =3D FIELD_PREP(MPAM0_EL1_PARTID_D, partid_d); + default_val |=3D FIELD_PREP(MPAM0_EL1_PARTID_I, partid_i); + default_val |=3D FIELD_PREP(MPAM0_EL1_PMG_D, pmg_d); + default_val |=3D FIELD_PREP(MPAM0_EL1_PMG_I, pmg_i); + + WRITE_ONCE(per_cpu(arm64_mpam_default, cpu), default_val); +} + +static inline void mpam_set_task_partid_pmg(struct task_struct *tsk, + u16 partid_d, u16 partid_i, + u8 pmg_d, u8 pmg_i) +{ +#ifdef CONFIG_ARM64_MPAM + u64 regval; + + regval =3D FIELD_PREP(MPAM0_EL1_PARTID_D, partid_d); + regval |=3D FIELD_PREP(MPAM0_EL1_PARTID_I, partid_i); + regval |=3D FIELD_PREP(MPAM0_EL1_PMG_D, pmg_d); + regval |=3D FIELD_PREP(MPAM0_EL1_PMG_I, pmg_i); + + WRITE_ONCE(task_thread_info(tsk)->mpam_partid_pmg, regval); +#endif +} + static inline u64 mpam_get_regval(struct task_struct *tsk) { #ifdef CONFIG_ARM64_MPAM --=20 2.39.5