From nobody Tue Dec 16 14:50:58 2025 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 36D0D30C600 for ; Fri, 5 Dec 2025 22:01:55 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764972116; cv=none; b=OONsh7/pVpfs/DtURiukKNuBsfoh4q96oXR8X5QDZdG79njvgtcjOqmHlRluIVj35MiZpWE4YndZPCkqur+a2y36RaJNJdc6jtQg0tIPd6H6YB+5XeUFu1c9HlYmBtaon6ASTtIhv9HWLunjRp1eITq0M4PllhYqe21qBtcwBYQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764972116; c=relaxed/simple; bh=JDi7JVCrq9PMyvQ/D650zdseEpNkQwbZtvfeqNix8XU=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=vDv2gydm2ipRLvlxKO9D34LFZ7c9wnF5G/PYapJXqGeCUVTKGuF6kMGpcUBCpVh1ot3e/Kmbb9v4m0OLu9rcfN/LlA3MLe6XbnKWdWxnFGwaGcX6JoXpRmbPol+Rs0UhR4Y77isSpuhMeOKJDFj7tT3Uef2Qo9rJ5ZaDu6DdJCI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 657E41C00; Fri, 5 Dec 2025 14:01:47 -0800 (PST) Received: from merodach.members.linode.com (usa-sjc-mx-foss1.foss.arm.com [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id E5F883F740; Fri, 5 Dec 2025 14:01:50 -0800 (PST) From: James Morse To: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: James Morse , D Scott Phillips OS , carl@os.amperecomputing.com, lcherian@marvell.com, bobo.shaobowang@huawei.com, tan.shaopeng@fujitsu.com, baolin.wang@linux.alibaba.com, Jamie Iles , Xin Hao , peternewman@google.com, dfustini@baylibre.com, amitsinght@marvell.com, David Hildenbrand , Dave Martin , Koba Ko , Shanker Donthineni , fenghuay@nvidia.com, baisheng.gao@unisoc.com, Jonathan Cameron , Gavin Shan , Ben Horgan , rohit.mathew@arm.com, reinette.chatre@intel.com, Punit Agrawal Subject: [RFC PATCH 36/38] arm_mpam: Add workaround for T241-MPAM-4 Date: Fri, 5 Dec 2025 21:58:59 +0000 Message-Id: <20251205215901.17772-37-james.morse@arm.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20251205215901.17772-1-james.morse@arm.com> References: <20251205215901.17772-1-james.morse@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Shanker Donthineni In the T241 implementation of memory-bandwidth partitioning, in the absence of contention for bandwidth, the minimum bandwidth setting can affect the amount of achieved bandwidth. Specifically, the achieved bandwidth in the absence of contention can settle to any value between the values of MPAMCFG_MBW_MIN and MPAMCFG_MBW_MAX. Also, if MPAMCFG_MBW_MIN is set zero (below 0.78125%), once a core enters a throttled state, it will never leave that state. The first issue is not a cocern if the MPAM software allows to program MPAMCFG_MBW_MIN through the sysfs interface. This patch ensures program MBW_MIN=3D1 (0.78125%) whenever MPAMCFG_MBW_MIN=3D0 is programmed. In the scenario where the resctrl doesn't support the MBW_MIN interface via sysfs, to achieve bandwidth closer to MW_MAX in the absence of contention, software should configure a relatively narrow gap between MBW_MIN and MBW_MAX. The recommendation is to use a 5% gap to mitigate the problem. Signed-off-by: Shanker Donthineni [ morse: Added as second quirk, adapted to use the new intermediate values in mpam_extend_config() ] Signed-off-by: James Morse --- Documentation/arch/arm64/silicon-errata.rst | 2 + drivers/resctrl/mpam_devices.c | 60 ++++++++++++++++----- drivers/resctrl/mpam_internal.h | 1 + 3 files changed, 49 insertions(+), 14 deletions(-) diff --git a/Documentation/arch/arm64/silicon-errata.rst b/Documentation/ar= ch/arm64/silicon-errata.rst index 4e86b85fe3d6..b18bc704d4a1 100644 --- a/Documentation/arch/arm64/silicon-errata.rst +++ b/Documentation/arch/arm64/silicon-errata.rst @@ -248,6 +248,8 @@ stable kernels. +----------------+-----------------+-----------------+--------------------= ---------+ | NVIDIA | T241 MPAM | T241-MPAM-1 | N/A = | +----------------+-----------------+-----------------+--------------------= ---------+ +| NVIDIA | T241 MPAM | T241-MPAM-4 | N/A = | ++----------------+-----------------+-----------------+--------------------= ---------+ +----------------+-----------------+-----------------+--------------------= ---------+ | Freescale/NXP | LS2080A/LS1043A | A-008585 | FSL_ERRATUM_A008585= | +----------------+-----------------+-----------------+--------------------= ---------+ diff --git a/drivers/resctrl/mpam_devices.c b/drivers/resctrl/mpam_devices.c index f1f03ceade0a..5ba0aa703807 100644 --- a/drivers/resctrl/mpam_devices.c +++ b/drivers/resctrl/mpam_devices.c @@ -678,6 +678,12 @@ static const struct mpam_quirk mpam_quirks[] =3D { .iidr_mask =3D MPAM_IIDR_MATCH_ONE, .workaround =3D T241_SCRUB_SHADOW_REGS, }, + { + /* NVIDIA t241 erratum T241-MPAM-4 */ + .iidr =3D MPAM_IIDR_NVIDIA_T421, + .iidr_mask =3D MPAM_IIDR_MATCH_ONE, + .workaround =3D T241_FORCE_MBW_MIN_TO_ONE, + }, { NULL }, /* Sentinel */ }; =20 @@ -1622,6 +1628,22 @@ static void mpam_init_reset_cfg(struct mpam_config *= reset_cfg) bitmap_fill(reset_cfg->features, MPAM_FEATURE_LAST); } =20 +/* + * This is not part of mpam_init_reset_cfg() as high level callers have the + * class, and low level callers a ris. + */ +static void mpam_wa_t241_force_mbw_min_to_one(struct mpam_config *cfg, + struct mpam_props *props) +{ + u16 max_hw_value, min_hw_granule, res0_bits; + + res0_bits =3D 16 - props->bwa_wd; + max_hw_value =3D ((1 << props->bwa_wd) - 1) << res0_bits; + min_hw_granule =3D ~max_hw_value; + + cfg->mbw_min =3D min_hw_granule + 1; +} + /* * Called via smp_call_on_cpu() to prevent migration, while still being * pre-emptible. Caller must hold mpam_srcu. @@ -2524,7 +2546,8 @@ static void __destroy_component_cfg(struct mpam_compo= nent *comp) static void mpam_reset_component_cfg(struct mpam_component *comp) { int i; - struct mpam_props *cprops =3D &comp->class->props; + struct mpam_class *class =3D comp->class; + struct mpam_props *cprops =3D &class->props; =20 mpam_assert_partid_sizes_fixed(); =20 @@ -2539,6 +2562,10 @@ static void mpam_reset_component_cfg(struct mpam_com= ponent *comp) comp->cfg[i].mbw_pbm =3D GENMASK(cprops->mbw_pbm_bits - 1, 0); if (cprops->bwa_wd) comp->cfg[i].mbw_max =3D GENMASK(15, 16 - cprops->bwa_wd); + + if (mpam_has_quirk(T241_FORCE_MBW_MIN_TO_ONE, class)) + mpam_wa_t241_force_mbw_min_to_one(&comp->cfg[i], + &class->props); } } =20 @@ -2825,6 +2852,18 @@ static void mpam_extend_config(struct mpam_class *cl= ass, struct mpam_config *cfg u16 min, min_hw_granule, delta; u16 max_hw_value, res0_bits; =20 + /* + * Calculate the values the 'min' control can hold. + * e.g. on a platform with bwa_wd =3D 8, min_hw_granule is 0x00ff because + * those bits are RES0. Configurations of this value are effectively + * zero. But configurations need to saturate at min_hw_granule on + * systems with mismatched bwa_wd, where the 'less than 0' values are + * implemented on some MSC, but not others. + */ + res0_bits =3D 16 - cprops->bwa_wd; + max_hw_value =3D ((1 << cprops->bwa_wd) - 1) << res0_bits; + min_hw_granule =3D ~max_hw_value; + /* * MAX and MIN should be set together. If only one is provided, * generate a configuration for the other. If only one control @@ -2834,19 +2873,6 @@ static void mpam_extend_config(struct mpam_class *cl= ass, struct mpam_config *cfg */ if (mpam_has_feature(mpam_feat_mbw_max, cfg) && !mpam_has_feature(mpam_feat_mbw_min, cfg)) { - /* - * Calculate the values the 'min' control can hold. - * e.g. on a platform with bwa_wd =3D 8, min_hw_granule is 0x00ff - * because those bits are RES0. Configurations of this value - * are effectively zero. But configurations need to saturate - * at min_hw_granule on systems with mismatched bwa_wd, where - * the 'less than 0' values are implemented on some MSC, but - * not others. - */ - res0_bits =3D 16 - cprops->bwa_wd; - max_hw_value =3D ((1 << cprops->bwa_wd) - 1) << res0_bits; - min_hw_granule =3D ~max_hw_value; - delta =3D ((5 * MPAMCFG_MBW_MAX_MAX) / 100) - 1; if (cfg->mbw_max > delta) min =3D cfg->mbw_max - delta; @@ -2856,6 +2882,12 @@ static void mpam_extend_config(struct mpam_class *cl= ass, struct mpam_config *cfg cfg->mbw_min =3D max(min, min_hw_granule); mpam_set_feature(mpam_feat_mbw_min, cfg); } + + if (mpam_has_quirk(T241_FORCE_MBW_MIN_TO_ONE, class) && + cfg->mbw_min <=3D min_hw_granule) { + cfg->mbw_min =3D min_hw_granule + 1; + mpam_set_feature(mpam_feat_mbw_min, cfg); + } } =20 int mpam_apply_config(struct mpam_component *comp, u16 partid, diff --git a/drivers/resctrl/mpam_internal.h b/drivers/resctrl/mpam_interna= l.h index 70b78cfd1f5b..01882f0acee2 100644 --- a/drivers/resctrl/mpam_internal.h +++ b/drivers/resctrl/mpam_internal.h @@ -223,6 +223,7 @@ struct mpam_props { /* Workaround bits for msc->quirks */ enum mpam_device_quirks { T241_SCRUB_SHADOW_REGS, + T241_FORCE_MBW_MIN_TO_ONE, MPAM_QUIRK_LAST, }; =20 --=20 2.39.5