From nobody Tue Dec 16 15:08:43 2025 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id E4CDC30216F for ; Fri, 5 Dec 2025 22:01:34 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764972096; cv=none; b=kDTAfCgUHS24iCHIpjskBfWMbIdv0dsx2Pae9L2Rm2ZcHMVcw3xBY0bhRaSqVbh11iMm74WeKNQR4StvJpUvh4bH2kks/8BRxrpy3uy4A71D5JKit49ieRFRu+Bixy/7PFMC+J83bF1FGS1MbL6nwMWTVidgLrQwBFPt3QB6AnU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764972096; c=relaxed/simple; bh=xjzk++ZulNUTQLYX4eWh7FZoXHE1Rz67GIoSsPqQBK8=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=cGb6Kg83rImoQxbzrfHhXDiGWgTGxlQgqLjq/m7dNQz612dEy0luHr+vhK5HY1/7MsuInvDKOt7w4gV6XUGpmVZclbwGiAwC250m8q2+B8QShfaex9vBoMSZjEfZ5DnRyHPGzvSkYBHBKQqlpM21oIg4sh18vAO3HJKONj57Xq8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=fail (p=none dis=none) header.from=arm.com; spf=fail smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=fail (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 11AA31AED; Fri, 5 Dec 2025 14:01:27 -0800 (PST) Received: from merodach.members.linode.com (usa-sjc-mx-foss1.foss.arm.com [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 925E53F740; Fri, 5 Dec 2025 14:01:30 -0800 (PST) From: James Morse To: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: James Morse , D Scott Phillips OS , carl@os.amperecomputing.com, lcherian@marvell.com, bobo.shaobowang@huawei.com, tan.shaopeng@fujitsu.com, baolin.wang@linux.alibaba.com, Jamie Iles , Xin Hao , peternewman@google.com, dfustini@baylibre.com, amitsinght@marvell.com, David Hildenbrand , Dave Martin , Koba Ko , Shanker Donthineni , fenghuay@nvidia.com, baisheng.gao@unisoc.com, Jonathan Cameron , Gavin Shan , Ben Horgan , rohit.mathew@arm.com, reinette.chatre@intel.com, Punit Agrawal Subject: [RFC PATCH 31/38] arm_mpam: resctrl: Update the rmid reallocation limit Date: Fri, 5 Dec 2025 21:58:54 +0000 Message-Id: <20251205215901.17772-32-james.morse@arm.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20251205215901.17772-1-james.morse@arm.com> References: <20251205215901.17772-1-james.morse@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" resctrl's limbo code needs to be told when the data left in a cache is small enough for the partid+pmg value to be re-allocated. x86 uses the cache size divided by the number of rmid users the cache may have. Do the same, but for the smallest cache, and with the number of partid-and-pmg users. Querying the cache size can't happen until after cacheinfo_sysfs_init() has run, so mpam_resctrl_setup() must wait until then. Signed-off-by: James Morse --- drivers/resctrl/mpam_resctrl.c | 54 ++++++++++++++++++++++++++++++++++ 1 file changed, 54 insertions(+) diff --git a/drivers/resctrl/mpam_resctrl.c b/drivers/resctrl/mpam_resctrl.c index 506063bd3348..ccdf8db742c9 100644 --- a/drivers/resctrl/mpam_resctrl.c +++ b/drivers/resctrl/mpam_resctrl.c @@ -16,6 +16,7 @@ #include #include #include +#include =20 #include =20 @@ -58,6 +59,13 @@ static bool cdp_enabled; */ static bool resctrl_enabled; =20 +/* + * mpam_resctrl_pick_caches() needs to know the size of the caches. cachei= nfo + * populates this from a device_initcall(). mpam_resctrl_setup() must wait. + */ +static bool cacheinfo_ready; +static DECLARE_WAIT_QUEUE_HEAD(wait_cacheinfo_ready); + /* * L3 local/total may come from different classes - what is the number of = MBWU * 'on L3'? @@ -584,6 +592,38 @@ void resctrl_arch_reset_cntr(struct rdt_resource *r, s= truct rdt_mon_domain *d, reset_mon_cdp_safe(mon, mon_comp, USE_PRE_ALLOCATED, closid, rmid); } =20 +/* + * The rmid realloc threshold should be for the smallest cache exposed to + * resctrl. + */ +static int update_rmid_limits(struct mpam_class *class) +{ + u32 num_unique_pmg =3D resctrl_arch_system_num_rmid_idx(); + struct mpam_props *cprops =3D &class->props; + struct cacheinfo *ci; + + lockdep_assert_cpus_held(); + + /* Assume cache levels are the same size for all CPUs... */ + ci =3D get_cpu_cacheinfo_level(smp_processor_id(), class->level); + if (!ci || ci->size =3D=3D 0) { + pr_debug("Could not read cache size for class %u\n", + class->level); + return -EINVAL; + } + + if (!mpam_has_feature(mpam_feat_msmon_csu, cprops)) + return 0; + + if (!resctrl_rmid_realloc_limit || + ci->size < resctrl_rmid_realloc_limit) { + resctrl_rmid_realloc_limit =3D ci->size; + resctrl_rmid_realloc_threshold =3D ci->size / num_unique_pmg; + } + + return 0; +} + static bool cache_has_usable_cpor(struct mpam_class *class) { struct mpam_props *cprops =3D &class->props; @@ -1025,6 +1065,9 @@ static void mpam_resctrl_pick_counters(void) /* CSU counters only make sense on a cache. */ switch (class->type) { case MPAM_CLASS_CACHE: + if (update_rmid_limits(class)) + continue; + counter_update_class(QOS_L3_OCCUP_EVENT_ID, class); return; default: @@ -1731,6 +1774,8 @@ int mpam_resctrl_setup(void) struct mpam_resctrl_res *res; struct mpam_resctrl_mon *mon; =20 + wait_event(wait_cacheinfo_ready, cacheinfo_ready); + cpus_read_lock(); for (i =3D 0; i < RDT_NUM_RESOURCES; i++) { res =3D &mpam_resctrl_controls[i]; @@ -1854,6 +1899,15 @@ void mpam_resctrl_teardown_class(struct mpam_class *= class) } } =20 +static int __init __cacheinfo_ready(void) +{ + cacheinfo_ready =3D true; + wake_up(&wait_cacheinfo_ready); + + return 0; +} +device_initcall_sync(__cacheinfo_ready); + #ifdef CONFIG_MPAM_KUNIT_TEST #include "test_mpam_resctrl.c" #endif --=20 2.39.5