From nobody Tue Dec 16 07:34:20 2025 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 945E32868AD for ; Fri, 5 Dec 2025 21:59:33 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764971976; cv=none; b=KqCn5520EfPZSnGaukYz0mZW/7UP/0Ow6GSKv+n8WY5S8b6iSfiyaUV8VknUqrR0TvcKwjPJsO5RAnlSXM6qU0g4S3mTKxndguV81j+24WkS0zGZ4uXcvMx8S8HwsLTYiata6rdEtgKNpLlkiyfRWw8tvKOkX2gpz6u6j+zOM3s= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764971976; c=relaxed/simple; bh=hvxD2wMl42JfwqnHFT1fFkOJudfzDX+5S3CjvQNq6MM=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=PPOYdcoH5B+XGMypTvg0wH5Cog3IfRBM/WNLT3GjpCv3Yh5pzWH5q5tssU8BZ3n8v58xzEfPmWwOFaIva63zU9gRRi62+F83fYmOOPCbw5CijdnDKR1qcYxaVrZiOdRpVj1G8TvmCM0tSz7xA1oHwWUe4xLU/vytufYCO6h/q1E= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 00D401A00; Fri, 5 Dec 2025 13:59:25 -0800 (PST) Received: from merodach.members.linode.com (usa-sjc-mx-foss1.foss.arm.com [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 517D23F740; Fri, 5 Dec 2025 13:59:28 -0800 (PST) From: James Morse To: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: James Morse , D Scott Phillips OS , carl@os.amperecomputing.com, lcherian@marvell.com, bobo.shaobowang@huawei.com, tan.shaopeng@fujitsu.com, baolin.wang@linux.alibaba.com, Jamie Iles , Xin Hao , peternewman@google.com, dfustini@baylibre.com, amitsinght@marvell.com, David Hildenbrand , Dave Martin , Koba Ko , Shanker Donthineni , fenghuay@nvidia.com, baisheng.gao@unisoc.com, Jonathan Cameron , Gavin Shan , Ben Horgan , rohit.mathew@arm.com, reinette.chatre@intel.com, Punit Agrawal Subject: [RFC PATCH 01/38] arm64: mpam: Context switch the MPAM registers Date: Fri, 5 Dec 2025 21:58:24 +0000 Message-Id: <20251205215901.17772-2-james.morse@arm.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20251205215901.17772-1-james.morse@arm.com> References: <20251205215901.17772-1-james.morse@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" MPAM allows traffic in the SoC to be labeled by the OS, these labels are used to apply policy in caches and bandwidth regulators, and to monitor traffic in the SoC. The label is made up of a PARTID and PMG value. The x86 equivalent calls these CLOSID and RMID, but they don't map precisely. MPAM has two CPU system registers that is used to hold the PARTID and PMG values that traffic generated at each exception level will use. These can be set per-task by the resctrl file system. (resctrl is the defacto interface for controlling this stuff). Add a helper to switch this. struct task_struct's separate CLOSID and RMID fields are insufficient to implement resctrl using MPAM, as resctrl can change the PARTID (CLOSID) and PMG (sort of like the RMID) separately. On x86, the rmid is an independent number, so a race that writes a mismatched closid and rmid into hardware is benign. On arm64, the pmg bits extend the partid. (i.e. partid-5 has a pmg-0 that is not the same as partid-6's pmg-0). In this case, mismatching the values will 'dirty' a pmg value that resctrl believes is clean, and is not tracking with its 'limbo' code. To avoid this, the partid and pmg are always read and written as a pair. Instead of making struct task_struct's closid and rmid fields an endian-unsafe union, add the value to struct thread_info and always use READ_ONCE()/WRITE_ONCE() when accessing this field. Resctrl allows a per-cpu 'default' value to be set, this overrides the values when scheduling a task in the default control-group, which has PARTID 0. The way 'code data prioritisation' gets emulated means the register value for the default group needs to be a variable. The current system register value is kept in a per-cpu variable to avoid writing to the system register if the value isn't going to change. Writes to this register may reset the hardware state for regulating bandwidth. Finally, there is no reason to context switch these registers unless there is a driver changing the values in struct task_struct. Hide the whole thing behind a static key. This also allows the driver to disable MPAM in response to errors reported by hardware. Move the existing static key to belong to the arch code, as in the future the MPAM driver may become a loadable module. All this should depend on whether there is an MPAM driver, hide it behind CONFIG_MPAM. CC: Amit Singh Tomar Signed-off-by: James Morse --- arch/arm64/Kconfig | 2 + arch/arm64/include/asm/mpam.h | 74 ++++++++++++++++++++++++++++ arch/arm64/include/asm/thread_info.h | 3 ++ arch/arm64/kernel/Makefile | 1 + arch/arm64/kernel/mpam.c | 13 +++++ arch/arm64/kernel/process.c | 7 +++ drivers/resctrl/mpam_devices.c | 2 - drivers/resctrl/mpam_internal.h | 2 + 8 files changed, 102 insertions(+), 2 deletions(-) create mode 100644 arch/arm64/include/asm/mpam.h create mode 100644 arch/arm64/kernel/mpam.c diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig index 004d58cfbff8..558baa9e7c08 100644 --- a/arch/arm64/Kconfig +++ b/arch/arm64/Kconfig @@ -2048,6 +2048,8 @@ config ARM64_MPAM =20 MPAM is exposed to user-space via the resctrl pseudo filesystem. =20 + This option enables the extra context switch code. + endmenu # "ARMv8.4 architectural features" =20 menu "ARMv8.5 architectural features" diff --git a/arch/arm64/include/asm/mpam.h b/arch/arm64/include/asm/mpam.h new file mode 100644 index 000000000000..86a55176f884 --- /dev/null +++ b/arch/arm64/include/asm/mpam.h @@ -0,0 +1,74 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* Copyright (C) 2025 Arm Ltd. */ + +#ifndef __ASM__MPAM_H +#define __ASM__MPAM_H + +#include +#include +#include +#include +#include + +#include +#include +#include + +DECLARE_STATIC_KEY_FALSE(mpam_enabled); +DECLARE_PER_CPU(u64, arm64_mpam_default); +DECLARE_PER_CPU(u64, arm64_mpam_current); + +/* + * The value of the MPAM0_EL1 sysreg when a task is in resctrl's default g= roup. + * This is used by the context switch code to use the resctrl CPU property + * instead. The value is modified when CDP is enabled/disabled by mounting + * the resctrl filesystem. + */ +extern u64 arm64_mpam_global_default; + +/* + * The resctrl filesystem writes to the partid/pmg values for threads and = CPUs, + * which may race with reads in __mpam_sched_in(). Ensure only one of the = old + * or new values are used. Particular care should be taken with the pmg fi= eld + * as __mpam_sched_in() may read a partid and pmg that don't match, causing + * this value to be stored with cache allocations, despite being considered + * 'free' by resctrl. + * + * A value in struct thread_info is used instead of struct task_struct as = the + * cpu's u64 register format is used, but struct task_struct has two u32'. + */ +static inline u64 mpam_get_regval(struct task_struct *tsk) +{ +#ifdef CONFIG_ARM64_MPAM + return READ_ONCE(task_thread_info(tsk)->mpam_partid_pmg); +#else + return 0; +#endif +} + +static inline void mpam_thread_switch(struct task_struct *tsk) +{ + u64 oldregval; + int cpu =3D smp_processor_id(); + u64 regval =3D mpam_get_regval(tsk); + + if (!IS_ENABLED(CONFIG_ARM64_MPAM) || + !static_branch_likely(&mpam_enabled)) + return; + + if (regval =3D=3D READ_ONCE(arm64_mpam_global_default)) + regval =3D READ_ONCE(per_cpu(arm64_mpam_default, cpu)); + + oldregval =3D READ_ONCE(per_cpu(arm64_mpam_current, cpu)); + if (oldregval =3D=3D regval) + return; + + write_sysreg_s(regval, SYS_MPAM1_EL1); + isb(); + + /* Synchronising the EL0 write is left until the ERET to EL0 */ + write_sysreg_s(regval, SYS_MPAM0_EL1); + + WRITE_ONCE(per_cpu(arm64_mpam_current, cpu), regval); +} +#endif /* __ASM__MPAM_H */ diff --git a/arch/arm64/include/asm/thread_info.h b/arch/arm64/include/asm/= thread_info.h index f241b8601ebd..c226dabd5019 100644 --- a/arch/arm64/include/asm/thread_info.h +++ b/arch/arm64/include/asm/thread_info.h @@ -41,6 +41,9 @@ struct thread_info { #ifdef CONFIG_SHADOW_CALL_STACK void *scs_base; void *scs_sp; +#endif +#ifdef CONFIG_ARM64_MPAM + u64 mpam_partid_pmg; #endif u32 cpu; }; diff --git a/arch/arm64/kernel/Makefile b/arch/arm64/kernel/Makefile index 76f32e424065..15979f366519 100644 --- a/arch/arm64/kernel/Makefile +++ b/arch/arm64/kernel/Makefile @@ -67,6 +67,7 @@ obj-$(CONFIG_CRASH_DUMP) +=3D crash_dump.o obj-$(CONFIG_VMCORE_INFO) +=3D vmcore_info.o obj-$(CONFIG_ARM_SDE_INTERFACE) +=3D sdei.o obj-$(CONFIG_ARM64_PTR_AUTH) +=3D pointer_auth.o +obj-$(CONFIG_ARM64_MPAM) +=3D mpam.o obj-$(CONFIG_ARM64_MTE) +=3D mte.o obj-y +=3D vdso-wrap.o obj-$(CONFIG_COMPAT_VDSO) +=3D vdso32-wrap.o diff --git a/arch/arm64/kernel/mpam.c b/arch/arm64/kernel/mpam.c new file mode 100644 index 000000000000..9866d2ca0faa --- /dev/null +++ b/arch/arm64/kernel/mpam.c @@ -0,0 +1,13 @@ +// SPDX-License-Identifier: GPL-2.0 +/* Copyright (C) 2025 Arm Ltd. */ + +#include + +#include +#include + +DEFINE_STATIC_KEY_FALSE(mpam_enabled); +DEFINE_PER_CPU(u64, arm64_mpam_default); +DEFINE_PER_CPU(u64, arm64_mpam_current); + +u64 arm64_mpam_global_default; diff --git a/arch/arm64/kernel/process.c b/arch/arm64/kernel/process.c index fba7ca102a8c..b510c0699313 100644 --- a/arch/arm64/kernel/process.c +++ b/arch/arm64/kernel/process.c @@ -51,6 +51,7 @@ #include #include #include +#include #include #include #include @@ -737,6 +738,12 @@ struct task_struct *__switch_to(struct task_struct *pr= ev, if (prev->thread.sctlr_user !=3D next->thread.sctlr_user) update_sctlr_el1(next->thread.sctlr_user); =20 + /* + * MPAM thread switch happens after the DSB to ensure prev's accesses + * use prev's MPAM settings. + */ + mpam_thread_switch(next); + /* the actual thread switch */ last =3D cpu_switch_to(prev, next); =20 diff --git a/drivers/resctrl/mpam_devices.c b/drivers/resctrl/mpam_devices.c index 0b5b158e1aaf..2996ad93fc3e 100644 --- a/drivers/resctrl/mpam_devices.c +++ b/drivers/resctrl/mpam_devices.c @@ -29,8 +29,6 @@ =20 #include "mpam_internal.h" =20 -DEFINE_STATIC_KEY_FALSE(mpam_enabled); /* This moves to arch code */ - /* * mpam_list_lock protects the SRCU lists when writing. Once the * mpam_enabled key is enabled these lists are read-only, diff --git a/drivers/resctrl/mpam_internal.h b/drivers/resctrl/mpam_interna= l.h index e79c3c47259c..4508a6654fe0 100644 --- a/drivers/resctrl/mpam_internal.h +++ b/drivers/resctrl/mpam_internal.h @@ -17,6 +17,8 @@ #include #include =20 +#include + #define MPAM_MSC_MAX_NUM_RIS 16 =20 struct platform_device; --=20 2.39.5 From nobody Tue Dec 16 07:34:20 2025 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 59A9A2C0F6F for ; Fri, 5 Dec 2025 21:59:37 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764971978; cv=none; b=TFnZGXBhvW0GPrDG7O3pNgmXDoJBGUpZu8hmVZ4mR0QvLJVFEdE8GHLVNGmbkOlKUlPkIqhEa6a6LxHIhz3ibxYMPro/Fju89blAFtdFWzI4wkES+G7cUx1RXqPKPVrEzwnwpBcm/sNlKM8MfqmJR+ri8JGv5ihbYwskDQxo3nc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764971978; c=relaxed/simple; bh=Y2C3HRErabhzZuANKJwwFPRXxgq8aRmmWSH4sZYiLAw=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=EryS6azQAo31vDnrEKoVHmcW5ALaHO9DQ6SIzQLQFy7u+5l0vYSW+ieLbuEx2PiW2kI7QSbM65ysQoComJjlSjLUou2iCY/hMlXZpg1Np6hZ+C1A8WljQ3CmSKw8elHp56bNqmm6e3JT8QV4fe6EVrnUb+VNxxBZ1QnHt8nio6g= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id E7D731A25; Fri, 5 Dec 2025 13:59:28 -0800 (PST) Received: from merodach.members.linode.com (usa-sjc-mx-foss1.foss.arm.com [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 867DA3F740; Fri, 5 Dec 2025 13:59:32 -0800 (PST) From: James Morse To: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: James Morse , D Scott Phillips OS , carl@os.amperecomputing.com, lcherian@marvell.com, bobo.shaobowang@huawei.com, tan.shaopeng@fujitsu.com, baolin.wang@linux.alibaba.com, Jamie Iles , Xin Hao , peternewman@google.com, dfustini@baylibre.com, amitsinght@marvell.com, David Hildenbrand , Dave Martin , Koba Ko , Shanker Donthineni , fenghuay@nvidia.com, baisheng.gao@unisoc.com, Jonathan Cameron , Gavin Shan , Ben Horgan , rohit.mathew@arm.com, reinette.chatre@intel.com, Punit Agrawal Subject: [RFC PATCH 02/38] arm64: mpam: Re-initialise MPAM regs when CPU comes online Date: Fri, 5 Dec 2025 21:58:25 +0000 Message-Id: <20251205215901.17772-3-james.morse@arm.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20251205215901.17772-1-james.morse@arm.com> References: <20251205215901.17772-1-james.morse@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Now that the MPAM system registers are expected to have values that change, reprogram them based on struct task_struct when a CPU is brought online. Previously MPAM's 'default PARTID' of 0 was used this is the PARTID that hardware guarantees to reset. Because there are a limited number of PARTID, this value is exposed to user space, meaning resctrl changes to the resctrl default group would also affect kernel threads. Instead, use the task's PARTID value for kernel work on behalf of user-space too. Signed-off-by: James Morse --- arch/arm64/kernel/cpufeature.c | 18 +++++++++++------- 1 file changed, 11 insertions(+), 7 deletions(-) diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c index 5ed401ff79e3..429128a181ac 100644 --- a/arch/arm64/kernel/cpufeature.c +++ b/arch/arm64/kernel/cpufeature.c @@ -86,6 +86,7 @@ #include #include #include +#include #include #include #include @@ -2439,13 +2440,16 @@ test_has_mpam(const struct arm64_cpu_capabilities *= entry, int scope) static void cpu_enable_mpam(const struct arm64_cpu_capabilities *entry) { - /* - * Access by the kernel (at EL1) should use the reserved PARTID - * which is configured unrestricted. This avoids priority-inversion - * where latency sensitive tasks have to wait for a task that has - * been throttled to release the lock. - */ - write_sysreg_s(0, SYS_MPAM1_EL1); + int cpu =3D smp_processor_id(); + u64 regval =3D 0; + + if (IS_ENABLED(CONFIG_MPAM)) + regval =3D READ_ONCE(per_cpu(arm64_mpam_current, cpu)); + + write_sysreg_s(regval, SYS_MPAM1_EL1); + isb(); + + write_sysreg_s(regval, SYS_MPAM0_EL1); } =20 static bool --=20 2.39.5 From nobody Tue Dec 16 07:34:20 2025 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 19CD2286405 for ; Fri, 5 Dec 2025 21:59:41 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764971983; cv=none; b=INt8dg/s/jNSYoyXf1xZCjEN+dp5iF9w9SOspT4juhZn/pPZ+zRUa7M1GjEXQhr1VDEErnuUNMVGUfHPZ/vt6hnf4CjpHb+gsWY6nuT9K1jJpruolJRWw0uhzdu0v17cAba0N0lzM7Ut3XCgW48WtCT90eAZgRTy0ifnqzlKZJA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764971983; c=relaxed/simple; bh=UosMmBFCjkmP2njqe3SsIp2hP9pn+gP1cZOixSsYthc=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=cilIjGPA1ytq+tsUm3c/EBvqzUZQ79vhbeVfha8x+hBX76HDuqXGFNTtts8db/i13C1SpcpGMxVXADjkXPDM8gX912mW0Y+7nktM8ast3S5Fq58nVVAxPUFDECHI54vM24UqKerebZL/Z6lc36YIV5N72E/JT0HTKbTh/ITAxvY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 08FFA1A32; Fri, 5 Dec 2025 13:59:33 -0800 (PST) Received: from merodach.members.linode.com (usa-sjc-mx-foss1.foss.arm.com [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 8D8623F740; Fri, 5 Dec 2025 13:59:36 -0800 (PST) From: James Morse To: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: James Morse , D Scott Phillips OS , carl@os.amperecomputing.com, lcherian@marvell.com, bobo.shaobowang@huawei.com, tan.shaopeng@fujitsu.com, baolin.wang@linux.alibaba.com, Jamie Iles , Xin Hao , peternewman@google.com, dfustini@baylibre.com, amitsinght@marvell.com, David Hildenbrand , Dave Martin , Koba Ko , Shanker Donthineni , fenghuay@nvidia.com, baisheng.gao@unisoc.com, Jonathan Cameron , Gavin Shan , Ben Horgan , rohit.mathew@arm.com, reinette.chatre@intel.com, Punit Agrawal Subject: [RFC PATCH 03/38] arm64: mpam: Advertise the CPUs MPAM limits to the driver Date: Fri, 5 Dec 2025 21:58:26 +0000 Message-Id: <20251205215901.17772-4-james.morse@arm.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20251205215901.17772-1-james.morse@arm.com> References: <20251205215901.17772-1-james.morse@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Requestors need to populate the MPAM fields for any traffic they send on the interconnect. For the CPUs these values are taken from the corresponding MPAMy_ELx register. Each requestor may have a limit on the largest PARTID or PMG value that can be used. The MPAM driver has to determine the system-wide minimum supported PARTID and PMG values. To do this, the driver needs to be told what each requestor's limit is. CPUs are special, but this infrastructure is also needed for the SMMU and GIC ITS. Call the helper to tell the MPAM driver what the CPUs can do. The return value can be ignored by the arch code as it runs well before the MPAM driver starts probing. Signed-off-by: James Morse --- arch/arm64/kernel/mpam.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm64/kernel/mpam.c b/arch/arm64/kernel/mpam.c index 9866d2ca0faa..e6feff2324ac 100644 --- a/arch/arm64/kernel/mpam.c +++ b/arch/arm64/kernel/mpam.c @@ -3,6 +3,7 @@ =20 #include =20 +#include #include #include =20 @@ -11,3 +12,14 @@ DEFINE_PER_CPU(u64, arm64_mpam_default); DEFINE_PER_CPU(u64, arm64_mpam_current); =20 u64 arm64_mpam_global_default; + +static int __init arm64_mpam_register_cpus(void) +{ + u64 mpamidr =3D read_sanitised_ftr_reg(SYS_MPAMIDR_EL1); + u16 partid_max =3D FIELD_GET(MPAMIDR_EL1_PARTID_MAX, mpamidr); + u8 pmg_max =3D FIELD_GET(MPAMIDR_EL1_PMG_MAX, mpamidr); + + return mpam_register_requestor(partid_max, pmg_max); +} +/* Must occur before mpam_msc_driver_init() from subsys_initcall() */ +arch_initcall(arm64_mpam_register_cpus) --=20 2.39.5 From nobody Tue Dec 16 07:34:20 2025 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 039891E1DFC for ; Fri, 5 Dec 2025 21:59:44 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764971987; cv=none; b=E/KRIs1R1he7d2PH7ZizvJg8eD925PSQZWoadHfF9xvkxPBXLTg9HskjJKe/k4u7M4PVfZ6rMDLDuUT2p8K7pAGH/hVuce/yKVI5p9Ub8FUSPXxemEa9N8YonJ20i6C99hIAj9nbok/kyq+SEDeBnH1JKX7PbNc/OOVtuCzrFhs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764971987; c=relaxed/simple; bh=72orXuFTaz4a1JXCn/twJq8FRo8TgJm6qgBEBr7/5ro=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=rxcnF1texOHneJ5VdUEFhECJxRBq7XDJxuWB82xMduSG6fBN099IReHHB68P7fp8Wrls5L50fx1ictmZ/bzqVAHgof96GR8M/JTidA2A9N3DcOoUvZZs2TBdEJt2Q80LjGAPmca2Wa6mlgFT432u4M6SgIDhGbQuR8ytOMMpXwk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id F147B1A25; Fri, 5 Dec 2025 13:59:36 -0800 (PST) Received: from merodach.members.linode.com (usa-sjc-mx-foss1.foss.arm.com [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 93CEA3F740; Fri, 5 Dec 2025 13:59:40 -0800 (PST) From: James Morse To: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: James Morse , D Scott Phillips OS , carl@os.amperecomputing.com, lcherian@marvell.com, bobo.shaobowang@huawei.com, tan.shaopeng@fujitsu.com, baolin.wang@linux.alibaba.com, Jamie Iles , Xin Hao , peternewman@google.com, dfustini@baylibre.com, amitsinght@marvell.com, David Hildenbrand , Dave Martin , Koba Ko , Shanker Donthineni , fenghuay@nvidia.com, baisheng.gao@unisoc.com, Jonathan Cameron , Gavin Shan , Ben Horgan , rohit.mathew@arm.com, reinette.chatre@intel.com, Punit Agrawal Subject: [RFC PATCH 04/38] arm64: mpam: Add cpu_pm notifier to restore MPAM sysregs Date: Fri, 5 Dec 2025 21:58:27 +0000 Message-Id: <20251205215901.17772-5-james.morse@arm.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20251205215901.17772-1-james.morse@arm.com> References: <20251205215901.17772-1-james.morse@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The MPAM system registers will be lost if the CPU is reset during PSCI's CPU_SUSPEND. Add a PM notifier to restore them. mpam_thread_switch(current) can't be used as this won't make any changes if the in-memory copy says the register already has the correct value. In reality the system register is UNKNOWN out of reset. Signed-off-by: James Morse --- arch/arm64/kernel/mpam.c | 30 ++++++++++++++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/arch/arm64/kernel/mpam.c b/arch/arm64/kernel/mpam.c index e6feff2324ac..dbe0a2d05abb 100644 --- a/arch/arm64/kernel/mpam.c +++ b/arch/arm64/kernel/mpam.c @@ -4,6 +4,7 @@ #include =20 #include +#include #include #include =20 @@ -13,12 +14,41 @@ DEFINE_PER_CPU(u64, arm64_mpam_current); =20 u64 arm64_mpam_global_default; =20 +static int mpam_pm_notifier(struct notifier_block *self, + unsigned long cmd, void *v) +{ + u64 regval; + int cpu =3D smp_processor_id(); + + switch (cmd) { + case CPU_PM_EXIT: + /* + * Don't use mpam_thread_switch() as the system register + * value has changed under our feet. + */ + regval =3D READ_ONCE(per_cpu(arm64_mpam_current, cpu)); + write_sysreg_s(regval, SYS_MPAM1_EL1); + isb(); + + write_sysreg_s(regval, SYS_MPAM0_EL1); + + return NOTIFY_OK; + default: + return NOTIFY_DONE; + } +} + +static struct notifier_block mpam_pm_nb =3D { + .notifier_call =3D mpam_pm_notifier, +}; + static int __init arm64_mpam_register_cpus(void) { u64 mpamidr =3D read_sanitised_ftr_reg(SYS_MPAMIDR_EL1); u16 partid_max =3D FIELD_GET(MPAMIDR_EL1_PARTID_MAX, mpamidr); u8 pmg_max =3D FIELD_GET(MPAMIDR_EL1_PMG_MAX, mpamidr); =20 + cpu_pm_register_notifier(&mpam_pm_nb); return mpam_register_requestor(partid_max, pmg_max); } /* Must occur before mpam_msc_driver_init() from subsys_initcall() */ --=20 2.39.5 From nobody Tue Dec 16 07:34:20 2025 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 607C92D9493 for ; Fri, 5 Dec 2025 21:59:49 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764971992; cv=none; b=a6xyR+EP2dTdpFz87h7c9x4vQXRh3raDCb3peJoiSzHmQf0vSFXM8Z+LcipuFa+QwC0xjcqzF5j9t8wCW9kfUY5KgoVjPivaT/NOEsuXgtvlWkgJNKk9hXl9OB3YzRVDG8CPHYgTVjRynRi/F/kiRGmqjlIrSFsqQBg4cIxcNTI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764971992; c=relaxed/simple; bh=cSus2geGI3l9W46KiKllHlUOTMbq0pgEOL6GvtLBw+A=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=b+AiyGth7RrgMPh3lHFxaRLqC01LqOxiiL3l6IpljpwyS70eEyD9q3KHEbDtD9ExNR7MwHBNgusiUsExR8mZHhLA11PqxxzF9UzixRJ1cl2mrv2BIa8hudgCLW9uelWLX+IRH8wGe33NU8QWDo6y7mjxaq5h9uM9Ot2FCp2gYMI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 25C8A1AC1; Fri, 5 Dec 2025 13:59:41 -0800 (PST) Received: from merodach.members.linode.com (usa-sjc-mx-foss1.foss.arm.com [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 979FB3F740; Fri, 5 Dec 2025 13:59:44 -0800 (PST) From: James Morse To: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: James Morse , D Scott Phillips OS , carl@os.amperecomputing.com, lcherian@marvell.com, bobo.shaobowang@huawei.com, tan.shaopeng@fujitsu.com, baolin.wang@linux.alibaba.com, Jamie Iles , Xin Hao , peternewman@google.com, dfustini@baylibre.com, amitsinght@marvell.com, David Hildenbrand , Dave Martin , Koba Ko , Shanker Donthineni , fenghuay@nvidia.com, baisheng.gao@unisoc.com, Jonathan Cameron , Gavin Shan , Ben Horgan , rohit.mathew@arm.com, reinette.chatre@intel.com, Punit Agrawal , Dave Martin Subject: [RFC PATCH 05/38] arm64: mpam: Add helpers to change a task or cpu's MPAM PARTID/PMG values Date: Fri, 5 Dec 2025 21:58:28 +0000 Message-Id: <20251205215901.17772-6-james.morse@arm.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20251205215901.17772-1-james.morse@arm.com> References: <20251205215901.17772-1-james.morse@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Care must be taken when modifying the PARTID and PMG of a task in any per-task structure as writing these values may race with the task being scheduled in, and reading the modified values. Add helpers to set the task properties, and the CPU default value. These use WRITE_ONCE() that pairs with the READ_ONCE() in mpam_get_regval() to avoid causing torn values. CC: Dave Martin CC: Ben Horgan Signed-off-by: James Morse --- arch/arm64/include/asm/mpam.h | 30 ++++++++++++++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/arch/arm64/include/asm/mpam.h b/arch/arm64/include/asm/mpam.h index 86a55176f884..2960ffaf6574 100644 --- a/arch/arm64/include/asm/mpam.h +++ b/arch/arm64/include/asm/mpam.h @@ -5,6 +5,7 @@ #define __ASM__MPAM_H =20 #include +#include #include #include #include @@ -37,6 +38,35 @@ extern u64 arm64_mpam_global_default; * A value in struct thread_info is used instead of struct task_struct as = the * cpu's u64 register format is used, but struct task_struct has two u32'. */ +static inline void mpam_set_cpu_defaults(int cpu, u16 partid_d, u16 partid= _i, + u8 pmg_d, u8 pmg_i) +{ + u64 default_val; + + default_val =3D FIELD_PREP(MPAM0_EL1_PARTID_D, partid_d); + default_val |=3D FIELD_PREP(MPAM0_EL1_PARTID_I, partid_i); + default_val |=3D FIELD_PREP(MPAM0_EL1_PMG_D, pmg_d); + default_val |=3D FIELD_PREP(MPAM0_EL1_PMG_I, pmg_i); + + WRITE_ONCE(per_cpu(arm64_mpam_default, cpu), default_val); +} + +static inline void mpam_set_task_partid_pmg(struct task_struct *tsk, + u16 partid_d, u16 partid_i, + u8 pmg_d, u8 pmg_i) +{ +#ifdef CONFIG_ARM64_MPAM + u64 regval; + + regval =3D FIELD_PREP(MPAM0_EL1_PARTID_D, partid_d); + regval |=3D FIELD_PREP(MPAM0_EL1_PARTID_I, partid_i); + regval |=3D FIELD_PREP(MPAM0_EL1_PMG_D, pmg_d); + regval |=3D FIELD_PREP(MPAM0_EL1_PMG_I, pmg_i); + + WRITE_ONCE(task_thread_info(tsk)->mpam_partid_pmg, regval); +#endif +} + static inline u64 mpam_get_regval(struct task_struct *tsk) { #ifdef CONFIG_ARM64_MPAM --=20 2.39.5 From nobody Tue Dec 16 07:34:20 2025 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id E1F1E2D877B for ; Fri, 5 Dec 2025 21:59:53 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764971995; cv=none; b=CuGz7oYbmqve2D3ANBF5xwr/Z0V9xofovc37C/4v85g7kErM5TzRwhXQQV5xl0MWzaJ/to4g2wLLjfo7BCsUeQ1TxvyxuHGWBcthpaK08wRdXJa4srBrBKreYzYJ9IGy52dCiwLiU4FBevAyC8LZ7ofLF8l/agmVzTWUfm6uZtY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764971995; c=relaxed/simple; bh=J9WAGI8WAt69+pKH/2+K+7un+qCHL2qLCTCpm3LTkn0=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=ED6IqD11/1HHM8nFbhaES63wn8/HQIyhV3lOWtAN2W+uuIBGKkTDacp7nco3Oin2TRF/51Zy6xLF7Ji8vuB3eOIeebjuyFQLxxpewPwf3P3d1/9s6ZIBuvU8wpjTJ+D0CyT+8OkIiWqFCxUSuKRtF1b78q5W1cJDWVWk1IJ+snI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 2C3F31A9A; Fri, 5 Dec 2025 13:59:45 -0800 (PST) Received: from merodach.members.linode.com (usa-sjc-mx-foss1.foss.arm.com [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id C07FA3F740; Fri, 5 Dec 2025 13:59:48 -0800 (PST) From: James Morse To: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: James Morse , D Scott Phillips OS , carl@os.amperecomputing.com, lcherian@marvell.com, bobo.shaobowang@huawei.com, tan.shaopeng@fujitsu.com, baolin.wang@linux.alibaba.com, Jamie Iles , Xin Hao , peternewman@google.com, dfustini@baylibre.com, amitsinght@marvell.com, David Hildenbrand , Dave Martin , Koba Ko , Shanker Donthineni , fenghuay@nvidia.com, baisheng.gao@unisoc.com, Jonathan Cameron , Gavin Shan , Ben Horgan , rohit.mathew@arm.com, reinette.chatre@intel.com, Punit Agrawal Subject: [RFC PATCH 06/38] KVM: arm64: Force guest EL1 to use user-space's partid configuration Date: Fri, 5 Dec 2025 21:58:29 +0000 Message-Id: <20251205215901.17772-7-james.morse@arm.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20251205215901.17772-1-james.morse@arm.com> References: <20251205215901.17772-1-james.morse@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" While we trap the guest's attempts to read/write the MPAM control registers, the hardware continues to use them. Guest-EL0 uses KVM's user-space's configuration, as the value is left in the register, and guest-EL1 uses either the host kernel's configuration, or in the case of VHE, the UNKNOWN reset value of MPAM1_EL1. On nVHE systems, EL2 continues to use partid-0 for world-switch, even when the host may have configured its kernel threads to use a different partid. 0 may have been assigned to another task. We want to force the guest-EL1 to use KVM's user-space's MPAM configuration, and EL2s to match the host's EL1 config. On a nVHE system, copy the EL1 MPAM register to EL2. This ensures world-switch uses the same partid as the kernel thread does on the host. When loading the guest's EL1 registers, copy the VMM's EL0 partid to the EL1 register. For VHE systems, we can skip restoring the EL1 register for the host, as it is out-of-context once HCR_EL2.TGE is set. This is done outside the usual sysreg save/restore as the values can change behind KVMs back, so should not be stored in the guest context. Signed-off-by: James Morse --- arch/arm64/include/asm/kvm_host.h | 1 + arch/arm64/kvm/hyp/include/hyp/sysreg-sr.h | 16 ++++++++++++++++ arch/arm64/kvm/hyp/nvhe/switch.c | 12 ++++++++++++ arch/arm64/kvm/hyp/vhe/sysreg-sr.c | 1 + 4 files changed, 30 insertions(+) diff --git a/arch/arm64/include/asm/kvm_host.h b/arch/arm64/include/asm/kvm= _host.h index b763293281c8..baba23b7ce97 100644 --- a/arch/arm64/include/asm/kvm_host.h +++ b/arch/arm64/include/asm/kvm_host.h @@ -447,6 +447,7 @@ enum vcpu_sysreg { MDCCINT_EL1, /* Monitor Debug Comms Channel Interrupt Enable Reg */ OSLSR_EL1, /* OS Lock Status Register */ DISR_EL1, /* Deferred Interrupt Status Register */ + MPAM1_EL1, /* Memory Partitioning And Monitoring register */ =20 /* Performance Monitors Registers */ PMCR_EL0, /* Control Register */ diff --git a/arch/arm64/kvm/hyp/include/hyp/sysreg-sr.h b/arch/arm64/kvm/hy= p/include/hyp/sysreg-sr.h index a17cbe7582de..d8ab0ced0403 100644 --- a/arch/arm64/kvm/hyp/include/hyp/sysreg-sr.h +++ b/arch/arm64/kvm/hyp/include/hyp/sysreg-sr.h @@ -166,6 +166,9 @@ static inline void __sysreg_save_el1_state(struct kvm_c= pu_context *ctxt) ctxt_sys_reg(ctxt, TFSRE0_EL1) =3D read_sysreg_s(SYS_TFSRE0_EL1); } =20 + if (system_supports_mpam()) + ctxt_sys_reg(ctxt, MPAM1_EL1) =3D read_sysreg_el1(SYS_MPAM1); + ctxt_sys_reg(ctxt, SP_EL1) =3D read_sysreg(sp_el1); ctxt_sys_reg(ctxt, ELR_EL1) =3D read_sysreg_el1(SYS_ELR); ctxt_sys_reg(ctxt, SPSR_EL1) =3D read_sysreg_el1(SYS_SPSR); @@ -261,6 +264,9 @@ static inline void __sysreg_restore_el1_state(struct kv= m_cpu_context *ctxt, write_sysreg_s(ctxt_sys_reg(ctxt, TFSRE0_EL1), SYS_TFSRE0_EL1); } =20 + if (system_supports_mpam()) + write_sysreg_el1(ctxt_sys_reg(ctxt, MPAM1_EL1), SYS_MPAM1); + if (!has_vhe() && cpus_have_final_cap(ARM64_WORKAROUND_SPECULATIVE_AT) && ctxt->__hyp_running_vcpu) { @@ -374,4 +380,14 @@ static inline void __sysreg32_restore_state(struct kvm= _vcpu *vcpu) write_sysreg(__vcpu_sys_reg(vcpu, DBGVCR32_EL2), dbgvcr32_el2); } =20 +/* + * The _EL0 value was written by the host's context switch and belongs to = the + * VMM. Copy this into the guest's _EL1 register. + */ +static inline void __mpam_guest_load(void) +{ + if (system_supports_mpam()) + write_sysreg_el1(read_sysreg_s(SYS_MPAM0_EL1), SYS_MPAM1); +} + #endif /* __ARM64_KVM_HYP_SYSREG_SR_H__ */ diff --git a/arch/arm64/kvm/hyp/nvhe/switch.c b/arch/arm64/kvm/hyp/nvhe/swi= tch.c index d3b9ec8a7c28..b785977aa61e 100644 --- a/arch/arm64/kvm/hyp/nvhe/switch.c +++ b/arch/arm64/kvm/hyp/nvhe/switch.c @@ -238,6 +238,15 @@ static inline bool fixup_guest_exit(struct kvm_vcpu *v= cpu, u64 *exit_code) return __fixup_guest_exit(vcpu, exit_code, handlers); } =20 +/* Use the host thread's partid and pmg for world switch */ +static void __mpam_copy_el1_to_el2(void) +{ + if (system_supports_mpam()) { + write_sysreg_s(read_sysreg_s(SYS_MPAM1_EL1), SYS_MPAM2_EL2); + isb(); + } +} + /* Switch to the guest for legacy non-VHE systems */ int __kvm_vcpu_run(struct kvm_vcpu *vcpu) { @@ -247,6 +256,8 @@ int __kvm_vcpu_run(struct kvm_vcpu *vcpu) bool pmu_switch_needed; u64 exit_code; =20 + __mpam_copy_el1_to_el2(); + /* * Having IRQs masked via PMR when entering the guest means the GIC * will not signal the CPU of interrupts of lower priority, and the @@ -306,6 +317,7 @@ int __kvm_vcpu_run(struct kvm_vcpu *vcpu) __timer_enable_traps(vcpu); =20 __debug_switch_to_guest(vcpu); + __mpam_guest_load(); =20 do { /* Jump in the fire! */ diff --git a/arch/arm64/kvm/hyp/vhe/sysreg-sr.c b/arch/arm64/kvm/hyp/vhe/sy= sreg-sr.c index f28c6cf4fe1b..2a84edc90465 100644 --- a/arch/arm64/kvm/hyp/vhe/sysreg-sr.c +++ b/arch/arm64/kvm/hyp/vhe/sysreg-sr.c @@ -222,6 +222,7 @@ void __vcpu_load_switch_sysregs(struct kvm_vcpu *vcpu) */ __sysreg32_restore_state(vcpu); __sysreg_restore_user_state(guest_ctxt); + __mpam_guest_load(); =20 if (unlikely(is_hyp_ctxt(vcpu))) { __sysreg_restore_vel2_state(vcpu); --=20 2.39.5 From nobody Tue Dec 16 07:34:20 2025 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 296FC2D24B6 for ; Fri, 5 Dec 2025 21:59:57 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764971999; cv=none; b=bAq1vk7vXVpOxQKUWhmBx75PU0MdmjOcs+eND0R5HhIdwyWASdTcq01K+/9Yd+/IGIdplxA9nY9r/J1fv9E+Z/Y/pwOzFZqhUWUY42cCmOIlM3f5yjKoUBymU64J5BqX00WjNFzEpdmZ4ksjcQ83VJaseLRvD952kFHCFYp2b/s= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764971999; c=relaxed/simple; bh=wYO1QFMibMa7iq/+SMFgNtmx4trfog3agVNQazzblH4=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=Hnn0u3B9dTJdcUZxNr+AX2PTGkWEM6WoA7jx2Cbnf3TtUcOEeYEnshHEaUh8OIJlV7H1ZYrFu746AXmuA+Jr99RlxjBFy+lO4/ZSYInbT8aYrWezBKmWXfHPwR/gf8F6WZTeCjHRfFv/6GJZCiEKiuaZp3Og80TX4w2VJm8b2PU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 5802E1AC1; Fri, 5 Dec 2025 13:59:49 -0800 (PST) Received: from merodach.members.linode.com (usa-sjc-mx-foss1.foss.arm.com [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id C75003F740; Fri, 5 Dec 2025 13:59:52 -0800 (PST) From: James Morse To: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: James Morse , D Scott Phillips OS , carl@os.amperecomputing.com, lcherian@marvell.com, bobo.shaobowang@huawei.com, tan.shaopeng@fujitsu.com, baolin.wang@linux.alibaba.com, Jamie Iles , Xin Hao , peternewman@google.com, dfustini@baylibre.com, amitsinght@marvell.com, David Hildenbrand , Dave Martin , Koba Ko , Shanker Donthineni , fenghuay@nvidia.com, baisheng.gao@unisoc.com, Jonathan Cameron , Gavin Shan , Ben Horgan , rohit.mathew@arm.com, reinette.chatre@intel.com, Punit Agrawal Subject: [RFC PATCH 07/38] arm_mpam: resctrl: Add boilerplate cpuhp and domain allocation Date: Fri, 5 Dec 2025 21:58:30 +0000 Message-Id: <20251205215901.17772-8-james.morse@arm.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20251205215901.17772-1-james.morse@arm.com> References: <20251205215901.17772-1-james.morse@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" resctrl has its own data structures to describe its resources. We can't use these directly as we play tricks with the 'MBA' resource, picking the MPAM controls or monitors that best apply. We may export the same component as both L3 and MBA. Add mpam_resctrl_exports[] as the array of class->resctrl mappings we are exporting, and add the cpuhp hooks that allocated and free the resctrl domain structures. While we're here, plumb in a few other obvious things. CONFIG_ARM_CPU_RESCTRL is used to allow this code to be built even though it can't yet be linked against resctrl. Signed-off-by: James Morse --- drivers/resctrl/Makefile | 1 + drivers/resctrl/mpam_devices.c | 12 ++ drivers/resctrl/mpam_internal.h | 22 +++ drivers/resctrl/mpam_resctrl.c | 329 ++++++++++++++++++++++++++++++++ include/linux/arm_mpam.h | 3 + 5 files changed, 367 insertions(+) create mode 100644 drivers/resctrl/mpam_resctrl.c diff --git a/drivers/resctrl/Makefile b/drivers/resctrl/Makefile index 898199dcf80d..40beaf999582 100644 --- a/drivers/resctrl/Makefile +++ b/drivers/resctrl/Makefile @@ -1,4 +1,5 @@ obj-$(CONFIG_ARM64_MPAM_DRIVER) +=3D mpam.o mpam-y +=3D mpam_devices.o +mpam-$(CONFIG_ARM_CPU_RESCTRL) +=3D mpam_resctrl.o =20 ccflags-$(CONFIG_ARM64_MPAM_DRIVER_DEBUG) +=3D -DDEBUG diff --git a/drivers/resctrl/mpam_devices.c b/drivers/resctrl/mpam_devices.c index 2996ad93fc3e..efaf7633bc35 100644 --- a/drivers/resctrl/mpam_devices.c +++ b/drivers/resctrl/mpam_devices.c @@ -1627,6 +1627,9 @@ static int mpam_cpu_online(unsigned int cpu) mpam_reprogram_msc(msc); } =20 + if (mpam_is_enabled()) + mpam_resctrl_online_cpu(cpu); + return 0; } =20 @@ -1670,6 +1673,9 @@ static int mpam_cpu_offline(unsigned int cpu) { struct mpam_msc *msc; =20 + if (mpam_is_enabled()) + mpam_resctrl_offline_cpu(cpu); + guard(srcu)(&mpam_srcu); list_for_each_entry_srcu(msc, &mpam_all_msc, all_msc_list, srcu_read_lock_held(&mpam_srcu)) { @@ -2516,6 +2522,12 @@ static void mpam_enable_once(void) mutex_unlock(&mpam_list_lock); cpus_read_unlock(); =20 + if (!err) { + err =3D mpam_resctrl_setup(); + if (err) + pr_err("Failed to initialise resctrl: %d\n", err); + } + if (err) { mpam_disable_reason =3D "Failed to enable."; schedule_work(&mpam_broken_work); diff --git a/drivers/resctrl/mpam_internal.h b/drivers/resctrl/mpam_interna= l.h index 4508a6654fe0..dfd3512ac924 100644 --- a/drivers/resctrl/mpam_internal.h +++ b/drivers/resctrl/mpam_internal.h @@ -12,6 +12,7 @@ #include #include #include +#include #include #include #include @@ -336,6 +337,17 @@ struct mpam_msc_ris { struct mpam_garbage garbage; }; =20 +struct mpam_resctrl_dom { + struct mpam_component *ctrl_comp; + struct rdt_ctrl_domain resctrl_ctrl_dom; + struct rdt_mon_domain resctrl_mon_dom; +}; + +struct mpam_resctrl_res { + struct mpam_class *class; + struct rdt_resource resctrl_res; +}; + static inline int mpam_alloc_csu_mon(struct mpam_class *class) { struct mpam_props *cprops =3D &class->props; @@ -390,6 +402,16 @@ void mpam_msmon_reset_mbwu(struct mpam_component *comp= , struct mon_cfg *ctx); int mpam_get_cpumask_from_cache_id(unsigned long cache_id, u32 cache_level, cpumask_t *affinity); =20 +#ifdef CONFIG_RESCTRL_FS +int mpam_resctrl_setup(void); +int mpam_resctrl_online_cpu(unsigned int cpu); +void mpam_resctrl_offline_cpu(unsigned int cpu); +#else +static inline int mpam_resctrl_setup(void) { return 0; } +static inline int mpam_resctrl_online_cpu(unsigned int cpu) { return 0; } +static inline void mpam_resctrl_offline_cpu(unsigned int cpu) { } +#endif /* CONFIG_RESCTRL_FS */ + /* * MPAM MSCs have the following register layout. See: * Arm Memory System Resource Partitioning and Monitoring (MPAM) System diff --git a/drivers/resctrl/mpam_resctrl.c b/drivers/resctrl/mpam_resctrl.c new file mode 100644 index 000000000000..320cebbd37ce --- /dev/null +++ b/drivers/resctrl/mpam_resctrl.c @@ -0,0 +1,329 @@ +// SPDX-License-Identifier: GPL-2.0 +// Copyright (C) 2025 Arm Ltd. + +#define pr_fmt(fmt) "%s:%s: " fmt, KBUILD_MODNAME, __func__ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#include "mpam_internal.h" + +/* + * The classes we've picked to map to resctrl resources, wrapped + * in with their resctrl structure. + * Class pointer may be NULL. + */ +static struct mpam_resctrl_res mpam_resctrl_controls[RDT_NUM_RESOURCES]; + +/* The lock for modifying resctrl's domain lists from cpuhp callbacks. */ +static DEFINE_MUTEX(domain_list_lock); + +static bool exposed_alloc_capable; +static bool exposed_mon_capable; + +bool resctrl_arch_alloc_capable(void) +{ + return exposed_alloc_capable; +} + +bool resctrl_arch_mon_capable(void) +{ + return exposed_mon_capable; +} + +/* + * MSC may raise an error interrupt if it sees an out or range partid/pmg, + * and go on to truncate the value. Regardless of what the hardware suppor= ts, + * only the system wide safe value is safe to use. + */ +u32 resctrl_arch_get_num_closid(struct rdt_resource *ignored) +{ + return mpam_partid_max + 1; +} + +struct rdt_resource *resctrl_arch_get_resource(enum resctrl_res_level l) +{ + if (l >=3D RDT_NUM_RESOURCES) + return NULL; + + return &mpam_resctrl_controls[l].resctrl_res; +} + +static int mpam_resctrl_control_init(struct mpam_resctrl_res *res, + enum resctrl_res_level type) +{ + /* TODO: initialise the resctrl resources */ + + return 0; +} + +static int mpam_resctrl_pick_domain_id(int cpu, struct mpam_component *com= p) +{ + struct mpam_class *class =3D comp->class; + + if (class->type =3D=3D MPAM_CLASS_CACHE) + return comp->comp_id; + + /* TODO: repaint domain ids to match the L3 domain ids */ + /* + * Otherwise, expose the ID used by the firmware table code. + */ + return comp->comp_id; +} + +static void mpam_resctrl_domain_hdr_init(int cpu, struct mpam_component *c= omp, + struct rdt_domain_hdr *hdr) +{ + lockdep_assert_cpus_held(); + + INIT_LIST_HEAD(&hdr->list); + hdr->id =3D mpam_resctrl_pick_domain_id(cpu, comp); + cpumask_set_cpu(cpu, &hdr->cpu_mask); +} + +/** + * mpam_resctrl_offline_domain_hdr() - Update the domain header to remove = a CPU. + * @cpu: The CPU to remove from the domain. + * @hdr: The domain's header. + * + * Removes @cpu from the header mask. If this was the last CPU in the doma= in, + * the domain header is removed from its parent list and true is returned, + * indicating the parent structure can be freed. + * If there are other CPUs in the domain, returns false. + */ +static bool mpam_resctrl_offline_domain_hdr(unsigned int cpu, + struct rdt_domain_hdr *hdr) +{ + cpumask_clear_cpu(cpu, &hdr->cpu_mask); + if (cpumask_empty(&hdr->cpu_mask)) { + list_del(&hdr->list); + return true; + } + + return false; +} + +static struct mpam_resctrl_dom * +mpam_resctrl_alloc_domain(unsigned int cpu, struct mpam_resctrl_res *res) +{ + int err; + struct mpam_resctrl_dom *dom; + struct rdt_mon_domain *mon_d; + struct rdt_ctrl_domain *ctrl_d; + struct mpam_class *class =3D res->class; + struct mpam_component *comp_iter, *ctrl_comp; + struct rdt_resource *r =3D &res->resctrl_res; + + lockdep_assert_held(&domain_list_lock); + + ctrl_comp =3D NULL; + guard(srcu)(&mpam_srcu); + list_for_each_entry_srcu(comp_iter, &class->components, class_list, + srcu_read_lock_held(&mpam_srcu)) { + if (cpumask_test_cpu(cpu, &comp_iter->affinity)) { + ctrl_comp =3D comp_iter; + break; + } + } + + /* class has no component for this CPU */ + if (WARN_ON_ONCE(!ctrl_comp)) + return ERR_PTR(-EINVAL); + + dom =3D kzalloc_node(sizeof(*dom), GFP_KERNEL, cpu_to_node(cpu)); + if (!dom) + return ERR_PTR(-ENOMEM); + + if (exposed_alloc_capable) { + dom->ctrl_comp =3D ctrl_comp; + + ctrl_d =3D &dom->resctrl_ctrl_dom; + mpam_resctrl_domain_hdr_init(cpu, ctrl_comp, &ctrl_d->hdr); + ctrl_d->hdr.type =3D RESCTRL_CTRL_DOMAIN; + /* TODO: this list should be sorted */ + list_add_tail_rcu(&ctrl_d->hdr.list, &r->ctrl_domains); + err =3D resctrl_online_ctrl_domain(r, ctrl_d); + if (err) { + dom =3D ERR_PTR(err); + goto offline_ctrl_domain; + } + } else { + pr_debug("Skipped control domain online - no controls\n"); + } + + if (exposed_mon_capable) { + mon_d =3D &dom->resctrl_mon_dom; + mpam_resctrl_domain_hdr_init(cpu, ctrl_comp, &mon_d->hdr); + mon_d->hdr.type =3D RESCTRL_MON_DOMAIN; + /* TODO: this list should be sorted */ + list_add_tail_rcu(&mon_d->hdr.list, &r->mon_domains); + err =3D resctrl_online_mon_domain(r, mon_d); + if (err) { + dom =3D ERR_PTR(err); + goto offline_mon_hdr; + } + } else { + pr_debug("Skipped monitor domain online - no monitors\n"); + } + goto out; + +offline_mon_hdr: + mpam_resctrl_offline_domain_hdr(cpu, &mon_d->hdr); +offline_ctrl_domain: + resctrl_offline_ctrl_domain(r, ctrl_d); +out: + return dom; +} + +static struct mpam_resctrl_dom * +mpam_resctrl_get_domain_from_cpu(int cpu, struct mpam_resctrl_res *res) +{ + struct mpam_resctrl_dom *dom; + struct rdt_ctrl_domain *ctrl_d; + + lockdep_assert_cpus_held(); + + list_for_each_entry_rcu(ctrl_d, &res->resctrl_res.ctrl_domains, + hdr.list) { + dom =3D container_of(ctrl_d, struct mpam_resctrl_dom, + resctrl_ctrl_dom); + + if (cpumask_test_cpu(cpu, &dom->ctrl_comp->affinity)) + return dom; + } + + return NULL; +} + +int mpam_resctrl_online_cpu(unsigned int cpu) +{ + int i; + struct mpam_resctrl_dom *dom; + struct mpam_resctrl_res *res; + + guard(mutex)(&domain_list_lock); + for (i =3D 0; i < RDT_NUM_RESOURCES; i++) { + res =3D &mpam_resctrl_controls[i]; + if (!res->class) + continue; // dummy_resource; + + dom =3D mpam_resctrl_get_domain_from_cpu(cpu, res); + if (!dom) + dom =3D mpam_resctrl_alloc_domain(cpu, res); + if (IS_ERR(dom)) + return PTR_ERR(dom); + } + + resctrl_online_cpu(cpu); + + return 0; +} + +void mpam_resctrl_offline_cpu(unsigned int cpu) +{ + int i; + struct mpam_resctrl_res *res; + struct mpam_resctrl_dom *dom; + struct rdt_mon_domain *mon_d; + struct rdt_ctrl_domain *ctrl_d; + bool ctrl_dom_empty, mon_dom_empty; + + resctrl_offline_cpu(cpu); + + guard(mutex)(&domain_list_lock); + for (i =3D 0; i < RDT_NUM_RESOURCES; i++) { + res =3D &mpam_resctrl_controls[i]; + if (!res->class) + continue; // dummy resource + + dom =3D mpam_resctrl_get_domain_from_cpu(cpu, res); + if (WARN_ON_ONCE(!dom)) + continue; + + ctrl_dom_empty =3D true; + if (exposed_alloc_capable) { + ctrl_d =3D &dom->resctrl_ctrl_dom; + ctrl_dom_empty =3D mpam_resctrl_offline_domain_hdr(cpu, &ctrl_d->hdr); + if (ctrl_dom_empty) + resctrl_offline_ctrl_domain(&res->resctrl_res, ctrl_d); + } + + mon_dom_empty =3D true; + if (exposed_mon_capable) { + mon_d =3D &dom->resctrl_mon_dom; + mon_dom_empty =3D mpam_resctrl_offline_domain_hdr(cpu, &mon_d->hdr); + if (mon_dom_empty) + resctrl_offline_mon_domain(&res->resctrl_res, mon_d); + } + + if (ctrl_dom_empty && mon_dom_empty) + kfree(dom); + } +} + +int mpam_resctrl_setup(void) +{ + int err =3D 0; + enum resctrl_res_level i; + struct mpam_resctrl_res *res; + + cpus_read_lock(); + for (i =3D 0; i < RDT_NUM_RESOURCES; i++) { + res =3D &mpam_resctrl_controls[i]; + INIT_LIST_HEAD_RCU(&res->resctrl_res.ctrl_domains); + INIT_LIST_HEAD_RCU(&res->resctrl_res.mon_domains); + res->resctrl_res.rid =3D i; + } + + /* TODO: pick MPAM classes to map to resctrl resources */ + + /* Initialise the resctrl structures from the classes */ + for (i =3D 0; i < RDT_NUM_RESOURCES; i++) { + res =3D &mpam_resctrl_controls[i]; + if (!res->class) + continue; // dummy resource + + err =3D mpam_resctrl_control_init(res, i); + if (err) { + pr_debug("Failed to initialise rid %u\n", i); + break; + } + } + cpus_read_unlock(); + + if (err || (!exposed_alloc_capable && !exposed_mon_capable)) { + if (err) + pr_debug("Internal error %d - resctrl not supported\n", + err); + else + pr_debug("No alloc(%u) or monitor(%u) found - resctrl not supported\n", + exposed_alloc_capable, exposed_mon_capable); + err =3D -EOPNOTSUPP; + } + + if (!err) { + if (!is_power_of_2(mpam_pmg_max + 1)) { + /* + * If not all the partid*pmg values are valid indexes, + * resctrl may allocate pmg that don't exist. This + * should cause an error interrupt. + */ + pr_warn("Number of PMG is not a power of 2! resctrl may misbehave"); + } + + /* TODO: call resctrl_init() */ + } + + return err; +} diff --git a/include/linux/arm_mpam.h b/include/linux/arm_mpam.h index 7f00c5285a32..2c7d1413a401 100644 --- a/include/linux/arm_mpam.h +++ b/include/linux/arm_mpam.h @@ -49,6 +49,9 @@ static inline int mpam_ris_create(struct mpam_msc *msc, u= 8 ris_idx, } #endif =20 +bool resctrl_arch_alloc_capable(void); +bool resctrl_arch_mon_capable(void); + /** * mpam_register_requestor() - Register a requestor with the MPAM driver * @partid_max: The maximum PARTID value the requestor can generate. --=20 2.39.5 From nobody Tue Dec 16 07:34:20 2025 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 6987D2C027E for ; Fri, 5 Dec 2025 22:00:01 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764972003; cv=none; b=A01QFFag4dOChb7vQEBpw4/UvAFdghMYzTVnIZsPXU2nt9OSErQ2Ip5f9IblsOG/1sD396uci/G0Wl3tlD+97Vsb+Kncd+iNgIJ8ljp/iK3hFefFMWMaoNbX42phrFpIH9fgTDObrGuQOnBKYZiDWM9lAlBA7mwrWaQ7F1JkUr0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764972003; c=relaxed/simple; bh=qm8+UwX2jA5MZOITS+pgjttD9SxH5N1pC27W5xgvxYY=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=VnIYFGB9lSVKbaZdM/gUuXOJWXY+wtedJfEyHhej9OOdysFK8pzLIKBsc9wXZqsPLlUhn5tK/INHd9PWws+jl4nEObm7L70wzIAqlLXFsrgMWTf641PJ5gbh+IKBb/lgMNjUeN38fazvt7efXBJOf5s9hU2mSDjhzmY0mQ+bC4s= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 5C9CA1A25; Fri, 5 Dec 2025 13:59:53 -0800 (PST) Received: from merodach.members.linode.com (usa-sjc-mx-foss1.foss.arm.com [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id F299A3F740; Fri, 5 Dec 2025 13:59:56 -0800 (PST) From: James Morse To: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: James Morse , D Scott Phillips OS , carl@os.amperecomputing.com, lcherian@marvell.com, bobo.shaobowang@huawei.com, tan.shaopeng@fujitsu.com, baolin.wang@linux.alibaba.com, Jamie Iles , Xin Hao , peternewman@google.com, dfustini@baylibre.com, amitsinght@marvell.com, David Hildenbrand , Dave Martin , Koba Ko , Shanker Donthineni , fenghuay@nvidia.com, baisheng.gao@unisoc.com, Jonathan Cameron , Gavin Shan , Ben Horgan , rohit.mathew@arm.com, reinette.chatre@intel.com, Punit Agrawal Subject: [RFC PATCH 08/38] arm_mpam: resctrl: Pick the caches we will use as resctrl resources Date: Fri, 5 Dec 2025 21:58:31 +0000 Message-Id: <20251205215901.17772-9-james.morse@arm.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20251205215901.17772-1-james.morse@arm.com> References: <20251205215901.17772-1-james.morse@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Systems with MPAM support may have a variety of control types at any point of their system layout. We can only expose certain types of control, and only if they exist at particular locations. Start with the well-know caches. These have to be depth 2 or 3 and support MPAM's cache portion bitmap controls, with a number of portions fewer than resctrl's limit. Signed-off-by: James Morse --- drivers/resctrl/mpam_resctrl.c | 91 +++++++++++++++++++++++++++++++++- 1 file changed, 89 insertions(+), 2 deletions(-) diff --git a/drivers/resctrl/mpam_resctrl.c b/drivers/resctrl/mpam_resctrl.c index 320cebbd37ce..ceaf11af4fc1 100644 --- a/drivers/resctrl/mpam_resctrl.c +++ b/drivers/resctrl/mpam_resctrl.c @@ -60,10 +60,96 @@ struct rdt_resource *resctrl_arch_get_resource(enum res= ctrl_res_level l) return &mpam_resctrl_controls[l].resctrl_res; } =20 +static bool cache_has_usable_cpor(struct mpam_class *class) +{ + struct mpam_props *cprops =3D &class->props; + + if (!mpam_has_feature(mpam_feat_cpor_part, cprops)) + return false; + + /* resctrl uses u32 for all bitmap configurations */ + return (class->props.cpbm_wd <=3D 32); +} + +/* Test whether we can export MPAM_CLASS_CACHE:{2,3}? */ +static void mpam_resctrl_pick_caches(void) +{ + struct mpam_class *class; + struct mpam_resctrl_res *res; + + lockdep_assert_cpus_held(); + + guard(srcu)(&mpam_srcu); + list_for_each_entry_srcu(class, &mpam_classes, classes_list, + srcu_read_lock_held(&mpam_srcu)) { + if (class->type !=3D MPAM_CLASS_CACHE) { + pr_debug("class %u is not a cache\n", class->level); + continue; + } + + if (class->level !=3D 2 && class->level !=3D 3) { + pr_debug("class %u is not L2 or L3\n", class->level); + continue; + } + + if (!cache_has_usable_cpor(class)) { + pr_debug("class %u cache misses CPOR\n", class->level); + continue; + } + + if (!cpumask_equal(&class->affinity, cpu_possible_mask)) { + pr_debug("class %u has missing CPUs\n", class->level); + pr_debug("class %u mask %*pb !=3D %*pb\n", class->level, + cpumask_pr_args(&class->affinity), + cpumask_pr_args(cpu_possible_mask)); + continue; + } + + if (class->level =3D=3D 2) + res =3D &mpam_resctrl_controls[RDT_RESOURCE_L2]; + else + res =3D &mpam_resctrl_controls[RDT_RESOURCE_L3]; + res->class =3D class; + exposed_alloc_capable =3D true; + } +} + static int mpam_resctrl_control_init(struct mpam_resctrl_res *res, enum resctrl_res_level type) { - /* TODO: initialise the resctrl resources */ + struct mpam_class *class =3D res->class; + struct rdt_resource *r =3D &res->resctrl_res; + + switch (res->resctrl_res.rid) { + case RDT_RESOURCE_L2: + case RDT_RESOURCE_L3: + r->alloc_capable =3D true; + r->schema_fmt =3D RESCTRL_SCHEMA_BITMAP; + r->cache.arch_has_sparse_bitmasks =3D true; + + r->cache.cbm_len =3D class->props.cpbm_wd; + /* mpam_devices will reject empty bitmaps */ + r->cache.min_cbm_bits =3D 1; + + if (r->rid =3D=3D RDT_RESOURCE_L2) { + r->name =3D "L2"; + r->ctrl_scope =3D RESCTRL_L2_CACHE; + } else { + r->name =3D "L3"; + r->ctrl_scope =3D RESCTRL_L3_CACHE; + } + + /* + * Which bits are shared with other ...things... + * Unknown devices use partid-0 which uses all the bitmap + * fields. Until we configured the SMMU and GIC not to do this + * 'all the bits' is the correct answer here. + */ + r->cache.shareable_bits =3D resctrl_get_default_ctrl(r); + break; + default: + break; + } =20 return 0; } @@ -286,7 +372,8 @@ int mpam_resctrl_setup(void) res->resctrl_res.rid =3D i; } =20 - /* TODO: pick MPAM classes to map to resctrl resources */ + /* Find some classes to use for controls */ + mpam_resctrl_pick_caches(); =20 /* Initialise the resctrl structures from the classes */ for (i =3D 0; i < RDT_NUM_RESOURCES; i++) { --=20 2.39.5 From nobody Tue Dec 16 07:34:20 2025 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 89A0C273D84 for ; Fri, 5 Dec 2025 22:00:05 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764972008; cv=none; b=oNT90cyLei+Mk22ETlmbUtaibHdNAHUGUprPNuCE0JqtWmOhgsXCw8qJ4eY/yRTVS12/jE+bQVeLT1G7OkyIDQncw8Gc/IOH8J/oVc6XdRxajrTIgm0vkZl0wAAnZktO5OoiosfK1dLlzsA9wuocQsoVfVZgyhWJRf3sI7+1c6Q= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764972008; c=relaxed/simple; bh=r7lfPkMofMVVMx0hNcPc0ncL5ZU2iXGg2D/NL0lwA0A=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=I8Hn9SkiLhgwyBMjtNOWmx+xYmIosfSymR8mB7kCAf7ppW7HxtBZqnETO9Hiv6tLUMq5MVMcBAkBSHjfvrMtriZz2ibLle+MDaPLID/oA4QqMht9h0s7Wi79fcwBvDf6mFvinD0PyEJQqYB7xaNDxnfeHMVL19OJbFZ5drZRHJc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 75CB61BA8; Fri, 5 Dec 2025 13:59:57 -0800 (PST) Received: from merodach.members.linode.com (usa-sjc-mx-foss1.foss.arm.com [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 072763F740; Fri, 5 Dec 2025 14:00:00 -0800 (PST) From: James Morse To: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: James Morse , D Scott Phillips OS , carl@os.amperecomputing.com, lcherian@marvell.com, bobo.shaobowang@huawei.com, tan.shaopeng@fujitsu.com, baolin.wang@linux.alibaba.com, Jamie Iles , Xin Hao , peternewman@google.com, dfustini@baylibre.com, amitsinght@marvell.com, David Hildenbrand , Dave Martin , Koba Ko , Shanker Donthineni , fenghuay@nvidia.com, baisheng.gao@unisoc.com, Jonathan Cameron , Gavin Shan , Ben Horgan , rohit.mathew@arm.com, reinette.chatre@intel.com, Punit Agrawal Subject: [RFC PATCH 09/38] arm_mpam: resctrl: Implement resctrl_arch_reset_all_ctrls() Date: Fri, 5 Dec 2025 21:58:32 +0000 Message-Id: <20251205215901.17772-10-james.morse@arm.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20251205215901.17772-1-james.morse@arm.com> References: <20251205215901.17772-1-james.morse@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" We already have a helper for resetting an mpam class and component. Hook it up to resctrl_arch_reset_all_ctrls() and the domain offline path. Signed-off-by: James Morse --- drivers/resctrl/mpam_devices.c | 6 +++--- drivers/resctrl/mpam_internal.h | 7 +++++++ drivers/resctrl/mpam_resctrl.c | 15 +++++++++++++++ 3 files changed, 25 insertions(+), 3 deletions(-) diff --git a/drivers/resctrl/mpam_devices.c b/drivers/resctrl/mpam_devices.c index efaf7633bc35..fccebfd980d8 100644 --- a/drivers/resctrl/mpam_devices.c +++ b/drivers/resctrl/mpam_devices.c @@ -2543,7 +2543,7 @@ static void mpam_enable_once(void) mpam_partid_max + 1, mpam_pmg_max + 1); } =20 -static void mpam_reset_component_locked(struct mpam_component *comp) +void mpam_reset_component_locked(struct mpam_component *comp) { struct mpam_vmsc *vmsc; =20 @@ -2567,7 +2567,7 @@ static void mpam_reset_component_locked(struct mpam_c= omponent *comp) } } =20 -static void mpam_reset_class_locked(struct mpam_class *class) +void mpam_reset_class_locked(struct mpam_class *class) { struct mpam_component *comp; =20 @@ -2579,7 +2579,7 @@ static void mpam_reset_class_locked(struct mpam_class= *class) mpam_reset_component_locked(comp); } =20 -static void mpam_reset_class(struct mpam_class *class) +void mpam_reset_class(struct mpam_class *class) { cpus_read_lock(); mpam_reset_class_locked(class); diff --git a/drivers/resctrl/mpam_internal.h b/drivers/resctrl/mpam_interna= l.h index dfd3512ac924..8684bd35d4ab 100644 --- a/drivers/resctrl/mpam_internal.h +++ b/drivers/resctrl/mpam_internal.h @@ -392,6 +392,13 @@ extern u8 mpam_pmg_max; void mpam_enable(struct work_struct *work); void mpam_disable(struct work_struct *work); =20 +/* Reset all the RIS in a class, optionally while holding cpus_read_lock()= */ +void mpam_reset_class_locked(struct mpam_class *class); +void mpam_reset_class(struct mpam_class *class); + +/* Reset all the RIS in a component under cpus_read_lock() */ +void mpam_reset_component_locked(struct mpam_component *comp); + int mpam_apply_config(struct mpam_component *comp, u16 partid, struct mpam_config *cfg); =20 diff --git a/drivers/resctrl/mpam_resctrl.c b/drivers/resctrl/mpam_resctrl.c index ceaf11af4fc1..a2deea1f4818 100644 --- a/drivers/resctrl/mpam_resctrl.c +++ b/drivers/resctrl/mpam_resctrl.c @@ -168,6 +168,19 @@ static int mpam_resctrl_pick_domain_id(int cpu, struct= mpam_component *comp) return comp->comp_id; } =20 +void resctrl_arch_reset_all_ctrls(struct rdt_resource *r) +{ + struct mpam_resctrl_res *res; + + lockdep_assert_cpus_held(); + + if (!mpam_is_enabled()) + return; + + res =3D container_of(r, struct mpam_resctrl_res, resctrl_res); + mpam_reset_class_locked(res->class); +} + static void mpam_resctrl_domain_hdr_init(int cpu, struct mpam_component *c= omp, struct rdt_domain_hdr *hdr) { @@ -339,6 +352,8 @@ void mpam_resctrl_offline_cpu(unsigned int cpu) =20 ctrl_dom_empty =3D true; if (exposed_alloc_capable) { + mpam_reset_component_locked(dom->ctrl_comp); + ctrl_d =3D &dom->resctrl_ctrl_dom; ctrl_dom_empty =3D mpam_resctrl_offline_domain_hdr(cpu, &ctrl_d->hdr); if (ctrl_dom_empty) --=20 2.39.5 From nobody Tue Dec 16 07:34:20 2025 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id D440F2D877B for ; Fri, 5 Dec 2025 22:00:09 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; 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Fri, 5 Dec 2025 14:00:01 -0800 (PST) Received: from merodach.members.linode.com (usa-sjc-mx-foss1.foss.arm.com [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 0B99B3F740; Fri, 5 Dec 2025 14:00:04 -0800 (PST) From: James Morse To: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: James Morse , D Scott Phillips OS , carl@os.amperecomputing.com, lcherian@marvell.com, bobo.shaobowang@huawei.com, tan.shaopeng@fujitsu.com, baolin.wang@linux.alibaba.com, Jamie Iles , Xin Hao , peternewman@google.com, dfustini@baylibre.com, amitsinght@marvell.com, David Hildenbrand , Dave Martin , Koba Ko , Shanker Donthineni , fenghuay@nvidia.com, baisheng.gao@unisoc.com, Jonathan Cameron , Gavin Shan , Ben Horgan , rohit.mathew@arm.com, reinette.chatre@intel.com, Punit Agrawal Subject: [RFC PATCH 10/38] arm_mpam: resctrl: Add resctrl_arch_get_config() Date: Fri, 5 Dec 2025 21:58:33 +0000 Message-Id: <20251205215901.17772-11-james.morse@arm.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20251205215901.17772-1-james.morse@arm.com> References: <20251205215901.17772-1-james.morse@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Implement resctrl_arch_get_config() by testing the live configuration for a CPOR bitmap. For any other configuration type return the default. Signed-off-by: James Morse --- drivers/resctrl/mpam_resctrl.c | 43 ++++++++++++++++++++++++++++++++++ 1 file changed, 43 insertions(+) diff --git a/drivers/resctrl/mpam_resctrl.c b/drivers/resctrl/mpam_resctrl.c index a2deea1f4818..a26eb1f3efd0 100644 --- a/drivers/resctrl/mpam_resctrl.c +++ b/drivers/resctrl/mpam_resctrl.c @@ -168,6 +168,49 @@ static int mpam_resctrl_pick_domain_id(int cpu, struct= mpam_component *comp) return comp->comp_id; } =20 +u32 resctrl_arch_get_config(struct rdt_resource *r, struct rdt_ctrl_domain= *d, + u32 closid, enum resctrl_conf_type type) +{ + u32 partid; + struct mpam_config *cfg; + struct mpam_props *cprops; + struct mpam_resctrl_res *res; + struct mpam_resctrl_dom *dom; + enum mpam_device_features configured_by; + + lockdep_assert_cpus_held(); + + if (!mpam_is_enabled()) + return resctrl_get_default_ctrl(r); + + res =3D container_of(r, struct mpam_resctrl_res, resctrl_res); + dom =3D container_of(d, struct mpam_resctrl_dom, resctrl_ctrl_dom); + cprops =3D &res->class->props; + + partid =3D resctrl_get_config_index(closid, type); + cfg =3D &dom->ctrl_comp->cfg[partid]; + + switch (r->rid) { + case RDT_RESOURCE_L2: + case RDT_RESOURCE_L3: + configured_by =3D mpam_feat_cpor_part; + break; + default: + return resctrl_get_default_ctrl(r); + } + + if (!r->alloc_capable || partid >=3D resctrl_arch_get_num_closid(r) || + !mpam_has_feature(configured_by, cfg)) + return resctrl_get_default_ctrl(r); + + switch (configured_by) { + case mpam_feat_cpor_part: + return cfg->cpbm; + default: + return resctrl_get_default_ctrl(r); + } +} + void resctrl_arch_reset_all_ctrls(struct rdt_resource *r) { struct mpam_resctrl_res *res; --=20 2.39.5 From nobody Tue Dec 16 07:34:20 2025 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 1E9B92D8DA8 for ; Fri, 5 Dec 2025 22:00:13 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764972015; cv=none; b=nxvvZB5ZBg8v6Ii7XRSQjFzbNoJD5f2RKRAKQtWFickj7D4F/ZdRo9wnDaM+Gf6DQ9pu/g+QHWyoouhmqr83eq/JBBuMVdlQDlfGP7eWMYaEURiqT+kTdZSILz8rG4KxHmFWIiYwYYCy+URPmbO+zFQgpdjQA7Z6pbNqyJdywzM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764972015; c=relaxed/simple; bh=6SKJPO9cs1AJbLDdgtXloQY17zKQihYuyLIoNFvDbJA=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=Pg4mR9sajdndaEMw1k8HEqD2GKALFfoDGg4p3k9JoZ1BVzLj6jYyQ1lhllc+qvrsdOmyHURXC48yz1608U1XcJPRI6vFkC1KjcsmCz1h8bhOoDBN/TviFBaKzuPioWtIlAqRBZmPEIKQLaa6Iy6nd+G/1NHvuToszvUkMFRLUjI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 85CE01A25; Fri, 5 Dec 2025 14:00:05 -0800 (PST) Received: from merodach.members.linode.com (usa-sjc-mx-foss1.foss.arm.com [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 1DC9B3F740; Fri, 5 Dec 2025 14:00:08 -0800 (PST) From: James Morse To: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: James Morse , D Scott Phillips OS , carl@os.amperecomputing.com, lcherian@marvell.com, bobo.shaobowang@huawei.com, tan.shaopeng@fujitsu.com, baolin.wang@linux.alibaba.com, Jamie Iles , Xin Hao , peternewman@google.com, dfustini@baylibre.com, amitsinght@marvell.com, David Hildenbrand , Dave Martin , Koba Ko , Shanker Donthineni , fenghuay@nvidia.com, baisheng.gao@unisoc.com, Jonathan Cameron , Gavin Shan , Ben Horgan , rohit.mathew@arm.com, reinette.chatre@intel.com, Punit Agrawal Subject: [RFC PATCH 11/38] arm_mpam: resctrl: Implement helpers to update configuration Date: Fri, 5 Dec 2025 21:58:34 +0000 Message-Id: <20251205215901.17772-12-james.morse@arm.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20251205215901.17772-1-james.morse@arm.com> References: <20251205215901.17772-1-james.morse@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" resctrl has two helpers for updating the configuration. resctrl_arch_update_one() updates a single value, and is used by the software-controller to apply feedback to the bandwidth controls, it has to be called on one of the CPUs in the resctrl:domain. resctrl_arch_update_domains() copies multiple staged configurations, it can be called from anywhere. Both helpers should update any changes to the underlying hardware. Imlpement resctrl_arch_update_domains() to use resctrl_arch_update_one(). Neither need to be called on a specific CPU as the mpam driver will send IPIs as needed. Signed-off-by: James Morse --- drivers/resctrl/mpam_resctrl.c | 71 ++++++++++++++++++++++++++++++++++ 1 file changed, 71 insertions(+) diff --git a/drivers/resctrl/mpam_resctrl.c b/drivers/resctrl/mpam_resctrl.c index a26eb1f3efd0..ae0d17857b78 100644 --- a/drivers/resctrl/mpam_resctrl.c +++ b/drivers/resctrl/mpam_resctrl.c @@ -211,6 +211,77 @@ u32 resctrl_arch_get_config(struct rdt_resource *r, st= ruct rdt_ctrl_domain *d, } } =20 +int resctrl_arch_update_one(struct rdt_resource *r, struct rdt_ctrl_domain= *d, + u32 closid, enum resctrl_conf_type t, u32 cfg_val) +{ + u32 partid; + struct mpam_config cfg; + struct mpam_props *cprops; + struct mpam_resctrl_res *res; + struct mpam_resctrl_dom *dom; + + lockdep_assert_cpus_held(); + lockdep_assert_irqs_enabled(); + + /* + * No need to check the CPU as mpam_apply_config() doesn't care, and + * resctrl_arch_update_domains() relies on this. + */ + res =3D container_of(r, struct mpam_resctrl_res, resctrl_res); + dom =3D container_of(d, struct mpam_resctrl_dom, resctrl_ctrl_dom); + cprops =3D &res->class->props; + + partid =3D resctrl_get_config_index(closid, t); + if (!r->alloc_capable || partid >=3D resctrl_arch_get_num_closid(r)) { + pr_debug("Not alloc capable or computed PARTID out of range\n"); + return -EINVAL; + } + + /* + * Copy the current config to avoid clearing other resources when the + * same component is exposed multiple times through resctrl. + */ + cfg =3D dom->ctrl_comp->cfg[partid]; + + switch (r->rid) { + case RDT_RESOURCE_L2: + case RDT_RESOURCE_L3: + cfg.cpbm =3D cfg_val; + mpam_set_feature(mpam_feat_cpor_part, &cfg); + break; + default: + return -EINVAL; + } + + return mpam_apply_config(dom->ctrl_comp, partid, &cfg); +} + +int resctrl_arch_update_domains(struct rdt_resource *r, u32 closid) +{ + int err =3D 0; + enum resctrl_conf_type t; + struct rdt_ctrl_domain *d; + struct resctrl_staged_config *cfg; + + lockdep_assert_cpus_held(); + lockdep_assert_irqs_enabled(); + + list_for_each_entry(d, &r->ctrl_domains, hdr.list) { + for (t =3D 0; t < CDP_NUM_TYPES; t++) { + cfg =3D &d->staged_config[t]; + if (!cfg->have_new_ctrl) + continue; + + err =3D resctrl_arch_update_one(r, d, closid, t, + cfg->new_ctrl); + if (err) + return err; + } + } + + return err; +} + void resctrl_arch_reset_all_ctrls(struct rdt_resource *r) { struct mpam_resctrl_res *res; --=20 2.39.5 From nobody Tue Dec 16 07:34:20 2025 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id C802E2D8764 for ; Fri, 5 Dec 2025 22:00:17 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764972022; cv=none; b=I0sa9Prz0iWhGB5HMqujmNZBi7duaVM5a8lOsHTSiAbKB27NmmdQaiUW5K+QDzLUUWB32KQXNXDPkxvVyy5ikbBT5NXXiN2CoXXvXub/lenpE2X/dAaer6CQuEX6FHN2FKVBl03FkpDgfur8xzQNNie31gB1U1ZcG3N7/GlEpco= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764972022; c=relaxed/simple; bh=QPAl3fcRhJEsk1p8oTbsHIP9oNlT3M3a2ka0zfkvjMI=; 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charset="utf-8" arm64 provides helpers for changing a tasks and a cpus mpam partid/pmg values. These are used to back a number of resctrl_arch_ functions. Connect them up. Signed-off-by: James Morse --- drivers/resctrl/mpam_resctrl.c | 58 ++++++++++++++++++++++++++++++++++ include/linux/arm_mpam.h | 5 +++ 2 files changed, 63 insertions(+) diff --git a/drivers/resctrl/mpam_resctrl.c b/drivers/resctrl/mpam_resctrl.c index ae0d17857b78..c2650abb99ec 100644 --- a/drivers/resctrl/mpam_resctrl.c +++ b/drivers/resctrl/mpam_resctrl.c @@ -8,6 +8,7 @@ #include #include #include +#include #include #include #include @@ -32,6 +33,8 @@ static DEFINE_MUTEX(domain_list_lock); static bool exposed_alloc_capable; static bool exposed_mon_capable; =20 +static bool cdp_enabled; + bool resctrl_arch_alloc_capable(void) { return exposed_alloc_capable; @@ -52,6 +55,61 @@ u32 resctrl_arch_get_num_closid(struct rdt_resource *ign= ored) return mpam_partid_max + 1; } =20 +void resctrl_arch_sched_in(struct task_struct *tsk) +{ + lockdep_assert_preemption_disabled(); + + mpam_thread_switch(tsk); +} + +void resctrl_arch_set_cpu_default_closid_rmid(int cpu, u32 closid, u32 rmi= d) +{ + WARN_ON_ONCE(closid > U16_MAX); + WARN_ON_ONCE(rmid > U8_MAX); + + if (!cdp_enabled) { + mpam_set_cpu_defaults(cpu, closid, closid, rmid, rmid); + } else { + /* + * When CDP is enabled, resctrl halves the closid range and we + * use odd/even partid for one closid. + */ + u32 partid_d =3D resctrl_get_config_index(closid, CDP_DATA); + u32 partid_i =3D resctrl_get_config_index(closid, CDP_CODE); + + mpam_set_cpu_defaults(cpu, partid_d, partid_i, rmid, rmid); + } +} + +void resctrl_arch_sync_cpu_closid_rmid(void *info) +{ + struct resctrl_cpu_defaults *r =3D info; + + lockdep_assert_preemption_disabled(); + + if (r) { + resctrl_arch_set_cpu_default_closid_rmid(smp_processor_id(), + r->closid, r->rmid); + } + + resctrl_arch_sched_in(current); +} + +void resctrl_arch_set_closid_rmid(struct task_struct *tsk, u32 closid, u32= rmid) +{ + WARN_ON_ONCE(closid > U16_MAX); + WARN_ON_ONCE(rmid > U8_MAX); + + if (!cdp_enabled) { + mpam_set_task_partid_pmg(tsk, closid, closid, rmid, rmid); + } else { + u32 partid_d =3D resctrl_get_config_index(closid, CDP_DATA); + u32 partid_i =3D resctrl_get_config_index(closid, CDP_CODE); + + mpam_set_task_partid_pmg(tsk, partid_d, partid_i, rmid, rmid); + } +} + struct rdt_resource *resctrl_arch_get_resource(enum resctrl_res_level l) { if (l >=3D RDT_NUM_RESOURCES) diff --git a/include/linux/arm_mpam.h b/include/linux/arm_mpam.h index 2c7d1413a401..5a78299ec464 100644 --- a/include/linux/arm_mpam.h +++ b/include/linux/arm_mpam.h @@ -52,6 +52,11 @@ static inline int mpam_ris_create(struct mpam_msc *msc, = u8 ris_idx, bool resctrl_arch_alloc_capable(void); bool resctrl_arch_mon_capable(void); =20 +void resctrl_arch_set_cpu_default_closid(int cpu, u32 closid); +void resctrl_arch_set_closid_rmid(struct task_struct *tsk, u32 closid, u32= rmid); +void resctrl_arch_set_cpu_default_closid_rmid(int cpu, u32 closid, u32 rmi= d); +void resctrl_arch_sched_in(struct task_struct *tsk); + /** * mpam_register_requestor() - Register a requestor with the MPAM driver * @partid_max: The maximum PARTID value the requestor can generate. --=20 2.39.5 From nobody Tue Dec 16 07:34:20 2025 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 3EFFE2D9494 for ; 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dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id CCA5E1BA8; Fri, 5 Dec 2025 14:00:13 -0800 (PST) Received: from merodach.members.linode.com (usa-sjc-mx-foss1.foss.arm.com [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 347833F7BD; Fri, 5 Dec 2025 14:00:17 -0800 (PST) From: James Morse To: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: James Morse , D Scott Phillips OS , carl@os.amperecomputing.com, lcherian@marvell.com, bobo.shaobowang@huawei.com, tan.shaopeng@fujitsu.com, baolin.wang@linux.alibaba.com, Jamie Iles , Xin Hao , peternewman@google.com, dfustini@baylibre.com, amitsinght@marvell.com, David Hildenbrand , Dave Martin , Koba Ko , Shanker Donthineni , fenghuay@nvidia.com, baisheng.gao@unisoc.com, Jonathan Cameron , Gavin Shan , Ben Horgan , rohit.mathew@arm.com, reinette.chatre@intel.com, Punit Agrawal , Dave Martin Subject: [RFC PATCH 13/38] arm_mpam: resctrl: Add CDP emulation Date: Fri, 5 Dec 2025 21:58:36 +0000 Message-Id: <20251205215901.17772-14-james.morse@arm.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20251205215901.17772-1-james.morse@arm.com> References: <20251205215901.17772-1-james.morse@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Intel RDT's CDP feature allows the cache to use a different control value depending on whether the accesses was for instruction fetch or a data access. MPAM's equivalent feature is the other way up: the CPU assigns a different partid label to traffic depending on whether it was instruction fetch or a data access, which causes the cache to use a different control value based solely on the partid. MPAM can emulate CDP, with the side effect that the alternative partid is seen by all MSC, it can't be enabled per-MSC. Add the resctrl hooks to turn this on or off. Add the helpers that match a closid against a task, which need to be aware that the value written to hardware is not the same as the one resctrl is using. Update the 'arm64_mpam_global_default' variable the arch code uses during context switch to know when the per-cpu value should be used instead. Awkwardly, the MB controls don't implement CDP. To emulate this, the MPAM equivalent needs programming twice by the resctrl glue, as resctrl expects the bandwidth controls to be applied independently for both data and isntruction-fetch. CC: Dave Martin CC: Ben Horgan CC: Amit Singh Tomar Signed-off-by: James Morse --- arch/arm64/include/asm/mpam.h | 1 + drivers/resctrl/mpam_resctrl.c | 115 ++++++++++++++++++++++++++++++++- include/linux/arm_mpam.h | 3 + 3 files changed, 118 insertions(+), 1 deletion(-) diff --git a/arch/arm64/include/asm/mpam.h b/arch/arm64/include/asm/mpam.h index 2960ffaf6574..689285c4c61f 100644 --- a/arch/arm64/include/asm/mpam.h +++ b/arch/arm64/include/asm/mpam.h @@ -4,6 +4,7 @@ #ifndef __ASM__MPAM_H #define __ASM__MPAM_H =20 +#include #include #include #include diff --git a/drivers/resctrl/mpam_resctrl.c b/drivers/resctrl/mpam_resctrl.c index c2650abb99ec..d5f75ed67e46 100644 --- a/drivers/resctrl/mpam_resctrl.c +++ b/drivers/resctrl/mpam_resctrl.c @@ -33,6 +33,10 @@ static DEFINE_MUTEX(domain_list_lock); static bool exposed_alloc_capable; static bool exposed_mon_capable; =20 +/* + * MPAM emulates CDP by setting different PARTID in the I/D fields of MPAM= 0_EL1. + * This applies globally to all traffic the CPU generates. + */ static bool cdp_enabled; =20 bool resctrl_arch_alloc_capable(void) @@ -45,6 +49,67 @@ bool resctrl_arch_mon_capable(void) return exposed_mon_capable; } =20 +bool resctrl_arch_get_cdp_enabled(enum resctrl_res_level rid) +{ + switch (rid) { + case RDT_RESOURCE_L2: + case RDT_RESOURCE_L3: + return cdp_enabled; + case RDT_RESOURCE_MBA: + default: + /* + * x86's MBA control doesn't support CDP, so user-space doesn't + * expect it. + */ + return false; + } +} + +/** + * resctrl_reset_task_closids() - Reset the PARTID/PMG values for all task= s. + * + * At boot, all existing tasks use partid zero for D and I. + * To enable/disable CDP emulation, all these tasks need relabelling. + */ +static void resctrl_reset_task_closids(void) +{ + struct task_struct *p, *t; + + read_lock(&tasklist_lock); + for_each_process_thread(p, t) { + resctrl_arch_set_closid_rmid(t, RESCTRL_RESERVED_CLOSID, + RESCTRL_RESERVED_RMID); + } + read_unlock(&tasklist_lock); +} + +int resctrl_arch_set_cdp_enabled(enum resctrl_res_level ignored, bool enab= le) +{ + u32 partid_i, partid_d; + + cdp_enabled =3D enable; + partid_i =3D partid_d =3D RESCTRL_RESERVED_CLOSID; + + if (enable) { + u32 partid =3D RESCTRL_RESERVED_CLOSID; + + partid_d =3D resctrl_get_config_index(partid, CDP_CODE); + partid_i =3D resctrl_get_config_index(partid, CDP_DATA); + } + + mpam_set_task_partid_pmg(current, partid_d, partid_i, 0, 0); + WRITE_ONCE(arm64_mpam_global_default, mpam_get_regval(current)); + + resctrl_reset_task_closids(); + + return 0; +} + +static bool mpam_resctrl_hide_cdp(enum resctrl_res_level rid) +{ + return cdp_enabled && !resctrl_arch_get_cdp_enabled(rid); +} + /* * MSC may raise an error interrupt if it sees an out or range partid/pmg, * and go on to truncate the value. Regardless of what the hardware suppor= ts, @@ -110,6 +175,30 @@ void resctrl_arch_set_closid_rmid(struct task_struct *= tsk, u32 closid, u32 rmid) } } =20 +bool resctrl_arch_match_closid(struct task_struct *tsk, u32 closid) +{ + u64 regval =3D mpam_get_regval(tsk); + u32 tsk_closid =3D FIELD_GET(MPAM0_EL1_PARTID_D, regval); + + if (cdp_enabled) + tsk_closid >>=3D 1; + + return tsk_closid =3D=3D closid; +} + +/* The task's pmg is not unique, the partid must be considered too */ +bool resctrl_arch_match_rmid(struct task_struct *tsk, u32 closid, u32 rmid) +{ + u64 regval =3D mpam_get_regval(tsk); + u32 tsk_closid =3D FIELD_GET(MPAM0_EL1_PARTID_D, regval); + u32 tsk_rmid =3D FIELD_GET(MPAM0_EL1_PMG_D, regval); + + if (cdp_enabled) + tsk_closid >>=3D 1; + + return (tsk_closid =3D=3D closid) && (tsk_rmid =3D=3D rmid); +} + struct rdt_resource *resctrl_arch_get_resource(enum resctrl_res_level l) { if (l >=3D RDT_NUM_RESOURCES) @@ -245,6 +334,14 @@ u32 resctrl_arch_get_config(struct rdt_resource *r, st= ruct rdt_ctrl_domain *d, dom =3D container_of(d, struct mpam_resctrl_dom, resctrl_ctrl_dom); cprops =3D &res->class->props; =20 + /* + * When CDP is enabled, but the resource doesn't support it, + * the control is cloned across both partids. + * Pick one at random to read: + */ + if (mpam_resctrl_hide_cdp(r->rid)) + type =3D CDP_DATA; + partid =3D resctrl_get_config_index(closid, type); cfg =3D &dom->ctrl_comp->cfg[partid]; =20 @@ -272,6 +369,7 @@ u32 resctrl_arch_get_config(struct rdt_resource *r, str= uct rdt_ctrl_domain *d, int resctrl_arch_update_one(struct rdt_resource *r, struct rdt_ctrl_domain= *d, u32 closid, enum resctrl_conf_type t, u32 cfg_val) { + int err; u32 partid; struct mpam_config cfg; struct mpam_props *cprops; @@ -311,7 +409,22 @@ int resctrl_arch_update_one(struct rdt_resource *r, st= ruct rdt_ctrl_domain *d, return -EINVAL; } =20 - return mpam_apply_config(dom->ctrl_comp, partid, &cfg); + /* + * When CDP is enabled, but the resource doesn't support it, we need to + * apply the same configuration to the other partid. + */ + if (mpam_resctrl_hide_cdp(r->rid)) { + partid =3D resctrl_get_config_index(closid, CDP_CODE); + err =3D mpam_apply_config(dom->ctrl_comp, partid, &cfg); + if (err) + return err; + + partid =3D resctrl_get_config_index(closid, CDP_DATA); + return mpam_apply_config(dom->ctrl_comp, partid, &cfg); + + } else { + return mpam_apply_config(dom->ctrl_comp, partid, &cfg); + } } =20 int resctrl_arch_update_domains(struct rdt_resource *r, u32 closid) diff --git a/include/linux/arm_mpam.h b/include/linux/arm_mpam.h index 5a78299ec464..ba0312b55d9f 100644 --- a/include/linux/arm_mpam.h +++ b/include/linux/arm_mpam.h @@ -5,6 +5,7 @@ #define __LINUX_ARM_MPAM_H =20 #include +#include #include =20 struct mpam_msc; @@ -56,6 +57,8 @@ void resctrl_arch_set_cpu_default_closid(int cpu, u32 clo= sid); void resctrl_arch_set_closid_rmid(struct task_struct *tsk, u32 closid, u32= rmid); void resctrl_arch_set_cpu_default_closid_rmid(int cpu, u32 closid, u32 rmi= d); void resctrl_arch_sched_in(struct task_struct *tsk); +bool resctrl_arch_match_closid(struct task_struct *tsk, u32 closid); +bool resctrl_arch_match_rmid(struct task_struct *tsk, u32 closid, u32 rmid= ); =20 /** * mpam_register_requestor() - Register a requestor with the MPAM driver --=20 2.39.5 From nobody Tue Dec 16 07:34:20 2025 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id CF3E12D8764 for ; Fri, 5 Dec 2025 22:00:25 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764972034; cv=none; b=MyTFEZ+8e2iPAhCl6PrZkR7DY6mxyV5hwwmgHCdU21MufQ9VeMhvP4UBNmUxSDxw+TydzWALGewaWRZnif7ENjopar0BjJCJg/RWkitZ1Q94yM1eSok7K7lAm3t3cOSPJ39GNEgxo0ZDyZxDt/R4G6lgnmvQ2NgMhGPtAy3DjeI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764972034; c=relaxed/simple; bh=Y36uoDk6T4dqX2I4zKbULgvLaYHJP5anK1wuFS3v+B4=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=ECqr5hz9e9xsoO6c6bLcAI+OF3ceHx033jarvXRe5cuz8Emm2fBHq1pGxOpBJe1iKn+I02ReEpUj7roFCh9om07UGXEJygJNFKtwtWCjBfVVEC5DnRjzHfRqmw62xWYfnPp+xuMJ8dcnyrhdreDq/NAHrD68MXi+w6F3F1RsCPo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id CFD2E1AED; Fri, 5 Dec 2025 14:00:17 -0800 (PST) Received: from merodach.members.linode.com (usa-sjc-mx-foss1.foss.arm.com [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 5DB043F740; Fri, 5 Dec 2025 14:00:21 -0800 (PST) From: James Morse To: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: James Morse , D Scott Phillips OS , carl@os.amperecomputing.com, lcherian@marvell.com, bobo.shaobowang@huawei.com, tan.shaopeng@fujitsu.com, baolin.wang@linux.alibaba.com, Jamie Iles , Xin Hao , peternewman@google.com, dfustini@baylibre.com, amitsinght@marvell.com, David Hildenbrand , Dave Martin , Koba Ko , Shanker Donthineni , fenghuay@nvidia.com, baisheng.gao@unisoc.com, Jonathan Cameron , Gavin Shan , Ben Horgan , rohit.mathew@arm.com, reinette.chatre@intel.com, Punit Agrawal Subject: [RFC PATCH 14/38] arm_mpam: resctrl: Add rmid index helpers Date: Fri, 5 Dec 2025 21:58:37 +0000 Message-Id: <20251205215901.17772-15-james.morse@arm.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20251205215901.17772-1-james.morse@arm.com> References: <20251205215901.17772-1-james.morse@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Because MPAM's pmg aren't identical to RDT's rmid, resctrl handles some data structures by index. This allows x86 to map indexes to RMID, and MPAM to map them to partid-and-pmg. Add the helpers to do this. Signed-off-by: James Morse --- drivers/resctrl/mpam_resctrl.c | 28 ++++++++++++++++++++++++++++ include/linux/arm_mpam.h | 3 +++ 2 files changed, 31 insertions(+) diff --git a/drivers/resctrl/mpam_resctrl.c b/drivers/resctrl/mpam_resctrl.c index d5f75ed67e46..19d70d00bbcc 100644 --- a/drivers/resctrl/mpam_resctrl.c +++ b/drivers/resctrl/mpam_resctrl.c @@ -120,6 +120,34 @@ u32 resctrl_arch_get_num_closid(struct rdt_resource *i= gnored) return mpam_partid_max + 1; } =20 +u32 resctrl_arch_system_num_rmid_idx(void) +{ + u8 closid_shift =3D fls(mpam_pmg_max); + u32 num_partid =3D resctrl_arch_get_num_closid(NULL); + + return num_partid << closid_shift; +} + +u32 resctrl_arch_rmid_idx_encode(u32 closid, u32 rmid) +{ + u8 closid_shift =3D fls(mpam_pmg_max); + + WARN_ON_ONCE(closid_shift > 8); + + return (closid << closid_shift) | rmid; +} + +void resctrl_arch_rmid_idx_decode(u32 idx, u32 *closid, u32 *rmid) +{ + u8 closid_shift =3D fls(mpam_pmg_max); + u32 pmg_mask =3D ~(~0 << closid_shift); + + WARN_ON_ONCE(closid_shift > 8); + + *closid =3D idx >> closid_shift; + *rmid =3D idx & pmg_mask; +} + void resctrl_arch_sched_in(struct task_struct *tsk) { lockdep_assert_preemption_disabled(); diff --git a/include/linux/arm_mpam.h b/include/linux/arm_mpam.h index ba0312b55d9f..385554ceb452 100644 --- a/include/linux/arm_mpam.h +++ b/include/linux/arm_mpam.h @@ -59,6 +59,9 @@ void resctrl_arch_set_cpu_default_closid_rmid(int cpu, u3= 2 closid, u32 rmid); void resctrl_arch_sched_in(struct task_struct *tsk); bool resctrl_arch_match_closid(struct task_struct *tsk, u32 closid); bool resctrl_arch_match_rmid(struct task_struct *tsk, u32 closid, u32 rmid= ); +u32 resctrl_arch_rmid_idx_encode(u32 closid, u32 rmid); +void resctrl_arch_rmid_idx_decode(u32 idx, u32 *closid, u32 *rmid); +u32 resctrl_arch_system_num_rmid_idx(void); =20 /** * mpam_register_requestor() - Register a requestor with the MPAM driver --=20 2.39.5 From nobody Tue Dec 16 07:34:20 2025 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id F108E1DF74F for ; Fri, 5 Dec 2025 22:00:29 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764972031; cv=none; b=KDqjgGLBXpnBWaP1xF1mybdRJ634DdBvgxuuLuISFH0H36yHqKIBLR3AdCtemYTAQeJV6TWI7fiDfGw8WTnligKUvpHI61K2PQKdfb1bixiHn8Z/30qJNnDoWzGsIecYHeYG2duAkC9po4R1vQSOUdwP2GxOKUIgURlbesTatUo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764972031; c=relaxed/simple; bh=jQshvI9xiZr2qK3YeIIdQKokz3rapwNNrTTpAd9ednE=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=QMzze5f3TOVPZahhTGlV0J9K8SOeaLhQRG1y/atayw/ivb+nlX8dTb2T25xL0EleIH2cfdOtDjXaOFxq/B1jwPEjQleC5KQo5CJzkMnL2IpcxrqTHOwrxSBLhiDzbsOjqjkOZBfmPaNjbC25oeZI0m1k/D50G5CoJxOuQ7gmUOc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id EA4541BB0; Fri, 5 Dec 2025 14:00:21 -0800 (PST) Received: from merodach.members.linode.com (usa-sjc-mx-foss1.foss.arm.com [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 667213F740; Fri, 5 Dec 2025 14:00:25 -0800 (PST) From: James Morse To: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: James Morse , D Scott Phillips OS , carl@os.amperecomputing.com, lcherian@marvell.com, bobo.shaobowang@huawei.com, tan.shaopeng@fujitsu.com, baolin.wang@linux.alibaba.com, Jamie Iles , Xin Hao , peternewman@google.com, dfustini@baylibre.com, amitsinght@marvell.com, David Hildenbrand , Dave Martin , Koba Ko , Shanker Donthineni , fenghuay@nvidia.com, baisheng.gao@unisoc.com, Jonathan Cameron , Gavin Shan , Ben Horgan , rohit.mathew@arm.com, reinette.chatre@intel.com, Punit Agrawal , Dave Martin Subject: [RFC PATCH 15/38] arm_mpam: resctrl: Convert to/from MPAMs fixed-point formats Date: Fri, 5 Dec 2025 21:58:38 +0000 Message-Id: <20251205215901.17772-16-james.morse@arm.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20251205215901.17772-1-james.morse@arm.com> References: <20251205215901.17772-1-james.morse@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Dave Martin MPAM uses a fixed-point formats for some hardware controls. Resctrl provides the bandwidth controls as a percentage. Add helpers to convert between these. Signed-off-by: Dave Martin Signed-off-by: James Morse --- drivers/resctrl/mpam_resctrl.c | 41 ++++++++++++++++++++++++++++++++++ 1 file changed, 41 insertions(+) diff --git a/drivers/resctrl/mpam_resctrl.c b/drivers/resctrl/mpam_resctrl.c index 19d70d00bbcc..55576d0caf12 100644 --- a/drivers/resctrl/mpam_resctrl.c +++ b/drivers/resctrl/mpam_resctrl.c @@ -10,6 +10,7 @@ #include #include #include +#include #include #include #include @@ -246,6 +247,46 @@ static bool cache_has_usable_cpor(struct mpam_class *c= lass) return (class->props.cpbm_wd <=3D 32); } =20 +/* + * Each fixed-point hardware value architecturally represents a range + * of values: the full range 0% - 100% is split contiguously into + * (1 << cprops->bwa_wd) equal bands. + * Find the nearest percentage value to the upper bound of the selected ba= nd: + */ +static u32 mbw_max_to_percent(u16 mbw_max, struct mpam_props *cprops) +{ + u32 val =3D mbw_max; + + val >>=3D 16 - cprops->bwa_wd; + val +=3D 1; + val *=3D MAX_MBA_BW; + val =3D DIV_ROUND_CLOSEST(val, 1 << cprops->bwa_wd); + + return val; +} + +/* + * Find the band whose upper bound is closest to the specified percentage. + * + * A round-to-nearest policy is followed here as a balanced compromise + * between unexpected under-commit of the resource (where the total of + * a set of resource allocations after conversion is less than the + * expected total, due to rounding of the individual converted + * percentages) and over-commit (where the total of the converted + * allocations is greater than expected). + */ +static u16 percent_to_mbw_max(u8 pc, struct mpam_props *cprops) +{ + u32 val =3D pc; + + val <<=3D cprops->bwa_wd; + val =3D DIV_ROUND_CLOSEST(val, MAX_MBA_BW); + val =3D max(val, 1) - 1; + val <<=3D 16 - cprops->bwa_wd; + + return val; +} + /* Test whether we can export MPAM_CLASS_CACHE:{2,3}? */ static void mpam_resctrl_pick_caches(void) { --=20 2.39.5 From nobody Tue Dec 16 07:34:20 2025 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 3F6102D9494 for ; Fri, 5 Dec 2025 22:00:34 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764972036; cv=none; b=TRSDjDMV1LrXZRvQLpOfUtHA6zVcZITJWcNWdvCwGeiK95PIpPK5YBUP4wuAgN8RvuO/lEae16+WBhR4Ep2usilvrgwMA4xV5GAxOuKHtlPcr+PNNe6BtGtz7Hhuv1hPhQm0QN/EzCjiYA35/6PS9vEqbBuHHkLsYa5c6K62xbY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764972036; c=relaxed/simple; bh=I/jwUSUgTy6h1PRmxJAgeGndaKMsF7rFZZ3fKEAiF9U=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=r3IFbvjBB1Nk7cLNsruhSPm28dFSHoDDliiHSZzTnb20b2OW8QMYfoFmnsWb7iQJB2RoCLIk2o1juz/W7ck95yvyCbWM2EPveHFeJ0f4Acn2BIj0jDYrE1zneIxiAPsWXCzdBYblpkIujPN9l6qpTCYyioLA6gstO0qPFjYLmQY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 4663C1BC0; Fri, 5 Dec 2025 14:00:26 -0800 (PST) Received: from merodach.members.linode.com (usa-sjc-mx-foss1.foss.arm.com [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 91B603F7BD; Fri, 5 Dec 2025 14:00:29 -0800 (PST) From: James Morse To: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: James Morse , D Scott Phillips OS , carl@os.amperecomputing.com, lcherian@marvell.com, bobo.shaobowang@huawei.com, tan.shaopeng@fujitsu.com, baolin.wang@linux.alibaba.com, Jamie Iles , Xin Hao , peternewman@google.com, dfustini@baylibre.com, amitsinght@marvell.com, David Hildenbrand , Dave Martin , Koba Ko , Shanker Donthineni , fenghuay@nvidia.com, baisheng.gao@unisoc.com, Jonathan Cameron , Gavin Shan , Ben Horgan , rohit.mathew@arm.com, reinette.chatre@intel.com, Punit Agrawal , Zeng Heng , Dave Martin Subject: [RFC PATCH 16/38] arm_mpam: resctrl: Add support for 'MB' resource Date: Fri, 5 Dec 2025 21:58:39 +0000 Message-Id: <20251205215901.17772-17-james.morse@arm.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20251205215901.17772-1-james.morse@arm.com> References: <20251205215901.17772-1-james.morse@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" resctrl supports 'MB', as a percentage throttling of traffic somewhere after the L3. This is the control that mba_sc uses, so ideally the class chosen should be as close as possible to the counters used for mba_local. MB's percentage control should be backed either with the fixed point fraction MBW_MAX. The bandwidth portion bitmaps is not used as its tricky to pick which bits to use to avoid contention, and may be possible to expose this as something other than a percentage in the future. CC: Zeng Heng Co-developed-by: Dave Martin Signed-off-by: Dave Martin Signed-off-by: James Morse > --- drivers/resctrl/mpam_resctrl.c | 212 ++++++++++++++++++++++++++++++++- 1 file changed, 211 insertions(+), 1 deletion(-) diff --git a/drivers/resctrl/mpam_resctrl.c b/drivers/resctrl/mpam_resctrl.c index 55576d0caf12..b9f3f00d8cad 100644 --- a/drivers/resctrl/mpam_resctrl.c +++ b/drivers/resctrl/mpam_resctrl.c @@ -247,6 +247,33 @@ static bool cache_has_usable_cpor(struct mpam_class *c= lass) return (class->props.cpbm_wd <=3D 32); } =20 +static bool mba_class_use_mbw_max(struct mpam_props *cprops) +{ + return (mpam_has_feature(mpam_feat_mbw_max, cprops) && + cprops->bwa_wd); +} + +static bool class_has_usable_mba(struct mpam_props *cprops) +{ + return mba_class_use_mbw_max(cprops); +} + +/* + * Calculate the worst-case percentage change from each implemented step + * in the control. + */ +static u32 get_mba_granularity(struct mpam_props *cprops) +{ + if (!mba_class_use_mbw_max(cprops)) + return 0; + + /* + * bwa_wd is the number of bits implemented in the 0.xxx + * fixed point fraction. 1 bit is 50%, 2 is 25% etc. + */ + return DIV_ROUND_UP(MAX_MBA_BW, 1 << cprops->bwa_wd); +} + /* * Each fixed-point hardware value architecturally represents a range * of values: the full range 0% - 100% is split contiguously into @@ -287,6 +314,96 @@ static u16 percent_to_mbw_max(u8 pc, struct mpam_props= *cprops) return val; } =20 +static u32 get_mba_min(struct mpam_props *cprops) +{ + u32 val =3D 0; + + if (mba_class_use_mbw_max(cprops)) + val =3D mbw_max_to_percent(val, cprops); + else + WARN_ON_ONCE(1); + + return val; +} + +/* Find the L3 cache that has affinity with this CPU */ +static int find_l3_equivalent_bitmask(int cpu, cpumask_var_t tmp_cpumask) +{ + u32 cache_id =3D get_cpu_cacheinfo_id(cpu, 3); + + lockdep_assert_cpus_held(); + + return mpam_get_cpumask_from_cache_id(cache_id, 3, tmp_cpumask); +} + +/* + * topology_matches_l3() - Is the provided class the same shape as L3 + * @victim: The class we'd like to pretend is L3. + * + * resctrl expects all the world's a Xeon, and all counters are on the + * L3. We play fast and loose with this, mapping counters on other + * classes - provided the CPU->domain mapping is the same kind of shape. + * + * Using cacheinfo directly would make this work even if resctrl can't + * use the L3 - but cacheinfo can't tell us anything about offline CPUs. + * Using the L3 resctrl domain list also depends on CPUs being online. + * Using the mpam_class we picked for L3 so we can use its domain list + * assumes that there are MPAM controls on the L3. + * Instead, this path eventually uses the mpam_get_cpumask_from_cache_id() + * helper which can tell us about offline CPUs ... but getting the cache_id + * to start with relies on at least one CPU per L3 cache being online at + * boot. + * + * Walk the victim component list and compare the affinity mask with the + * corresponding L3. The topology matches if each victim:component's affin= ity + * mask is the same as the CPU's corresponding L3's. These lists/masks are + * computed from firmware tables so don't change at runtime. + */ +static bool topology_matches_l3(struct mpam_class *victim) +{ + int cpu, err; + struct mpam_component *victim_iter; + cpumask_var_t __free(free_cpumask_var) tmp_cpumask; + + if (!alloc_cpumask_var(&tmp_cpumask, GFP_KERNEL)) + return false; + + guard(srcu)(&mpam_srcu); + list_for_each_entry_srcu(victim_iter, &victim->components, class_list, + srcu_read_lock_held(&mpam_srcu)) { + if (cpumask_empty(&victim_iter->affinity)) { + pr_debug("class %u has CPU-less component %u - can't match L3!\n", + victim->level, victim_iter->comp_id); + return false; + } + + cpu =3D cpumask_any(&victim_iter->affinity); + if (WARN_ON_ONCE(cpu >=3D nr_cpu_ids)) + return false; + + cpumask_clear(tmp_cpumask); + err =3D find_l3_equivalent_bitmask(cpu, tmp_cpumask); + if (err) { + pr_debug("Failed to find L3's equivalent component to class %u componen= t %u\n", + victim->level, victim_iter->comp_id); + return false; + } + + /* Any differing bits in the affinity mask? */ + if (!cpumask_equal(tmp_cpumask, &victim_iter->affinity)) { + pr_debug("class %u component %u has Mismatched CPU mask with L3 equival= ent\n" + "L3:%*pbl !=3D victim:%*pbl\n", + victim->level, victim_iter->comp_id, + cpumask_pr_args(tmp_cpumask), + cpumask_pr_args(&victim_iter->affinity)); + + return false; + } + } + + return true; +} + /* Test whether we can export MPAM_CLASS_CACHE:{2,3}? */ static void mpam_resctrl_pick_caches(void) { @@ -330,10 +447,63 @@ static void mpam_resctrl_pick_caches(void) } } =20 +static void mpam_resctrl_pick_mba(void) +{ + struct mpam_class *class, *candidate_class =3D NULL; + struct mpam_resctrl_res *res; + + lockdep_assert_cpus_held(); + + guard(srcu)(&mpam_srcu); + list_for_each_entry_srcu(class, &mpam_classes, classes_list, + srcu_read_lock_held(&mpam_srcu)) { + struct mpam_props *cprops =3D &class->props; + + if (class->level < 3) { + pr_debug("class %u is before L3\n", class->level); + continue; + } + + if (!class_has_usable_mba(cprops)) { + pr_debug("class %u has no bandwidth control\n", + class->level); + continue; + } + + if (!cpumask_equal(&class->affinity, cpu_possible_mask)) { + pr_debug("class %u has missing CPUs\n", class->level); + continue; + } + + if (!topology_matches_l3(class)) { + pr_debug("class %u topology doesn't match L3\n", + class->level); + continue; + } + + /* + * mba_sc reads the mbm_local counter, and waggles the MBA + * controls. mbm_local is implicitly part of the L3, pick a + * resource to be MBA that as close as possible to the L3. + */ + if (!candidate_class || class->level < candidate_class->level) + candidate_class =3D class; + } + + if (candidate_class) { + pr_debug("selected class %u to back MBA\n", + candidate_class->level); + res =3D &mpam_resctrl_controls[RDT_RESOURCE_MBA]; + res->class =3D candidate_class; + exposed_alloc_capable =3D true; + } +} + static int mpam_resctrl_control_init(struct mpam_resctrl_res *res, enum resctrl_res_level type) { struct mpam_class *class =3D res->class; + struct mpam_props *cprops =3D &class->props; struct rdt_resource *r =3D &res->resctrl_res; =20 switch (res->resctrl_res.rid) { @@ -362,6 +532,20 @@ static int mpam_resctrl_control_init(struct mpam_resct= rl_res *res, * 'all the bits' is the correct answer here. */ r->cache.shareable_bits =3D resctrl_get_default_ctrl(r); + break; + case RDT_RESOURCE_MBA: + r->alloc_capable =3D true; + r->schema_fmt =3D RESCTRL_SCHEMA_RANGE; + r->ctrl_scope =3D RESCTRL_L3_CACHE; + + r->membw.delay_linear =3D true; + r->membw.throttle_mode =3D THREAD_THROTTLE_UNDEFINED; + r->membw.min_bw =3D get_mba_min(cprops); + r->membw.max_bw =3D MAX_MBA_BW; + r->membw.bw_gran =3D get_mba_granularity(cprops); + + r->name =3D "MB"; + break; default: break; @@ -377,7 +561,17 @@ static int mpam_resctrl_pick_domain_id(int cpu, struct= mpam_component *comp) if (class->type =3D=3D MPAM_CLASS_CACHE) return comp->comp_id; =20 - /* TODO: repaint domain ids to match the L3 domain ids */ + if (topology_matches_l3(class)) { + /* Use the corresponding L3 component ID as the domain ID */ + int id =3D get_cpu_cacheinfo_id(cpu, 3); + + /* Implies topology_matches_l3() made a mistake */ + if (WARN_ON_ONCE(id =3D=3D -1)) + return comp->comp_id; + + return id; + } + /* * Otherwise, expose the ID used by the firmware table code. */ @@ -419,6 +613,12 @@ u32 resctrl_arch_get_config(struct rdt_resource *r, st= ruct rdt_ctrl_domain *d, case RDT_RESOURCE_L3: configured_by =3D mpam_feat_cpor_part; break; + case RDT_RESOURCE_MBA: + if (mpam_has_feature(mpam_feat_mbw_max, cprops)) { + configured_by =3D mpam_feat_mbw_max; + break; + } + fallthrough; default: return resctrl_get_default_ctrl(r); } @@ -430,6 +630,8 @@ u32 resctrl_arch_get_config(struct rdt_resource *r, str= uct rdt_ctrl_domain *d, switch (configured_by) { case mpam_feat_cpor_part: return cfg->cpbm; + case mpam_feat_mbw_max: + return mbw_max_to_percent(cfg->mbw_max, cprops); default: return resctrl_get_default_ctrl(r); } @@ -474,6 +676,13 @@ int resctrl_arch_update_one(struct rdt_resource *r, st= ruct rdt_ctrl_domain *d, cfg.cpbm =3D cfg_val; mpam_set_feature(mpam_feat_cpor_part, &cfg); break; + case RDT_RESOURCE_MBA: + if (mpam_has_feature(mpam_feat_mbw_max, cprops)) { + cfg.mbw_max =3D percent_to_mbw_max(cfg_val, cprops); + mpam_set_feature(mpam_feat_mbw_max, &cfg); + break; + } + fallthrough; default: return -EINVAL; } @@ -743,6 +952,7 @@ int mpam_resctrl_setup(void) =20 /* Find some classes to use for controls */ mpam_resctrl_pick_caches(); + mpam_resctrl_pick_mba(); =20 /* Initialise the resctrl structures from the classes */ for (i =3D 0; i < RDT_NUM_RESOURCES; i++) { --=20 2.39.5 From nobody Tue Dec 16 07:34:20 2025 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 3977C2F6912 for ; Fri, 5 Dec 2025 22:00:38 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764972039; cv=none; b=kyciJ7onflziwXwVQVv74BJhhJcODwqKT9/9Kny+8eVwf/g0ezg1YF2FRSD/tMYHoIfWz2kDt4qgB8pas5dCYYsiNN3ZOn0Rtmp+/mWYYtUhd2ZcQw7pFJuFoPVn47E2IAtJxDHJRgyck3Qs/NICrL5zNQL3C0T+3u39FAJmI1g= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764972039; c=relaxed/simple; bh=Xi1Cg1lFMm8mEihO6bw4CM7tikbw5UNe4T7svID/yjw=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=W0NmnprMFgCg8+IhH4ShC0I5UqI4kxgqRiAJh+EaNDkWWYeCOurzfKqkPFLt3oPgsQT05xnVzpfP5rpRUq34+9IdrA8lRcNu0QseZeSQX0ZcZf+VFMJhx+Ph7Isty0KAb156fJJ6hXzk2R/0KaxfpBQR6tIPNPVcL8lT7DdahnM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 6EDE81BB2; Fri, 5 Dec 2025 14:00:30 -0800 (PST) Received: from merodach.members.linode.com (usa-sjc-mx-foss1.foss.arm.com [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id E02B93F740; Fri, 5 Dec 2025 14:00:33 -0800 (PST) From: James Morse To: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: James Morse , D Scott Phillips OS , carl@os.amperecomputing.com, lcherian@marvell.com, bobo.shaobowang@huawei.com, tan.shaopeng@fujitsu.com, baolin.wang@linux.alibaba.com, Jamie Iles , Xin Hao , peternewman@google.com, dfustini@baylibre.com, amitsinght@marvell.com, David Hildenbrand , Dave Martin , Koba Ko , Shanker Donthineni , fenghuay@nvidia.com, baisheng.gao@unisoc.com, Jonathan Cameron , Gavin Shan , Ben Horgan , rohit.mathew@arm.com, reinette.chatre@intel.com, Punit Agrawal , Dave Martin Subject: [RFC PATCH 17/38] arm_mpam: resctrl: Add kunit test for control format conversions Date: Fri, 5 Dec 2025 21:58:40 +0000 Message-Id: <20251205215901.17772-18-james.morse@arm.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20251205215901.17772-1-james.morse@arm.com> References: <20251205215901.17772-1-james.morse@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Dave Martin resctrl specifies the format of the control schemes, and these don't match the hardware. Some of the conversions are a bit hairy - add some kunit tests. Signed-off-by: Dave Martin [morse: squashed enough of Dave's fixes in here that it's his patch now!] Signed-off-by: James Morse --- drivers/resctrl/mpam_resctrl.c | 4 + drivers/resctrl/test_mpam_resctrl.c | 312 ++++++++++++++++++++++++++++ 2 files changed, 316 insertions(+) create mode 100644 drivers/resctrl/test_mpam_resctrl.c diff --git a/drivers/resctrl/mpam_resctrl.c b/drivers/resctrl/mpam_resctrl.c index b9f3f00d8cad..fe830524639e 100644 --- a/drivers/resctrl/mpam_resctrl.c +++ b/drivers/resctrl/mpam_resctrl.c @@ -993,3 +993,7 @@ int mpam_resctrl_setup(void) =20 return err; } + +#ifdef CONFIG_MPAM_KUNIT_TEST +#include "test_mpam_resctrl.c" +#endif diff --git a/drivers/resctrl/test_mpam_resctrl.c b/drivers/resctrl/test_mpa= m_resctrl.c new file mode 100644 index 000000000000..d0615aa7671c --- /dev/null +++ b/drivers/resctrl/test_mpam_resctrl.c @@ -0,0 +1,312 @@ +// SPDX-License-Identifier: GPL-2.0 +// Copyright (C) 2025 Arm Ltd. +/* This file is intended to be included into mpam_resctrl.c */ + +#include +#include +#include +#include +#include + +struct percent_value_case { + u8 pc; + u8 width; + u16 value; +}; + +/* + * Mysterious inscriptions taken from ARM DDI 0598D.b, + * "Arm Architecture Reference Manual Supplement - Memory System + * Resource Partitioning and Monitoring (MPAM), for A-profile + * architecture", Section 9.8, "About the fixed-point fractional + * format" (exact percentage entries only): + */ +static const struct percent_value_case percent_value_cases[] =3D { + /* Architectural cases: */ + { 1, 8, 1 }, { 1, 12, 0x27 }, { 1, 16, 0x28e }, + { 25, 8, 0x3f }, { 25, 12, 0x3ff }, { 25, 16, 0x3fff }, + { 35, 8, 0x58 }, { 35, 12, 0x598 }, { 35, 16, 0x5998 }, + { 45, 8, 0x72 }, { 45, 12, 0x732 }, { 45, 16, 0x7332 }, + { 50, 8, 0x7f }, { 50, 12, 0x7ff }, { 50, 16, 0x7fff }, + { 52, 8, 0x84 }, { 52, 12, 0x850 }, { 52, 16, 0x851d }, + { 55, 8, 0x8b }, { 55, 12, 0x8cb }, { 55, 16, 0x8ccb }, + { 58, 8, 0x93 }, { 58, 12, 0x946 }, { 58, 16, 0x9479 }, + { 75, 8, 0xbf }, { 75, 12, 0xbff }, { 75, 16, 0xbfff }, + { 88, 8, 0xe0 }, { 88, 12, 0xe13 }, { 88, 16, 0xe146 }, + { 95, 8, 0xf2 }, { 95, 12, 0xf32 }, { 95, 16, 0xf332 }, + { 100, 8, 0xff }, { 100, 12, 0xfff }, { 100, 16, 0xffff }, + +}; + +static void test_percent_value_desc(const struct percent_value_case *param, + char *desc) +{ + snprintf(desc, KUNIT_PARAM_DESC_SIZE, + "pc=3D%d, width=3D%d, value=3D0x%.*x\n", + param->pc, param->width, + DIV_ROUND_UP(param->width, 4), param->value); +} + +KUNIT_ARRAY_PARAM(test_percent_value, percent_value_cases, + test_percent_value_desc); + +struct percent_value_test_info { + u32 pc; /* result of value-to-percent conversion */ + u32 value; /* result of percent-to-value conversion */ + u32 max_value; /* maximum raw value allowed by test params */ + unsigned int shift; /* promotes raw testcase value to 16 bits */ +}; + +/* + * Convert a reference percentage to a fixed-point MAX value and + * vice-versa, based on param (not test->param_value!) + */ +static void __prepare_percent_value_test(struct kunit *test, + struct percent_value_test_info *res, + const struct percent_value_case *param) +{ + struct mpam_props fake_props =3D { }; + + /* Reject bogus test parameters that would break the tests: */ + KUNIT_ASSERT_GE(test, param->width, 1); + KUNIT_ASSERT_LE(test, param->width, 16); + KUNIT_ASSERT_LT(test, param->value, 1 << param->width); + + mpam_set_feature(mpam_feat_mbw_max, &fake_props); + fake_props.bwa_wd =3D param->width; + + res->shift =3D 16 - param->width; + res->max_value =3D GENMASK_U32(param->width - 1, 0); + res->value =3D percent_to_mbw_max(param->pc, &fake_props); + res->pc =3D mbw_max_to_percent(param->value << res->shift, &fake_props); +} + +static void test_get_mba_granularity(struct kunit *test) +{ + int ret; + struct mpam_props fake_props =3D { }; + + /* Use MBW_MAX */ + mpam_set_feature(mpam_feat_mbw_max, &fake_props); + + fake_props.bwa_wd =3D 0; + KUNIT_EXPECT_FALSE(test, mba_class_use_mbw_max(&fake_props)); + + fake_props.bwa_wd =3D 1; + KUNIT_EXPECT_TRUE(test, mba_class_use_mbw_max(&fake_props)); + + /* Architectural maximum: */ + fake_props.bwa_wd =3D 16; + KUNIT_EXPECT_TRUE(test, mba_class_use_mbw_max(&fake_props)); + + /* No usable control... */ + fake_props.bwa_wd =3D 0; + ret =3D get_mba_granularity(&fake_props); + KUNIT_EXPECT_EQ(test, ret, 0); + + fake_props.bwa_wd =3D 1; + ret =3D get_mba_granularity(&fake_props); + KUNIT_EXPECT_EQ(test, ret, 50); /* DIV_ROUND_UP(100, 1 << 1)% =3D 50% */ + + fake_props.bwa_wd =3D 2; + ret =3D get_mba_granularity(&fake_props); + KUNIT_EXPECT_EQ(test, ret, 25); /* DIV_ROUND_UP(100, 1 << 2)% =3D 25% */ + + fake_props.bwa_wd =3D 3; + ret =3D get_mba_granularity(&fake_props); + KUNIT_EXPECT_EQ(test, ret, 13); /* DIV_ROUND_UP(100, 1 << 3)% =3D 13% */ + + fake_props.bwa_wd =3D 6; + ret =3D get_mba_granularity(&fake_props); + KUNIT_EXPECT_EQ(test, ret, 2); /* DIV_ROUND_UP(100, 1 << 6)% =3D 2% */ + + fake_props.bwa_wd =3D 7; + ret =3D get_mba_granularity(&fake_props); + KUNIT_EXPECT_EQ(test, ret, 1); /* DIV_ROUND_UP(100, 1 << 7)% =3D 1% */ + + /* Granularity saturates at 1% */ + fake_props.bwa_wd =3D 16; /* architectural maximum */ + ret =3D get_mba_granularity(&fake_props); + KUNIT_EXPECT_EQ(test, ret, 1); /* DIV_ROUND_UP(100, 1 << 16)% =3D 1% */ +} + +static void test_mbw_max_to_percent(struct kunit *test) +{ + const struct percent_value_case *param =3D test->param_value; + struct percent_value_test_info res; + + /* + * Since the reference values in percent_value_cases[] all + * correspond to exact percentages, round-to-nearest will + * always give the exact percentage back when the MPAM max + * value has precision of 0.5% or finer. (Always true for the + * reference data, since they all specify 8 bits or more of + * precision. + * + * So, keep it simple and demand an exact match: + */ + __prepare_percent_value_test(test, &res, param); + KUNIT_EXPECT_EQ(test, res.pc, param->pc); +} + +static void test_percent_to_mbw_max(struct kunit *test) +{ + const struct percent_value_case *param =3D test->param_value; + struct percent_value_test_info res; + + __prepare_percent_value_test(test, &res, param); + + KUNIT_EXPECT_GE(test, res.value, param->value << res.shift); + KUNIT_EXPECT_LE(test, res.value, (param->value + 1) << res.shift); + KUNIT_EXPECT_LE(test, res.value, res.max_value << res.shift); + + /* No flexibility allowed for 0% and 100%! */ + + if (param->pc =3D=3D 0) + KUNIT_EXPECT_EQ(test, res.value, 0); + + if (param->pc =3D=3D 100) + KUNIT_EXPECT_EQ(test, res.value, res.max_value << res.shift); +} + +static const void *test_all_bwa_wd_gen_params(struct kunit *test, const vo= id *prev, + char *desc) +{ + uintptr_t param =3D (uintptr_t)prev; + + if (param > 15) + return NULL; + + param++; + + snprintf(desc, KUNIT_PARAM_DESC_SIZE, "wd=3D%u\n", (unsigned int)param); + + return (void *)param; +} + +static unsigned int test_get_bwa_wd(struct kunit *test) +{ + uintptr_t param =3D (uintptr_t)test->param_value; + + KUNIT_ASSERT_GE(test, param, 1); + KUNIT_ASSERT_LE(test, param, 16); + + return param; +} + +static void test_mbw_max_to_percent_limits(struct kunit *test) +{ + struct mpam_props fake_props =3D {0}; + u32 max_value; + + mpam_set_feature(mpam_feat_mbw_max, &fake_props); + fake_props.bwa_wd =3D test_get_bwa_wd(test); + max_value =3D GENMASK(15, 16 - fake_props.bwa_wd); + + KUNIT_EXPECT_EQ(test, mbw_max_to_percent(max_value, &fake_props), + MAX_MBA_BW); + KUNIT_EXPECT_EQ(test, mbw_max_to_percent(0, &fake_props), + get_mba_min(&fake_props)); + + /* + * Rounding policy dependent 0% sanity-check: + * With round-to-nearest, the minimum mbw_max value really + * should map to 0% if there are at least 200 steps. + * (100 steps may be enough for some other rounding policies.) + */ + if (fake_props.bwa_wd >=3D 8) + KUNIT_EXPECT_EQ(test, mbw_max_to_percent(0, &fake_props), 0); + + if (fake_props.bwa_wd < 8 && + mbw_max_to_percent(0, &fake_props) =3D=3D 0) + kunit_warn(test, "wd=3D%d: Testsuite/driver Rounding policy mismatch?", + fake_props.bwa_wd); +} + +/* + * Check that converting a percentage to mbw_max and back again (or, as + * appropriate, vice-versa) always restores the original value: + */ +static void test_percent_max_roundtrip_stability(struct kunit *test) +{ + struct mpam_props fake_props =3D {0}; + unsigned int shift; + u32 pc, max, pc2, max2; + + mpam_set_feature(mpam_feat_mbw_max, &fake_props); + fake_props.bwa_wd =3D test_get_bwa_wd(test); + shift =3D 16 - fake_props.bwa_wd; + + /* + * Converting a valid value from the coarser scale to the finer + * scale and back again must yield the original value: + */ + if (fake_props.bwa_wd >=3D 7) { + /* More than 100 steps: only test exact pc values: */ + for (pc =3D get_mba_min(&fake_props); pc <=3D MAX_MBA_BW; pc++) { + max =3D percent_to_mbw_max(pc, &fake_props); + pc2 =3D mbw_max_to_percent(max, &fake_props); + KUNIT_EXPECT_EQ(test, pc2, pc); + } + } else { + /* Fewer than 100 steps: only test exact mbw_max values: */ + for (max =3D 0; max < 1 << 16; max +=3D 1 << shift) { + pc =3D mbw_max_to_percent(max, &fake_props); + max2 =3D percent_to_mbw_max(pc, &fake_props); + KUNIT_EXPECT_EQ(test, max2, max); + } + } +} + +static void test_percent_to_max_rounding(struct kunit *test) +{ + const struct percent_value_case *param =3D test->param_value; + unsigned int num_rounded_up =3D 0, total =3D 0; + struct percent_value_test_info res; + + for (param =3D percent_value_cases, total =3D 0; + param < &percent_value_cases[ARRAY_SIZE(percent_value_cases)]; + param++, total++) { + __prepare_percent_value_test(test, &res, param); + if (res.value > param->value << res.shift) + num_rounded_up++; + } + + /* + * The MPAM driver applies a round-to-nearest policy, whereas a + * round-down policy seems to have been applied in the + * reference table from which the test vectors were selected. + * + * For a large and well-distributed suite of test vectors, + * about half should be rounded up and half down compared with + * the reference table. The actual test vectors are few in + * number and probably not very well distributed however, so + * tolerate a round-up rate of between 1/4 and 3/4 before + * crying foul: + */ + + kunit_info(test, "Round-up rate: %u%% (%u/%u)\n", + DIV_ROUND_CLOSEST(num_rounded_up * 100, total), + num_rounded_up, total); + + KUNIT_EXPECT_GE(test, 4 * num_rounded_up, 1 * total); + KUNIT_EXPECT_LE(test, 4 * num_rounded_up, 3 * total); +} + +static struct kunit_case mpam_resctrl_test_cases[] =3D { + KUNIT_CASE(test_get_mba_granularity), + KUNIT_CASE_PARAM(test_mbw_max_to_percent, test_percent_value_gen_params), + KUNIT_CASE_PARAM(test_percent_to_mbw_max, test_percent_value_gen_params), + KUNIT_CASE_PARAM(test_mbw_max_to_percent_limits, test_all_bwa_wd_gen_para= ms), + KUNIT_CASE(test_percent_to_max_rounding), + KUNIT_CASE_PARAM(test_percent_max_roundtrip_stability, + test_all_bwa_wd_gen_params), + {} +}; + +static struct kunit_suite mpam_resctrl_test_suite =3D { + .name =3D "mpam_resctrl_test_suite", + .test_cases =3D mpam_resctrl_test_cases, +}; + +kunit_test_suites(&mpam_resctrl_test_suite); --=20 2.39.5 From nobody Tue Dec 16 07:34:20 2025 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 762862F7AB1 for ; Fri, 5 Dec 2025 22:00:42 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764972045; cv=none; b=ZhIFYAMrZSq9AC1ZVQVywgjK6ITFXXmVZVI61AJUi5vQeZLOzVB+fwF7q/ywgk1BcDi8C3cIeuqQHaEkLsmIiHvGGo9GlTPAVbC9dUVwj0uLe0rwqUdEYOHS1EghcIu4oMUUAsUjNhT2J2LnmIm3C+3JQdUOBLNdDl90ctrXiJ4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764972045; c=relaxed/simple; bh=L6Wo+78BzlPsdlQkXQR95Tj2GKrQ4Et9yr4EnE+nGCA=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=rhw1muys3G7AAGC6A9BMfwhzLa+GGHRaeD9lz4q6tWVWavdPo689dlWG3CNHcJWCgb4zr19iVKZ8vtCb+ixnqa1CwmnTUI/dp12XxN/fIHuRYVtPgrJ0lSZ+6+iUh8PAkTt+S85AcZkSy0bv0CmvFPesqPx1bdnolmkger7ofCA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 72D181AED; Fri, 5 Dec 2025 14:00:34 -0800 (PST) Received: from merodach.members.linode.com (usa-sjc-mx-foss1.foss.arm.com [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 102523F740; Fri, 5 Dec 2025 14:00:37 -0800 (PST) From: James Morse To: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: James Morse , D Scott Phillips OS , carl@os.amperecomputing.com, lcherian@marvell.com, bobo.shaobowang@huawei.com, tan.shaopeng@fujitsu.com, baolin.wang@linux.alibaba.com, Jamie Iles , Xin Hao , peternewman@google.com, dfustini@baylibre.com, amitsinght@marvell.com, David Hildenbrand , Dave Martin , Koba Ko , Shanker Donthineni , fenghuay@nvidia.com, baisheng.gao@unisoc.com, Jonathan Cameron , Gavin Shan , Ben Horgan , rohit.mathew@arm.com, reinette.chatre@intel.com, Punit Agrawal Subject: [RFC PATCH 18/38] arm_mpam: resctrl: Add support for csu counters Date: Fri, 5 Dec 2025 21:58:41 +0000 Message-Id: <20251205215901.17772-19-james.morse@arm.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20251205215901.17772-1-james.morse@arm.com> References: <20251205215901.17772-1-james.morse@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" resctrl exposes a counter via a file named llc_occupancy. This isn't really a counter as its value goes up and down, this is a snapshot of the cache storage usage monitor. Add some picking code to find a cache as close as possible to the L3 that supports the CSU monitor. If there is an L3, but it doesn't have any controls, force the L3 resource to exist. The existing topology_matches_l3() and mpam_resctrl_domain_hdr_init() code will ensure this looks like the L3, even if the class belongs to a later cache. Signed-off-by: James Morse --- drivers/resctrl/mpam_internal.h | 6 ++ drivers/resctrl/mpam_resctrl.c | 148 ++++++++++++++++++++++++++++++++ 2 files changed, 154 insertions(+) diff --git a/drivers/resctrl/mpam_internal.h b/drivers/resctrl/mpam_interna= l.h index 8684bd35d4ab..f9d2a1004c32 100644 --- a/drivers/resctrl/mpam_internal.h +++ b/drivers/resctrl/mpam_internal.h @@ -348,6 +348,12 @@ struct mpam_resctrl_res { struct rdt_resource resctrl_res; }; =20 +struct mpam_resctrl_mon { + struct mpam_class *class; + + /* per-class data that resctrl needs will live here */ +}; + static inline int mpam_alloc_csu_mon(struct mpam_class *class) { struct mpam_props *cprops =3D &class->props; diff --git a/drivers/resctrl/mpam_resctrl.c b/drivers/resctrl/mpam_resctrl.c index fe830524639e..fc1f054f187e 100644 --- a/drivers/resctrl/mpam_resctrl.c +++ b/drivers/resctrl/mpam_resctrl.c @@ -31,6 +31,16 @@ static struct mpam_resctrl_res mpam_resctrl_controls[RDT= _NUM_RESOURCES]; /* The lock for modifying resctrl's domain lists from cpuhp callbacks. */ static DEFINE_MUTEX(domain_list_lock); =20 +/* + * The classes we've picked to map to resctrl events. + * Resctrl believes all the worlds a Xeon, and these are all on the L3. Th= is + * array lets us find the actual class backing the event counters. e.g. + * the only memory bandwidth counters may be on the memory controller, but= to + * make use of them, we pretend they are on L3. + * Class pointer may be NULL. + */ +static struct mpam_resctrl_mon mpam_resctrl_counters[QOS_NUM_EVENTS]; + static bool exposed_alloc_capable; static bool exposed_mon_capable; =20 @@ -258,6 +268,28 @@ static bool class_has_usable_mba(struct mpam_props *cp= rops) return mba_class_use_mbw_max(cprops); } =20 +static bool cache_has_usable_csu(struct mpam_class *class) +{ + struct mpam_props *cprops; + + if (!class) + return false; + + cprops =3D &class->props; + + if (!mpam_has_feature(mpam_feat_msmon_csu, cprops)) + return false; + + /* + * CSU counters settle on the value, so we can get away with + * having only one. + */ + if (!cprops->num_csu_mon) + return false; + + return (mpam_partid_max > 1) || (mpam_pmg_max !=3D 0); +} + /* * Calculate the worst-case percentage change from each implemented step * in the control. @@ -499,6 +531,64 @@ static void mpam_resctrl_pick_mba(void) } } =20 +static void counter_update_class(enum resctrl_event_id evt_id, + struct mpam_class *class) +{ + struct mpam_class *existing_class =3D mpam_resctrl_counters[evt_id].class; + + if (existing_class) { + if (class->level =3D=3D 3) { + pr_debug("Existing class is L3 - L3 wins\n"); + return; + } else if (existing_class->level < class->level) { + pr_debug("Existing class is closer to L3, %u versus %u - closer is bett= er\n", + existing_class->level, class->level); + return; + } + } + + mpam_resctrl_counters[evt_id].class =3D class; + exposed_mon_capable =3D true; +} + +static void mpam_resctrl_pick_counters(void) +{ + struct mpam_class *class; + bool has_csu; + + lockdep_assert_cpus_held(); + + guard(srcu)(&mpam_srcu); + list_for_each_entry_srcu(class, &mpam_classes, classes_list, + srcu_read_lock_held(&mpam_srcu)) { + if (class->level < 3) { + pr_debug("class %u is before L3", class->level); + continue; + } + + if (!cpumask_equal(&class->affinity, cpu_possible_mask)) { + pr_debug("class %u does not cover all CPUs", + class->level); + continue; + } + + has_csu =3D cache_has_usable_csu(class); + if (has_csu && topology_matches_l3(class)) { + pr_debug("class %u has usable CSU, and matches L3 topology", + class->level); + + /* CSU counters only make sense on a cache. */ + switch (class->type) { + case MPAM_CLASS_CACHE: + counter_update_class(QOS_L3_OCCUP_EVENT_ID, class); + return; + default: + return; + } + } + } +} + static int mpam_resctrl_control_init(struct mpam_resctrl_res *res, enum resctrl_res_level type) { @@ -578,6 +668,50 @@ static int mpam_resctrl_pick_domain_id(int cpu, struct= mpam_component *comp) return comp->comp_id; } =20 +static void mpam_resctrl_monitor_init(struct mpam_resctrl_mon *mon, + enum resctrl_event_id type) +{ + struct mpam_resctrl_res *res =3D &mpam_resctrl_controls[RDT_RESOURCE_L3]; + struct rdt_resource *l3 =3D &res->resctrl_res; + + lockdep_assert_cpus_held(); + + /* There also needs to be an L3 cache present */ + if (get_cpu_cacheinfo_id(smp_processor_id(), 3) =3D=3D -1) + return; + + /* + * If there are no MPAM resources on L3, force it into existence. + * topology_matches_l3() already ensures this looks like the L3. + * The domain-ids will be fixed up by mpam_resctrl_domain_hdr_init(). + */ + if (!res->class) { + pr_warn_once("Faking L3 MSC to enable counters.\n"); + res->class =3D mpam_resctrl_counters[type].class; + } + + /* Called multiple times!, once per event type */ + if (exposed_mon_capable) { + l3->mon_capable =3D true; + + /* Setting name is necessary on monitor only platforms */ + l3->name =3D "L3"; + l3->mon_scope =3D RESCTRL_L3_CACHE; + + resctrl_enable_mon_event(type); + + /* + * Unfortunately, num_rmid doesn't mean anything for + * mpam, and its exposed to user-space! + * num-rmid is supposed to mean the number of groups + * that can be created, both control or monitor groups. + * For mpam, each control group has its own pmg/rmid + * space. + */ + l3->mon.num_rmid =3D 1; + } +} + u32 resctrl_arch_get_config(struct rdt_resource *r, struct rdt_ctrl_domain= *d, u32 closid, enum resctrl_conf_type type) { @@ -939,8 +1073,10 @@ void mpam_resctrl_offline_cpu(unsigned int cpu) int mpam_resctrl_setup(void) { int err =3D 0; + enum resctrl_event_id j; enum resctrl_res_level i; struct mpam_resctrl_res *res; + struct mpam_resctrl_mon *mon; =20 cpus_read_lock(); for (i =3D 0; i < RDT_NUM_RESOURCES; i++) { @@ -966,6 +1102,18 @@ int mpam_resctrl_setup(void) break; } } + + /* Find some classes to use for monitors */ + mpam_resctrl_pick_counters(); + + for (j =3D 0; j < QOS_NUM_EVENTS; j++) { + mon =3D &mpam_resctrl_counters[j]; + if (!mon->class) + continue; // dummy resource + + mpam_resctrl_monitor_init(mon, j); + } + cpus_read_unlock(); =20 if (err || (!exposed_alloc_capable && !exposed_mon_capable)) { --=20 2.39.5 From nobody Tue Dec 16 07:34:20 2025 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 82D642DFF28 for ; Fri, 5 Dec 2025 22:00:46 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764972049; cv=none; b=p4FMBLTCrik4La6HlSe2nCCQ35p4NRsNFl1I8I5cRPVYaodFgCkoe6HrcViSw4xi7EDGuOt+cNrFOPNgb+npke0Ps2twgyESdkCZEsnerL3py1jkl2GrXgJxgDURTSoyrSUvHZjLgfEcQbnxkTFhVebr1NV+3Q029dpWZtWbNQM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764972049; c=relaxed/simple; bh=BB49oR8OOeWfYaB3/LnFatUHVMcvmbZO0C+pmH5mPmg=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=H2/1m0Fy7M1hjMWSSSNSZ8TwnUeQ6C3nUlEz1U1UV6evUJGTqMJ11DTeUNADjykSaPIuMjvKqBbCgqVe4s3xUzy2la0uqiZ0Imb6+tHmfr9FjFLpuDWOrnzkeWLyjrT5J2VLIIy6gDs1PaBVOb5gRv8hBzKIg2xi5bMWGDIBBsk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 8D2491BA8; Fri, 5 Dec 2025 14:00:38 -0800 (PST) Received: from merodach.members.linode.com (usa-sjc-mx-foss1.foss.arm.com [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 1A0053F740; Fri, 5 Dec 2025 14:00:41 -0800 (PST) From: James Morse To: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: James Morse , D Scott Phillips OS , carl@os.amperecomputing.com, lcherian@marvell.com, bobo.shaobowang@huawei.com, tan.shaopeng@fujitsu.com, baolin.wang@linux.alibaba.com, Jamie Iles , Xin Hao , peternewman@google.com, dfustini@baylibre.com, amitsinght@marvell.com, David Hildenbrand , Dave Martin , Koba Ko , Shanker Donthineni , fenghuay@nvidia.com, baisheng.gao@unisoc.com, Jonathan Cameron , Gavin Shan , Ben Horgan , rohit.mathew@arm.com, reinette.chatre@intel.com, Punit Agrawal Subject: [RFC PATCH 19/38] arm_mpam: resctrl: pick classes for use as mbm counters Date: Fri, 5 Dec 2025 21:58:42 +0000 Message-Id: <20251205215901.17772-20-james.morse@arm.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20251205215901.17772-1-james.morse@arm.com> References: <20251205215901.17772-1-james.morse@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" resctrl has two types of counters, NUMA-local and global. MPAM has only bandwidth counters, but the position of the MSC may mean it counts NUMA-local, or global traffic. But the topology information is not available. Apply a heuristic: the L2 or L3 supports bandwidth monitors, these are probably NUMA-local. If the memory controller supports bandwidth monitors, they are probably global. This also allows us to assert that we don't have the same class backing two different resctrl events. Because the class or component backing the event may not be 'the L3', it is necessary for mpam_resctrl_get_domain_from_cpu() to search the monitor domains too. This matters the most for 'monitor only' systems, where 'the L3' control domains may be empty, and the ctrl_comp pointer NULL. resctrl expects there to be enough monitors for every possible control and monitor group to have one. Such a system gets called 'free running' as the monitors can be programmed once and left running. Any other platform will need to emulate ABMC. Signed-off-by: James Morse --- drivers/resctrl/mpam_internal.h | 8 ++ drivers/resctrl/mpam_resctrl.c | 141 ++++++++++++++++++++++++++++++-- 2 files changed, 144 insertions(+), 5 deletions(-) diff --git a/drivers/resctrl/mpam_internal.h b/drivers/resctrl/mpam_interna= l.h index f9d2a1004c32..0984ac32f303 100644 --- a/drivers/resctrl/mpam_internal.h +++ b/drivers/resctrl/mpam_internal.h @@ -339,6 +339,14 @@ struct mpam_msc_ris { =20 struct mpam_resctrl_dom { struct mpam_component *ctrl_comp; + + /* + * There is no single mon_comp because different events may be backed + * by different class/components. mon_comp is indexed by the event + * number. + */ + struct mpam_component *mon_comp[QOS_NUM_EVENTS]; + struct rdt_ctrl_domain resctrl_ctrl_dom; struct rdt_mon_domain resctrl_mon_dom; }; diff --git a/drivers/resctrl/mpam_resctrl.c b/drivers/resctrl/mpam_resctrl.c index fc1f054f187e..9978eb48c1f4 100644 --- a/drivers/resctrl/mpam_resctrl.c +++ b/drivers/resctrl/mpam_resctrl.c @@ -50,6 +50,14 @@ static bool exposed_mon_capable; */ static bool cdp_enabled; =20 +/* Whether this num_mbw_mon could result in a free_running system */ +static int __mpam_monitors_free_running(u16 num_mbwu_mon) +{ + if (num_mbwu_mon >=3D resctrl_arch_system_num_rmid_idx()) + return resctrl_arch_system_num_rmid_idx(); + return 0; +} + bool resctrl_arch_alloc_capable(void) { return exposed_alloc_capable; @@ -290,6 +298,26 @@ static bool cache_has_usable_csu(struct mpam_class *cl= ass) return (mpam_partid_max > 1) || (mpam_pmg_max !=3D 0); } =20 +static bool class_has_usable_mbwu(struct mpam_class *class) +{ + struct mpam_props *cprops =3D &class->props; + + if (!mpam_has_feature(mpam_feat_msmon_mbwu, cprops)) + return false; + + /* + * resctrl expects the bandwidth counters to be free running, + * which means we need as many monitors as resctrl has + * control/monitor groups. + */ + if (__mpam_monitors_free_running(cprops->num_mbwu_mon)) { + pr_debug("monitors usable in free-running mode\n"); + return true; + } + + return false; +} + /* * Calculate the worst-case percentage change from each implemented step * in the control. @@ -554,7 +582,7 @@ static void counter_update_class(enum resctrl_event_id = evt_id, static void mpam_resctrl_pick_counters(void) { struct mpam_class *class; - bool has_csu; + bool has_csu, has_mbwu; =20 lockdep_assert_cpus_held(); =20 @@ -586,7 +614,37 @@ static void mpam_resctrl_pick_counters(void) return; } } + + has_mbwu =3D class_has_usable_mbwu(class); + if (has_mbwu && topology_matches_l3(class)) { + pr_debug("class %u has usable MBWU, and matches L3 topology", + class->level); + + /* + * MBWU counters may be 'local' or 'total' depending on + * where they are in the topology. Counters on caches + * are assumed to be local. If it's on the memory + * controller, its assumed to be global. + */ + switch (class->type) { + case MPAM_CLASS_CACHE: + counter_update_class(QOS_L3_MBM_LOCAL_EVENT_ID, + class); + break; + case MPAM_CLASS_MEMORY: + counter_update_class(QOS_L3_MBM_TOTAL_EVENT_ID, + class); + break; + default: + break; + } + } } + + /* Allocation of MBWU monitors assumes that the class is unique... */ + if (mpam_resctrl_counters[QOS_L3_MBM_LOCAL_EVENT_ID].class) + WARN_ON_ONCE(mpam_resctrl_counters[QOS_L3_MBM_LOCAL_EVENT_ID].class =3D= =3D + mpam_resctrl_counters[QOS_L3_MBM_TOTAL_EVENT_ID].class); } =20 static int mpam_resctrl_control_init(struct mpam_resctrl_res *res, @@ -910,6 +968,20 @@ static bool mpam_resctrl_offline_domain_hdr(unsigned i= nt cpu, return false; } =20 +static struct mpam_component *find_component(struct mpam_class *victim, in= t cpu) +{ + struct mpam_component *victim_comp; + + guard(srcu)(&mpam_srcu); + list_for_each_entry_srcu(victim_comp, &victim->components, class_list, + srcu_read_lock_held(&mpam_srcu)) { + if (cpumask_test_cpu(cpu, &victim_comp->affinity)) + return victim_comp; + } + + return NULL; +} + static struct mpam_resctrl_dom * mpam_resctrl_alloc_domain(unsigned int cpu, struct mpam_resctrl_res *res) { @@ -959,8 +1031,32 @@ mpam_resctrl_alloc_domain(unsigned int cpu, struct mp= am_resctrl_res *res) } =20 if (exposed_mon_capable) { + int i; + struct mpam_component *mon_comp, *any_mon_comp; + + /* + * Even if the monitor domain is backed by a different + * component, the L3 component IDs need to be used... only + * there may be no ctrl_comp for the L3. + * Search each event's class list for a component with + * overlapping CPUs and set up the dom->mon_comp array. + */ + for (i =3D 0; i < QOS_NUM_EVENTS; i++) { + struct mpam_resctrl_mon *mon; + + mon =3D &mpam_resctrl_counters[i]; + if (!mon->class) + continue; // dummy resource + + mon_comp =3D find_component(mon->class, cpu); + dom->mon_comp[i] =3D mon_comp; + if (mon_comp) + any_mon_comp =3D mon_comp; + } + WARN_ON_ONCE(!any_mon_comp); + mon_d =3D &dom->resctrl_mon_dom; - mpam_resctrl_domain_hdr_init(cpu, ctrl_comp, &mon_d->hdr); + mpam_resctrl_domain_hdr_init(cpu, any_mon_comp, &mon_d->hdr); mon_d->hdr.type =3D RESCTRL_MON_DOMAIN; /* TODO: this list should be sorted */ list_add_tail_rcu(&mon_d->hdr.list, &r->mon_domains); @@ -982,16 +1078,47 @@ mpam_resctrl_alloc_domain(unsigned int cpu, struct m= pam_resctrl_res *res) return dom; } =20 +/* + * We know all the monitors are associated with the L3, even if there are = no + * controls and therefore no control component. Find the cache-id for the = CPU + * and use that to search for existing resctrl domains. + * This relies on mpam_resctrl_pick_domain_id() using the L3 cache-id + * for anything that is not a cache. + */ +static struct mpam_resctrl_dom *mpam_resctrl_get_mon_domain_from_cpu(int c= pu) +{ + u32 cache_id; + struct rdt_mon_domain *mon_d; + struct mpam_resctrl_dom *dom; + struct mpam_resctrl_res *l3 =3D &mpam_resctrl_controls[RDT_RESOURCE_L3]; + + if (!l3->class) + return NULL; + /* TODO: how does this order with cacheinfo updates under cpuhp? */ + cache_id =3D get_cpu_cacheinfo_id(cpu, 3); + if (cache_id =3D=3D ~0) + return NULL; + + list_for_each_entry(mon_d, &l3->resctrl_res.mon_domains, hdr.list) { + dom =3D container_of(mon_d, struct mpam_resctrl_dom, resctrl_mon_dom); + + if (mon_d->hdr.id =3D=3D cache_id) + return dom; + } + + return NULL; +} + static struct mpam_resctrl_dom * mpam_resctrl_get_domain_from_cpu(int cpu, struct mpam_resctrl_res *res) { struct mpam_resctrl_dom *dom; struct rdt_ctrl_domain *ctrl_d; + struct rdt_resource *r =3D &res->resctrl_res; =20 lockdep_assert_cpus_held(); =20 - list_for_each_entry_rcu(ctrl_d, &res->resctrl_res.ctrl_domains, - hdr.list) { + list_for_each_entry_rcu(ctrl_d, &r->ctrl_domains, hdr.list) { dom =3D container_of(ctrl_d, struct mpam_resctrl_dom, resctrl_ctrl_dom); =20 @@ -999,7 +1126,11 @@ mpam_resctrl_get_domain_from_cpu(int cpu, struct mpam= _resctrl_res *res) return dom; } =20 - return NULL; + if (r->rid !=3D RDT_RESOURCE_L3) + return NULL; + + /* Search the mon domain list too - needed on monitor only platforms. */ + return mpam_resctrl_get_mon_domain_from_cpu(cpu); } =20 int mpam_resctrl_online_cpu(unsigned int cpu) --=20 2.39.5 From nobody Tue Dec 16 07:34:20 2025 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id B68C92FB0BA for ; Fri, 5 Dec 2025 22:00:50 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764972052; cv=none; b=cEmZ/YIOTokhoWRzz5deppYrotjIUk/WGCPSoq198igx5DXgXVgx1okndW+u3W1/jIzXYdjRS9CZ3DIe5FD2+emhZ8rbn2r5PD2zy56qa3VHaIB9QgvGAgmw0lLYRZmvLUvYvxhfkEShrVasA+Vyqf4IAfK8NIJRIQa3KsmB9N0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764972052; c=relaxed/simple; bh=PPKnAJeRZEyzaBQHrICucx6mMKJVoBb8xG/UJcUpAz8=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=nO8UrwtRJQtbVLKK72t9YHOsv8/W1GiygOPNj+mRTz761ZiOYLG8LwopnXhSEK5Zr+9Wv6IJxT+npf4ci51giVs+dGFmR8HgaiGLyqV6YZ7BQkTXoCLF70/5Rqk3G4xhNS38AjSgMqCP/RZbrNVQ7OqcTzuFZHaZ7zQ84ZqLmX4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 840661BB0; Fri, 5 Dec 2025 14:00:42 -0800 (PST) Received: from merodach.members.linode.com (usa-sjc-mx-foss1.foss.arm.com [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 2363F3F740; Fri, 5 Dec 2025 14:00:46 -0800 (PST) From: James Morse To: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: James Morse , D Scott Phillips OS , carl@os.amperecomputing.com, lcherian@marvell.com, bobo.shaobowang@huawei.com, tan.shaopeng@fujitsu.com, baolin.wang@linux.alibaba.com, Jamie Iles , Xin Hao , peternewman@google.com, dfustini@baylibre.com, amitsinght@marvell.com, David Hildenbrand , Dave Martin , Koba Ko , Shanker Donthineni , fenghuay@nvidia.com, baisheng.gao@unisoc.com, Jonathan Cameron , Gavin Shan , Ben Horgan , rohit.mathew@arm.com, reinette.chatre@intel.com, Punit Agrawal Subject: [RFC PATCH 20/38] arm_mpam: resctrl: Pre-allocate free running monitors Date: Fri, 5 Dec 2025 21:58:43 +0000 Message-Id: <20251205215901.17772-21-james.morse@arm.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20251205215901.17772-1-james.morse@arm.com> References: <20251205215901.17772-1-james.morse@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" When there are enough monitors, the resctrl mbm local and total files can be exposed. These need all the monitors that resctrl may use to be allocated up front. Add helpers to do this. If a different candidate class is discovered, the old array should be free'd and the allocated monitors returned to the driver. Signed-off-by: James Morse --- drivers/resctrl/mpam_internal.h | 8 +++- drivers/resctrl/mpam_resctrl.c | 84 ++++++++++++++++++++++++++++++++- 2 files changed, 89 insertions(+), 3 deletions(-) diff --git a/drivers/resctrl/mpam_internal.h b/drivers/resctrl/mpam_interna= l.h index 0984ac32f303..b7c914febeb4 100644 --- a/drivers/resctrl/mpam_internal.h +++ b/drivers/resctrl/mpam_internal.h @@ -359,7 +359,13 @@ struct mpam_resctrl_res { struct mpam_resctrl_mon { struct mpam_class *class; =20 - /* per-class data that resctrl needs will live here */ + /* + * Array of allocated MBWU monitors, indexed by (closid, rmid). + * When ABMC is not in use, this array directly maps (closid, rmid) + * to the allocated monitor. Otherwise this array is sparse, and + * un-assigned (closid, rmid) are -1. + */ + int *mbwu_idx_to_mon; }; =20 static inline int mpam_alloc_csu_mon(struct mpam_class *class) diff --git a/drivers/resctrl/mpam_resctrl.c b/drivers/resctrl/mpam_resctrl.c index 9978eb48c1f4..de5220fed97d 100644 --- a/drivers/resctrl/mpam_resctrl.c +++ b/drivers/resctrl/mpam_resctrl.c @@ -559,10 +559,58 @@ static void mpam_resctrl_pick_mba(void) } } =20 +static void __free_mbwu_mon(struct mpam_class *class, int *array, + u16 num_mbwu_mon) +{ + for (int i =3D 0; i < num_mbwu_mon; i++) { + if (array[i] < 0) + continue; + + mpam_free_mbwu_mon(class, array[i]); + array[i] =3D ~0; + } +} + +static int __alloc_mbwu_mon(struct mpam_class *class, int *array, + u16 num_mbwu_mon) +{ + for (int i =3D 0; i < num_mbwu_mon; i++) { + int mbwu_mon =3D mpam_alloc_mbwu_mon(class); + + if (mbwu_mon < 0) { + __free_mbwu_mon(class, array, num_mbwu_mon); + return mbwu_mon; + } + array[i] =3D mbwu_mon; + } + + return 0; +} + +static int *__alloc_mbwu_array(struct mpam_class *class, u16 num_mbwu_mon) +{ + int err; + size_t array_size =3D num_mbwu_mon * sizeof(int); + int *array __free(kfree) =3D kmalloc(array_size, GFP_KERNEL); + + if (!array) + return ERR_PTR(-ENOMEM); + + memset(array, -1, array_size); + + err =3D __alloc_mbwu_mon(class, array, num_mbwu_mon); + if (err) + return ERR_PTR(err); + return_ptr(array); +} + static void counter_update_class(enum resctrl_event_id evt_id, struct mpam_class *class) { - struct mpam_class *existing_class =3D mpam_resctrl_counters[evt_id].class; + struct mpam_resctrl_mon *mon =3D &mpam_resctrl_counters[evt_id]; + struct mpam_class *existing_class =3D mon->class; + u16 num_mbwu_mon =3D class->props.num_mbwu_mon; + int *existing_array =3D mon->mbwu_idx_to_mon; =20 if (existing_class) { if (class->level =3D=3D 3) { @@ -575,8 +623,40 @@ static void counter_update_class(enum resctrl_event_id= evt_id, } } =20 - mpam_resctrl_counters[evt_id].class =3D class; + pr_debug("Updating event %u to use class %u\n", evt_id, class->level); + mon->class =3D class; exposed_mon_capable =3D true; + + if (evt_id =3D=3D QOS_L3_OCCUP_EVENT_ID) + return; + + /* Might not need all the monitors */ + num_mbwu_mon =3D __mpam_monitors_free_running(num_mbwu_mon); + if (!num_mbwu_mon) { + pr_debug("Not pre-allocating free-running counters\n"); + return; + } + + /* + * This is the pre-allocated free-running monitors path. It always + * allocates one monitor per PARTID * PMG. + */ + WARN_ON_ONCE(num_mbwu_mon !=3D resctrl_arch_system_num_rmid_idx()); + + mon->mbwu_idx_to_mon =3D __alloc_mbwu_array(class, num_mbwu_mon); + if (IS_ERR(mon->mbwu_idx_to_mon)) { + pr_debug("Failed to allocate MBWU array\n"); + mon->class =3D existing_class; + mon->mbwu_idx_to_mon =3D existing_array; + return; + } + + if (existing_array) { + pr_debug("Releasing previous class %u's monitors\n", + existing_class->level); + __free_mbwu_mon(existing_class, existing_array, num_mbwu_mon); + kfree(existing_array); + } } =20 static void mpam_resctrl_pick_counters(void) --=20 2.39.5 From nobody Tue Dec 16 07:34:20 2025 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id ACCAA2FB0BA for ; Fri, 5 Dec 2025 22:00:54 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764972056; cv=none; b=N0W4UPd4hShlBpYOCWfkwCmFYrtI5sYlWpC0vfPUGlhVI6FZa/4tg7lCxU7aD1/z/b2yz203GFvmb5AMwJOo8+hX799gxMNp4pSNQEfsCO/R0yJSktOs5trkXrF3suQBPOuDM5aVtAkLbaFjQXIochW/o9HYIuUnJSpD9V1+Lc8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764972056; c=relaxed/simple; bh=M36nzOwEzA3vLt0eIAN/IpRFOFrQ5CZJ2CGSb3OPKeE=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=j2gWtQm9+ubkOTcslEmO4p0PMtF0ElF5IJeDp6aQtjM+cPZI7IP6srRccaBpKxUCtzQkVBHhZDi4OUFsIB0Lk2ox2aQgacOI+WRLeeuhdDg/BRUtxW+c1qxen+C40ZcbohuJD7RPKGotumaDnrCmyqkmvLDCqhgxVmlDVsbANWg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 8C9D41BA8; Fri, 5 Dec 2025 14:00:46 -0800 (PST) Received: from merodach.members.linode.com (usa-sjc-mx-foss1.foss.arm.com [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 2B1383F740; Fri, 5 Dec 2025 14:00:50 -0800 (PST) From: James Morse To: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: James Morse , D Scott Phillips OS , carl@os.amperecomputing.com, lcherian@marvell.com, bobo.shaobowang@huawei.com, tan.shaopeng@fujitsu.com, baolin.wang@linux.alibaba.com, Jamie Iles , Xin Hao , peternewman@google.com, dfustini@baylibre.com, amitsinght@marvell.com, David Hildenbrand , Dave Martin , Koba Ko , Shanker Donthineni , fenghuay@nvidia.com, baisheng.gao@unisoc.com, Jonathan Cameron , Gavin Shan , Ben Horgan , rohit.mathew@arm.com, reinette.chatre@intel.com, Punit Agrawal Subject: [RFC PATCH 21/38] arm_mpam: resctrl: Pre-allocate assignable monitors Date: Fri, 5 Dec 2025 21:58:44 +0000 Message-Id: <20251205215901.17772-22-james.morse@arm.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20251205215901.17772-1-james.morse@arm.com> References: <20251205215901.17772-1-james.morse@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" When there are not enough monitors, MPAM is able to emulate ABMC by making a smaller number of monitors assignable. These monitors still need to be allocated from the driver, and mapped to whichever control/monitor group resctrl wants to use them with. Add a second array to hold the monitor values indexed by resctrl's cntr_id. When CDP is in use, two monitors are needed so the available number of counters halves. Platforms with one monitor will have zero monitors when CDP is in use. Signed-off-by: James Morse --- drivers/resctrl/mpam_internal.h | 7 +++ drivers/resctrl/mpam_resctrl.c | 102 ++++++++++++++++++++++++++++++++ 2 files changed, 109 insertions(+) diff --git a/drivers/resctrl/mpam_internal.h b/drivers/resctrl/mpam_interna= l.h index b7c914febeb4..05101186af17 100644 --- a/drivers/resctrl/mpam_internal.h +++ b/drivers/resctrl/mpam_internal.h @@ -366,6 +366,13 @@ struct mpam_resctrl_mon { * un-assigned (closid, rmid) are -1. */ int *mbwu_idx_to_mon; + + /* + * Array of assigned MBWU monitors, indexed by idx argument. + * When ABMC is not in use, this array can be NULL. Otherwise + * it maps idx to the allocated monitor. + */ + int *assigned_counters; }; =20 static inline int mpam_alloc_csu_mon(struct mpam_class *class) diff --git a/drivers/resctrl/mpam_resctrl.c b/drivers/resctrl/mpam_resctrl.c index de5220fed97d..f607feaf0126 100644 --- a/drivers/resctrl/mpam_resctrl.c +++ b/drivers/resctrl/mpam_resctrl.c @@ -50,6 +50,12 @@ static bool exposed_mon_capable; */ static bool cdp_enabled; =20 +/* + * L3 local/total may come from different classes - what is the number of = MBWU + * 'on L3'? + */ +static unsigned int l3_num_allocated_mbwu =3D ~0; + /* Whether this num_mbw_mon could result in a free_running system */ static int __mpam_monitors_free_running(u16 num_mbwu_mon) { @@ -58,6 +64,15 @@ static int __mpam_monitors_free_running(u16 num_mbwu_mon) return 0; } =20 +/* + * If l3_num_allocated_mbwu is forced below PARTID * PMG, then the counters + * are not free running, and ABMC's user-interface must be used to assign = them. + */ +static bool mpam_resctrl_abmc_enabled(void) +{ + return l3_num_allocated_mbwu < resctrl_arch_system_num_rmid_idx(); +} + bool resctrl_arch_alloc_capable(void) { return exposed_alloc_capable; @@ -102,8 +117,25 @@ static void resctrl_reset_task_closids(void) read_unlock(&tasklist_lock); } =20 +static void mpam_resctrl_monitor_sync_abmc_vals(struct rdt_resource *l3) +{ + l3->mon.num_mbm_cntrs =3D l3_num_allocated_mbwu; + if (cdp_enabled) + l3->mon.num_mbm_cntrs /=3D 2; + + if (l3->mon.num_mbm_cntrs) { + l3->mon.mbm_cntr_assignable =3D mpam_resctrl_abmc_enabled(); + l3->mon.mbm_assign_on_mkdir =3D mpam_resctrl_abmc_enabled(); + } else { + l3->mon.mbm_cntr_assignable =3D false; + l3->mon.mbm_assign_on_mkdir =3D false; + } +} + int resctrl_arch_set_cdp_enabled(enum resctrl_res_level ignored, bool enab= le) { + struct mpam_resctrl_res *res =3D &mpam_resctrl_controls[RDT_RESOURCE_L3]; + struct rdt_resource *l3 =3D &res->resctrl_res; u32 partid_i, partid_d; =20 cdp_enabled =3D enable; @@ -120,6 +152,7 @@ int resctrl_arch_set_cdp_enabled(enum resctrl_res_level= ignored, bool enable) WRITE_ONCE(arm64_mpam_global_default, mpam_get_regval(current)); =20 resctrl_reset_task_closids(); + mpam_resctrl_monitor_sync_abmc_vals(l3); =20 return 0; } @@ -315,6 +348,11 @@ static bool class_has_usable_mbwu(struct mpam_class *c= lass) return true; } =20 + if (cprops->num_mbwu_mon) { + pr_debug("monitors usable via ABMC assignment\n"); + return true; + } + return false; } =20 @@ -584,6 +622,8 @@ static int __alloc_mbwu_mon(struct mpam_class *class, i= nt *array, array[i] =3D mbwu_mon; } =20 + l3_num_allocated_mbwu =3D min(l3_num_allocated_mbwu, num_mbwu_mon); + return 0; } =20 @@ -727,6 +767,23 @@ static void mpam_resctrl_pick_counters(void) mpam_resctrl_counters[QOS_L3_MBM_TOTAL_EVENT_ID].class); } =20 +bool resctrl_arch_mbm_cntr_assign_enabled(struct rdt_resource *r) +{ + if (r !=3D &mpam_resctrl_controls[RDT_RESOURCE_L3].resctrl_res) + return false; + + return mpam_resctrl_abmc_enabled(); +} + +int resctrl_arch_mbm_cntr_assign_set(struct rdt_resource *r, bool enable) +{ + lockdep_assert_cpus_held(); + + WARN_ON_ONCE(1); + + return 0; +} + static int mpam_resctrl_control_init(struct mpam_resctrl_res *res, enum resctrl_res_level type) { @@ -806,6 +863,41 @@ static int mpam_resctrl_pick_domain_id(int cpu, struct= mpam_component *comp) return comp->comp_id; } =20 +/* + * This must run after all event counters have been picked so that any free + * running counters have already been allocated. + */ +static int mpam_resctrl_monitor_init_abmc(struct mpam_resctrl_mon *mon) +{ + struct mpam_resctrl_res *res =3D &mpam_resctrl_controls[RDT_RESOURCE_L3]; + size_t array_size =3D resctrl_arch_system_num_rmid_idx() * sizeof(int); + int *rmid_array __free(kfree) =3D kmalloc(array_size, GFP_KERNEL); + struct rdt_resource *l3 =3D &res->resctrl_res; + struct mpam_class *class =3D mon->class; + u16 num_mbwu_mon; + + if (mon->mbwu_idx_to_mon) { + pr_debug("monitors free running\n"); + return 0; + } + + if (!rmid_array) { + pr_debug("Failed to allocate RMID array\n"); + return -ENOMEM; + } + memset(rmid_array, -1, array_size); + + num_mbwu_mon =3D class->props.num_mbwu_mon; + mon->assigned_counters =3D __alloc_mbwu_array(mon->class, num_mbwu_mon); + if (IS_ERR(mon->assigned_counters)) + return PTR_ERR(mon->assigned_counters); + mon->mbwu_idx_to_mon =3D no_free_ptr(rmid_array); + + mpam_resctrl_monitor_sync_abmc_vals(l3); + + return 0; +} + static void mpam_resctrl_monitor_init(struct mpam_resctrl_mon *mon, enum resctrl_event_id type) { @@ -847,6 +939,16 @@ static void mpam_resctrl_monitor_init(struct mpam_resc= trl_mon *mon, * space. */ l3->mon.num_rmid =3D 1; + + switch (type) { + case QOS_L3_MBM_LOCAL_EVENT_ID: + case QOS_L3_MBM_TOTAL_EVENT_ID: + mpam_resctrl_monitor_init_abmc(mon); + + return; + default: + return; + } } } =20 --=20 2.39.5 From nobody Tue Dec 16 07:34:20 2025 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 881C32FCBE3 for ; Fri, 5 Dec 2025 22:00:58 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764972060; cv=none; b=LO9iv2+8g2kikw/an6PZN3NIBR5iB+WyIlculQ2AXCmc5iHeR7OFxyE/BvQqNZzbANoY7IcpESCRsp1kHgzOopRCv0nLlYDyS+8Ujxc5sJI+jmUSPZwk11mDXiDiMZTBmpKavpTca6rPzMcM7P3GLFtpTrv86lHRIIK3XyZRJEI= ARC-Message-Signature: i=1; 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Fri, 5 Dec 2025 14:00:54 -0800 (PST) From: James Morse To: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: James Morse , D Scott Phillips OS , carl@os.amperecomputing.com, lcherian@marvell.com, bobo.shaobowang@huawei.com, tan.shaopeng@fujitsu.com, baolin.wang@linux.alibaba.com, Jamie Iles , Xin Hao , peternewman@google.com, dfustini@baylibre.com, amitsinght@marvell.com, David Hildenbrand , Dave Martin , Koba Ko , Shanker Donthineni , fenghuay@nvidia.com, baisheng.gao@unisoc.com, Jonathan Cameron , Gavin Shan , Ben Horgan , rohit.mathew@arm.com, reinette.chatre@intel.com, Punit Agrawal Subject: [RFC PATCH 22/38] arm_mpam: resctrl: Add kunit test for ABMC/CDP interactions Date: Fri, 5 Dec 2025 21:58:45 +0000 Message-Id: <20251205215901.17772-23-james.morse@arm.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20251205215901.17772-1-james.morse@arm.com> References: <20251205215901.17772-1-james.morse@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" ABMC exposes a fun corner case where a platform with one monitor can use ABMC for assignable counters - but not when CDP is enabled. Add some tests. Signed-off-by: James Morse --- drivers/resctrl/test_mpam_resctrl.c | 62 +++++++++++++++++++++++++++++ 1 file changed, 62 insertions(+) diff --git a/drivers/resctrl/test_mpam_resctrl.c b/drivers/resctrl/test_mpa= m_resctrl.c index d0615aa7671c..c83d54f21fa0 100644 --- a/drivers/resctrl/test_mpam_resctrl.c +++ b/drivers/resctrl/test_mpam_resctrl.c @@ -293,6 +293,67 @@ static void test_percent_to_max_rounding(struct kunit = *test) KUNIT_EXPECT_LE(test, 4 * num_rounded_up, 3 * total); } =20 +static void test_num_assignable_counters(struct kunit *test) +{ + unsigned int orig_l3_num_allocated_mbwu =3D l3_num_allocated_mbwu; + u32 orig_mpam_partid_max =3D mpam_partid_max; + u32 orig_mpam_pmg_max =3D mpam_pmg_max; + bool orig_cdp_enabled =3D cdp_enabled; + struct rdt_resource fake_l3; + + /* Force there to be some PARTID/PMG */ + mpam_partid_max =3D 3; + mpam_pmg_max =3D 1; + + cdp_enabled =3D false; + + /* ABMC off, CDP off */ + l3_num_allocated_mbwu =3D resctrl_arch_system_num_rmid_idx(); + mpam_resctrl_monitor_sync_abmc_vals(&fake_l3); + KUNIT_EXPECT_EQ(test, fake_l3.mon.num_mbm_cntrs, resctrl_arch_system_num_= rmid_idx()); + KUNIT_EXPECT_FALSE(test, fake_l3.mon.mbm_cntr_assignable); + KUNIT_EXPECT_FALSE(test, fake_l3.mon.mbm_assign_on_mkdir); + + /* ABMC on, CDP off */ + l3_num_allocated_mbwu =3D 4; + mpam_resctrl_monitor_sync_abmc_vals(&fake_l3); + KUNIT_EXPECT_EQ(test, fake_l3.mon.num_mbm_cntrs, 4); + KUNIT_EXPECT_TRUE(test, fake_l3.mon.mbm_cntr_assignable); + KUNIT_EXPECT_TRUE(test, fake_l3.mon.mbm_assign_on_mkdir); + + cdp_enabled =3D true; + + /* ABMC off, CDP on */ + l3_num_allocated_mbwu =3D resctrl_arch_system_num_rmid_idx(); + mpam_resctrl_monitor_sync_abmc_vals(&fake_l3); + + /* (value not consumed by resctrl) */ + KUNIT_EXPECT_EQ(test, fake_l3.mon.num_mbm_cntrs, resctrl_arch_system_num_= rmid_idx() / 2); + + KUNIT_EXPECT_FALSE(test, fake_l3.mon.mbm_cntr_assignable); + KUNIT_EXPECT_FALSE(test, fake_l3.mon.mbm_assign_on_mkdir); + + /* ABMC on, CDP on */ + l3_num_allocated_mbwu =3D 4; + mpam_resctrl_monitor_sync_abmc_vals(&fake_l3); + KUNIT_EXPECT_EQ(test, fake_l3.mon.num_mbm_cntrs, 2); + KUNIT_EXPECT_TRUE(test, fake_l3.mon.mbm_cntr_assignable); + KUNIT_EXPECT_TRUE(test, fake_l3.mon.mbm_assign_on_mkdir); + + /* ABMC 'on', CDP on - but not enough counters */ + l3_num_allocated_mbwu =3D 1; + mpam_resctrl_monitor_sync_abmc_vals(&fake_l3); + KUNIT_EXPECT_EQ(test, fake_l3.mon.num_mbm_cntrs, 0); + KUNIT_EXPECT_FALSE(test, fake_l3.mon.mbm_cntr_assignable); + KUNIT_EXPECT_FALSE(test, fake_l3.mon.mbm_assign_on_mkdir); + + /* Restore global variables that were messed with */ + l3_num_allocated_mbwu =3D orig_l3_num_allocated_mbwu; + mpam_partid_max =3D orig_mpam_partid_max; + mpam_pmg_max =3D orig_mpam_pmg_max; + cdp_enabled =3D orig_cdp_enabled; +} + static struct kunit_case mpam_resctrl_test_cases[] =3D { KUNIT_CASE(test_get_mba_granularity), KUNIT_CASE_PARAM(test_mbw_max_to_percent, test_percent_value_gen_params), @@ -301,6 +362,7 @@ static struct kunit_case mpam_resctrl_test_cases[] =3D { KUNIT_CASE(test_percent_to_max_rounding), KUNIT_CASE_PARAM(test_percent_max_roundtrip_stability, test_all_bwa_wd_gen_params), + KUNIT_CASE(test_num_assignable_counters), {} }; =20 --=20 2.39.5 From nobody Tue Dec 16 07:34:20 2025 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 26AE22E6CDB for ; Fri, 5 Dec 2025 22:01:02 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764972064; cv=none; b=A4eOrTNfg4O6A1lSqsAdvYW9kYRV7TkpDiJ6kuonuDAADAcbtMc9KhbI6QepIdrW8iaVdxWgbcM1Uk7gALgZKV2W1sqAfezRTcQhx/fkWkH2NQrdP+NdGuSaLJ/dMRlsBEHzA052JNt7VMFcoJy0kqIYH5FefXxaHSVX6c2VRR4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764972064; c=relaxed/simple; bh=UBLZKrHtHi1V26lGVMB6TenhnDqartokqPsHphy0iWI=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=CGnm6wbz4FbiRq3SplDdwCvLiSumgJhzxXjwf9Xk3iN+Vm0AaqtPYUEW2qe3wus5uui2bXTMHqYFrLjA+q2yWLefufkgzzAWwtBOD0kRwiQIwxhFMPaduwiyKPaJ9NJmhWRiboZyNB5DqxpXVDKpdjKufurprKPXIJD9TJ/B/DI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id A62B81A25; Fri, 5 Dec 2025 14:00:54 -0800 (PST) Received: from merodach.members.linode.com (usa-sjc-mx-foss1.foss.arm.com [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 41FCB3F740; Fri, 5 Dec 2025 14:00:58 -0800 (PST) From: James Morse To: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: James Morse , D Scott Phillips OS , carl@os.amperecomputing.com, lcherian@marvell.com, bobo.shaobowang@huawei.com, tan.shaopeng@fujitsu.com, baolin.wang@linux.alibaba.com, Jamie Iles , Xin Hao , peternewman@google.com, dfustini@baylibre.com, amitsinght@marvell.com, David Hildenbrand , Dave Martin , Koba Ko , Shanker Donthineni , fenghuay@nvidia.com, baisheng.gao@unisoc.com, Jonathan Cameron , Gavin Shan , Ben Horgan , rohit.mathew@arm.com, reinette.chatre@intel.com, Punit Agrawal Subject: [RFC PATCH 23/38] arm_mpam: resctrl: Add resctrl_arch_config_cntr() for ABMC use Date: Fri, 5 Dec 2025 21:58:46 +0000 Message-Id: <20251205215901.17772-24-james.morse@arm.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20251205215901.17772-1-james.morse@arm.com> References: <20251205215901.17772-1-james.morse@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" ABMC has a helper resctrl_arch_config_cntr() for changing the mapping between 'cntr_id' and a CLOSID/RMID pair. Add the helper. For MPAM this is done by updating the mon->mbwu_idx_to_mon[] array, and as usual CDP means it needs doing in three different ways. Signed-off-by: James Morse --- drivers/resctrl/mpam_resctrl.c | 37 ++++++++++++++++++++++++++++++++++ 1 file changed, 37 insertions(+) diff --git a/drivers/resctrl/mpam_resctrl.c b/drivers/resctrl/mpam_resctrl.c index f607feaf0126..22ad5dd3c383 100644 --- a/drivers/resctrl/mpam_resctrl.c +++ b/drivers/resctrl/mpam_resctrl.c @@ -767,6 +767,43 @@ static void mpam_resctrl_pick_counters(void) mpam_resctrl_counters[QOS_L3_MBM_TOTAL_EVENT_ID].class); } =20 +static void __config_cntr(struct mpam_resctrl_mon *mon, u32 cntr_id, + enum resctrl_conf_type cdp_type, u32 closid, u32 rmid, + bool assign) +{ + u32 mbwu_idx, mon_idx =3D resctrl_get_config_index(cntr_id, cdp_type); + + closid =3D resctrl_get_config_index(closid, cdp_type); + mbwu_idx =3D resctrl_arch_rmid_idx_encode(closid, rmid); + WARN_ON_ONCE(mon_idx > l3_num_allocated_mbwu); + + if (assign) + mon->mbwu_idx_to_mon[mbwu_idx] =3D mon->assigned_counters[mon_idx]; + else + mon->mbwu_idx_to_mon[mbwu_idx] =3D -1; +} + +void resctrl_arch_config_cntr(struct rdt_resource *r, struct rdt_mon_domai= n *d, + enum resctrl_event_id evtid, u32 rmid, u32 closid, + u32 cntr_id, bool assign) +{ + struct mpam_resctrl_mon *mon =3D &mpam_resctrl_counters[evtid]; + + if (!mon->mbwu_idx_to_mon || !mon->assigned_counters) { + pr_debug("monitor arrays not allocated\n"); + return; + } + + if (cdp_enabled) { + __config_cntr(mon, cntr_id, CDP_CODE, closid, rmid, assign); + __config_cntr(mon, cntr_id, CDP_DATA, closid, rmid, assign); + } else { + __config_cntr(mon, cntr_id, CDP_NONE, closid, rmid, assign); + } + + resctrl_arch_reset_rmid(r, d, closid, rmid, evtid); +} + bool resctrl_arch_mbm_cntr_assign_enabled(struct rdt_resource *r) { if (r !=3D &mpam_resctrl_controls[RDT_RESOURCE_L3].resctrl_res) --=20 2.39.5 From nobody Tue Dec 16 07:34:20 2025 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 18C7B2DBF45 for ; Fri, 5 Dec 2025 22:01:06 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764972068; cv=none; b=DFNBpNnKnA40YaGuIcoDs4rjDPvTF6Dy/q7CkYD9X5LSkbYwIvIKAYp+blSgvfGz07fh9Lu+1/yxBwExUvepvA5kLCFyXbM5C2rB+Tz2b6/1qB9N5irS3KlFcYfaLQ/dAtkXHbHLhDRa9j+XBI/C+JW5TObPnCaeagkpwsqhIws= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764972068; c=relaxed/simple; bh=EPm4zXEcn1HNjJPcJWC9poG5x/fikXJNRttL+pN2tqA=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=ED+eF6iMAE2XzElsM3iHogyG9zdrO/91SUg0AHjJF1VSdTj3Ericdiz7c3qE496BLEc4CnovBcUYzef6gJL9ElfPG3CPrMnmTMAgu5RQEEy0miUzN0utcUAkd8zE7xIiMQywDmVs8EQzSwp/6KgvazXotQEbnHUW/ZI+0yP6vnE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id B28E21BA8; Fri, 5 Dec 2025 14:00:58 -0800 (PST) Received: from merodach.members.linode.com (usa-sjc-mx-foss1.foss.arm.com [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 4E9B53F740; Fri, 5 Dec 2025 14:01:02 -0800 (PST) From: James Morse To: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: James Morse , D Scott Phillips OS , carl@os.amperecomputing.com, lcherian@marvell.com, bobo.shaobowang@huawei.com, tan.shaopeng@fujitsu.com, baolin.wang@linux.alibaba.com, Jamie Iles , Xin Hao , peternewman@google.com, dfustini@baylibre.com, amitsinght@marvell.com, David Hildenbrand , Dave Martin , Koba Ko , Shanker Donthineni , fenghuay@nvidia.com, baisheng.gao@unisoc.com, Jonathan Cameron , Gavin Shan , Ben Horgan , rohit.mathew@arm.com, reinette.chatre@intel.com, Punit Agrawal Subject: [RFC PATCH 24/38] arm_mpam: resctrl: Allow resctrl to allocate monitors Date: Fri, 5 Dec 2025 21:58:47 +0000 Message-Id: <20251205215901.17772-25-james.morse@arm.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20251205215901.17772-1-james.morse@arm.com> References: <20251205215901.17772-1-james.morse@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" When resctrl wants to read a domain's 'QOS_L3_OCCUP', it needs to allocate a monitor on the corresponding resource. Monitors are allocated by class instead of component. MBM monitors are much more complicated, if there are enough monitors, they will be pre-allocated and free-running. If ABMC is in use instead then 'some' are pre-allocated in a different way, and need assigning. Add helpers to allocate a CSU monitor. These helper return an out of range value for MBM counters. Allocating a montitor context is expected to block until hardware resources become available. This only makes sense for QOS_L3_OCCUP as unallocated MBM counters are losing data. Signed-off-by: James Morse --- Since ABMC got merged it may be possible to remove the monitor alloc call for MBM counters from resctrl as this work is now done by ABMC's assign call. --- drivers/resctrl/mpam_internal.h | 14 ++++++- drivers/resctrl/mpam_resctrl.c | 68 +++++++++++++++++++++++++++++++++ include/linux/arm_mpam.h | 4 ++ 3 files changed, 85 insertions(+), 1 deletion(-) diff --git a/drivers/resctrl/mpam_internal.h b/drivers/resctrl/mpam_interna= l.h index 05101186af17..3a68ebd498fa 100644 --- a/drivers/resctrl/mpam_internal.h +++ b/drivers/resctrl/mpam_internal.h @@ -32,6 +32,14 @@ DECLARE_STATIC_KEY_FALSE(mpam_enabled); #define PACKED_FOR_KUNIT #endif =20 +/* + * This 'mon' values must not alias an actual monitor, so must be larger t= han + * U16_MAX, but not be confused with an errno value, so smaller than + * (u32)-SZ_4K. + * USE_PRE_ALLOCATED is used to avoid confusion with an actual monitor. + */ +#define USE_PRE_ALLOCATED (U16_MAX + 1) + static inline bool mpam_is_enabled(void) { return static_branch_likely(&mpam_enabled); @@ -215,7 +223,11 @@ enum mon_filter_options { }; =20 struct mon_cfg { - u16 mon; + /* + * mon must be large enough to hold out of range values like + * USE_RMID_IDX + */ + u32 mon; u8 pmg; bool match_pmg; bool csu_exclude_clean; diff --git a/drivers/resctrl/mpam_resctrl.c b/drivers/resctrl/mpam_resctrl.c index 22ad5dd3c383..a2b238d47117 100644 --- a/drivers/resctrl/mpam_resctrl.c +++ b/drivers/resctrl/mpam_resctrl.c @@ -21,6 +21,8 @@ =20 #include "mpam_internal.h" =20 +DECLARE_WAIT_QUEUE_HEAD(resctrl_mon_ctx_waiters); + /* * The classes we've picked to map to resctrl resources, wrapped * in with their resctrl structure. @@ -287,6 +289,72 @@ struct rdt_resource *resctrl_arch_get_resource(enum re= sctrl_res_level l) return &mpam_resctrl_controls[l].resctrl_res; } =20 +static int resctrl_arch_mon_ctx_alloc_no_wait(enum resctrl_event_id evtid) +{ + struct mpam_resctrl_mon *mon =3D &mpam_resctrl_counters[evtid]; + + if (!mon->class) + return -EINVAL; + + switch (evtid) { + case QOS_L3_OCCUP_EVENT_ID: + /* With CDP, one monitor gets used for both code/data reads */ + return mpam_alloc_csu_mon(mon->class); + case QOS_L3_MBM_LOCAL_EVENT_ID: + case QOS_L3_MBM_TOTAL_EVENT_ID: + return USE_PRE_ALLOCATED; + default: + return -EOPNOTSUPP; + } +} + +void *resctrl_arch_mon_ctx_alloc(struct rdt_resource *r, + enum resctrl_event_id evtid) +{ + DEFINE_WAIT(wait); + int *ret; + + ret =3D kmalloc(sizeof(*ret), GFP_KERNEL); + if (!ret) + return ERR_PTR(-ENOMEM); + + do { + prepare_to_wait(&resctrl_mon_ctx_waiters, &wait, + TASK_INTERRUPTIBLE); + *ret =3D resctrl_arch_mon_ctx_alloc_no_wait(evtid); + if (*ret =3D=3D -ENOSPC) + schedule(); + } while (*ret =3D=3D -ENOSPC && !signal_pending(current)); + finish_wait(&resctrl_mon_ctx_waiters, &wait); + + return ret; +} + +static void resctrl_arch_mon_ctx_free_no_wait(enum resctrl_event_id evtid, + u32 mon_idx) +{ + struct mpam_resctrl_mon *mon =3D &mpam_resctrl_counters[evtid]; + + if (!mon->class) + return; + + if (evtid =3D=3D QOS_L3_OCCUP_EVENT_ID) + mpam_free_csu_mon(mon->class, mon_idx); + + wake_up(&resctrl_mon_ctx_waiters); +} + +void resctrl_arch_mon_ctx_free(struct rdt_resource *r, + enum resctrl_event_id evtid, void *arch_mon_ctx) +{ + u32 mon_idx =3D *(u32 *)arch_mon_ctx; + + kfree(arch_mon_ctx); + arch_mon_ctx =3D NULL; + + resctrl_arch_mon_ctx_free_no_wait(evtid, mon_idx); +} + static bool cache_has_usable_cpor(struct mpam_class *class) { struct mpam_props *cprops =3D &class->props; diff --git a/include/linux/arm_mpam.h b/include/linux/arm_mpam.h index 385554ceb452..e1461e32af75 100644 --- a/include/linux/arm_mpam.h +++ b/include/linux/arm_mpam.h @@ -63,6 +63,10 @@ u32 resctrl_arch_rmid_idx_encode(u32 closid, u32 rmid); void resctrl_arch_rmid_idx_decode(u32 idx, u32 *closid, u32 *rmid); u32 resctrl_arch_system_num_rmid_idx(void); =20 +struct rdt_resource; +void *resctrl_arch_mon_ctx_alloc(struct rdt_resource *r, enum resctrl_even= t_id evtid); +void resctrl_arch_mon_ctx_free(struct rdt_resource *r, enum resctrl_event_= id evtid, void *ctx); + /** * mpam_register_requestor() - Register a requestor with the MPAM driver * @partid_max: The maximum PARTID value the requestor can generate. --=20 2.39.5 From nobody Tue Dec 16 07:34:20 2025 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 0A03F2FD7D5 for ; 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dmarc=fail (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id C58E91A32; Fri, 5 Dec 2025 14:01:02 -0800 (PST) Received: from merodach.members.linode.com (usa-sjc-mx-foss1.foss.arm.com [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 60B863F740; Fri, 5 Dec 2025 14:01:06 -0800 (PST) From: James Morse To: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: James Morse , D Scott Phillips OS , carl@os.amperecomputing.com, lcherian@marvell.com, bobo.shaobowang@huawei.com, tan.shaopeng@fujitsu.com, baolin.wang@linux.alibaba.com, Jamie Iles , Xin Hao , peternewman@google.com, dfustini@baylibre.com, amitsinght@marvell.com, David Hildenbrand , Dave Martin , Koba Ko , Shanker Donthineni , fenghuay@nvidia.com, baisheng.gao@unisoc.com, Jonathan Cameron , Gavin Shan , Ben Horgan , rohit.mathew@arm.com, reinette.chatre@intel.com, Punit Agrawal Subject: [RFC PATCH 25/38] arm_mpam: resctrl: Add resctrl_arch_rmid_read() and resctrl_arch_reset_rmid() Date: Fri, 5 Dec 2025 21:58:48 +0000 Message-Id: <20251205215901.17772-26-james.morse@arm.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20251205215901.17772-1-james.morse@arm.com> References: <20251205215901.17772-1-james.morse@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" resctrl uses resctrl_arch_rmid_read() to read counters. CDP emulation means the counter may need reading in three different ways. The same goes for reset. The helpers behind the resctrl_arch_ functions will be re-used for the ABMC equivalent functions. Add the rounding helper for checking monitor values while we're here. Signed-off-by: James Morse --- drivers/resctrl/mpam_resctrl.c | 154 +++++++++++++++++++++++++++++++++ include/linux/arm_mpam.h | 5 ++ 2 files changed, 159 insertions(+) diff --git a/drivers/resctrl/mpam_resctrl.c b/drivers/resctrl/mpam_resctrl.c index a2b238d47117..dc8a819d0976 100644 --- a/drivers/resctrl/mpam_resctrl.c +++ b/drivers/resctrl/mpam_resctrl.c @@ -355,6 +355,160 @@ void resctrl_arch_mon_ctx_free(struct rdt_resource *r, resctrl_arch_mon_ctx_free_no_wait(evtid, mon_idx); } =20 +static int +__read_mon(struct mpam_resctrl_mon *mon, struct mpam_component *mon_comp, + enum mpam_device_features mon_type, + int mon_idx, + enum resctrl_conf_type cdp_type, u32 closid, u32 rmid, u64 *val) +{ + struct mon_cfg cfg =3D { }; + + if (!mpam_is_enabled()) + return -EINVAL; + + /* Shift closid to account for CDP */ + closid =3D resctrl_get_config_index(closid, cdp_type); + + if (mon_idx =3D=3D USE_PRE_ALLOCATED) { + int mbwu_idx =3D resctrl_arch_rmid_idx_encode(closid, rmid); + mon_idx =3D mon->mbwu_idx_to_mon[mbwu_idx]; + if (mon_idx =3D=3D -1) { + if (mpam_resctrl_abmc_enabled()) { + /* Report Unassigned */ + return -ENOENT; + } + /* Report Unavailable */ + return -EINVAL; + } + } + + cfg.mon =3D mon_idx; + cfg.match_pmg =3D true; + cfg.partid =3D closid; + cfg.pmg =3D rmid; + + if (irqs_disabled()) { + /* Check if we can access this domain without an IPI */ + return -EIO; + } + + return mpam_msmon_read(mon_comp, &cfg, mon_type, val); +} + +static int read_mon_cdp_safe(struct mpam_resctrl_mon *mon, struct mpam_com= ponent *mon_comp, + enum mpam_device_features mon_type, + int mon_idx, u32 closid, u32 rmid, u64 *val) +{ + if (cdp_enabled) { + u64 code_val =3D 0, data_val =3D 0; + int err; + + err =3D __read_mon(mon, mon_comp, mon_type, mon_idx, + CDP_CODE, closid, rmid, &code_val); + if (err) + return err; + + err =3D __read_mon(mon, mon_comp, mon_type, mon_idx, + CDP_DATA, closid, rmid, &data_val); + if (!err) + *val +=3D code_val + data_val; + return err; + } + + return __read_mon(mon, mon_comp, mon_type, mon_idx, + CDP_NONE, closid, rmid, val); +} + +/* MBWU when not in ABMC mode, and CSU counters. */ +int resctrl_arch_rmid_read(struct rdt_resource *r, struct rdt_mon_domain *= d, + u32 closid, u32 rmid, enum resctrl_event_id eventid, + u64 *val, void *arch_mon_ctx) +{ + struct mpam_resctrl_dom *l3_dom; + struct mpam_component *mon_comp; + u32 mon_idx =3D *(u32 *)arch_mon_ctx; + enum mpam_device_features mon_type; + struct mpam_resctrl_mon *mon =3D &mpam_resctrl_counters[eventid]; + + resctrl_arch_rmid_read_context_check(); + + if (eventid >=3D QOS_NUM_EVENTS || !mon->class) + return -EINVAL; + + l3_dom =3D container_of(d, struct mpam_resctrl_dom, resctrl_mon_dom); + mon_comp =3D l3_dom->mon_comp[eventid]; + + switch (eventid) { + case QOS_L3_OCCUP_EVENT_ID: + mon_type =3D mpam_feat_msmon_csu; + break; + case QOS_L3_MBM_LOCAL_EVENT_ID: + case QOS_L3_MBM_TOTAL_EVENT_ID: + mon_type =3D mpam_feat_msmon_mbwu; + break; + default: + return -EINVAL; + } + + return read_mon_cdp_safe(mon, mon_comp, mon_type, mon_idx, + closid, rmid, val); +} + +static void __reset_mon(struct mpam_resctrl_mon *mon, struct mpam_componen= t *mon_comp, + int mon_idx, + enum resctrl_conf_type cdp_type, u32 closid, u32 rmid) +{ + struct mon_cfg cfg =3D { }; + + if (!mpam_is_enabled()) + return; + + /* Shift closid to account for CDP */ + closid =3D resctrl_get_config_index(closid, cdp_type); + + if (mon_idx =3D=3D USE_PRE_ALLOCATED) { + int mbwu_idx =3D resctrl_arch_rmid_idx_encode(closid, rmid); + mon_idx =3D mon->mbwu_idx_to_mon[mbwu_idx]; + } + + if (mon_idx =3D=3D -1) + return; + cfg.mon =3D mon_idx; + mpam_msmon_reset_mbwu(mon_comp, &cfg); +} + +static void reset_mon_cdp_safe(struct mpam_resctrl_mon *mon, struct mpam_c= omponent *mon_comp, + int mon_idx, u32 closid, u32 rmid) +{ + if (cdp_enabled) { + __reset_mon(mon, mon_comp, mon_idx, CDP_CODE, closid, rmid); + __reset_mon(mon, mon_comp, mon_idx, CDP_DATA, closid, rmid); + } else { + __reset_mon(mon, mon_comp, mon_idx, CDP_NONE, closid, rmid); + } +} + +/* Called via IPI. Call with read_cpus_lock() held. */ +void resctrl_arch_reset_rmid(struct rdt_resource *r, struct rdt_mon_domain= *d, + u32 closid, u32 rmid, enum resctrl_event_id eventid) +{ + struct mpam_resctrl_dom *l3_dom; + struct mpam_component *mon_comp; + struct mpam_resctrl_mon *mon =3D &mpam_resctrl_counters[eventid]; + + if (!mpam_is_enabled()) + return; + + /* Only MBWU counters are relevant, and for supported event types. */ + if (eventid =3D=3D QOS_L3_OCCUP_EVENT_ID || !mon->class) + return; + + l3_dom =3D container_of(d, struct mpam_resctrl_dom, resctrl_mon_dom); + mon_comp =3D l3_dom->mon_comp[eventid]; + + reset_mon_cdp_safe(mon, mon_comp, USE_PRE_ALLOCATED, closid, rmid); +} + static bool cache_has_usable_cpor(struct mpam_class *class) { struct mpam_props *cprops =3D &class->props; diff --git a/include/linux/arm_mpam.h b/include/linux/arm_mpam.h index e1461e32af75..86d5e326d2bd 100644 --- a/include/linux/arm_mpam.h +++ b/include/linux/arm_mpam.h @@ -67,6 +67,11 @@ struct rdt_resource; void *resctrl_arch_mon_ctx_alloc(struct rdt_resource *r, enum resctrl_even= t_id evtid); void resctrl_arch_mon_ctx_free(struct rdt_resource *r, enum resctrl_event_= id evtid, void *ctx); =20 +static inline unsigned int resctrl_arch_round_mon_val(unsigned int val) +{ + return val; +} + /** * mpam_register_requestor() - Register a requestor with the MPAM driver * @partid_max: The maximum PARTID value the requestor can generate. --=20 2.39.5 From nobody Tue Dec 16 07:34:20 2025 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id DEA342FE585 for ; Fri, 5 Dec 2025 22:01:14 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764972076; cv=none; b=Y2WnzWb01/PXLiFo811XGq+ykT0QeQmppja5TT9R2gcMw8UPDsgINhMiwloJY13SNTw1eF3e9HA8RHth2/6V/dpGdTfCsIdUJXq5mIapdHsIvZ3EuyMqFpAdc+i8URZlkBshkh5a97qoX4Z6BGiv3bgM9ngZ+5rkrfH/27ic8Uo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764972076; c=relaxed/simple; bh=5Ymt2AMKHk4CKCow414PzZ8bYi7EcNfN3ULWEK5rG3g=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=rFY14tGCqbMUx6xYLYqPbzQ+OSww7Wti/uw2ZWajQFOevd0fFLRAT/jB08WBlhO7tptwgXDCnBklZs4cs2mMtqa5mMjs5Cf8mPAWhIwcapZjCwGV8TOuw2p7/RHhCJJA2Fino69gR8DE21KztNWA7MtkbeTIFm6o2J6U/vBJh9Q= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id CD1541BC0; Fri, 5 Dec 2025 14:01:06 -0800 (PST) Received: from merodach.members.linode.com (usa-sjc-mx-foss1.foss.arm.com [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 6E1E53F740; Fri, 5 Dec 2025 14:01:10 -0800 (PST) From: James Morse To: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: James Morse , D Scott Phillips OS , carl@os.amperecomputing.com, lcherian@marvell.com, bobo.shaobowang@huawei.com, tan.shaopeng@fujitsu.com, baolin.wang@linux.alibaba.com, Jamie Iles , Xin Hao , peternewman@google.com, dfustini@baylibre.com, amitsinght@marvell.com, David Hildenbrand , Dave Martin , Koba Ko , Shanker Donthineni , fenghuay@nvidia.com, baisheng.gao@unisoc.com, Jonathan Cameron , Gavin Shan , Ben Horgan , rohit.mathew@arm.com, reinette.chatre@intel.com, Punit Agrawal Subject: [RFC PATCH 26/38] arm_mpam: resctrl: Add resctrl_arch_cntr_read() & resctrl_arch_reset_cntr() Date: Fri, 5 Dec 2025 21:58:49 +0000 Message-Id: <20251205215901.17772-27-james.morse@arm.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20251205215901.17772-1-james.morse@arm.com> References: <20251205215901.17772-1-james.morse@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" When used in ABMC mode, resctrl uses a different set of helpers to read and reset the counters. Add these. Signed-off-by: James Morse --- drivers/resctrl/mpam_resctrl.c | 43 ++++++++++++++++++++++++++++++++++ 1 file changed, 43 insertions(+) diff --git a/drivers/resctrl/mpam_resctrl.c b/drivers/resctrl/mpam_resctrl.c index dc8a819d0976..1333dc40714a 100644 --- a/drivers/resctrl/mpam_resctrl.c +++ b/drivers/resctrl/mpam_resctrl.c @@ -454,6 +454,28 @@ int resctrl_arch_rmid_read(struct rdt_resource *r, str= uct rdt_mon_domain *d, closid, rmid, val); } =20 +/* MBWU counters when in ABMC mode */ +int resctrl_arch_cntr_read(struct rdt_resource *r, struct rdt_mon_domain *= d, + u32 closid, u32 rmid, int mon_idx, + enum resctrl_event_id eventid, u64 *val) +{ + struct mpam_resctrl_mon *mon =3D &mpam_resctrl_counters[eventid]; + struct mpam_resctrl_dom *l3_dom; + struct mpam_component *mon_comp; + + if (!mpam_is_enabled()) + return -EINVAL; + + if (eventid =3D=3D QOS_L3_OCCUP_EVENT_ID || !mon->class) + return -EINVAL; + + l3_dom =3D container_of(d, struct mpam_resctrl_dom, resctrl_mon_dom); + mon_comp =3D l3_dom->mon_comp[eventid]; + + return read_mon_cdp_safe(mon, mon_comp, mpam_feat_msmon_mbwu, mon_idx, + closid, rmid, val); +} + static void __reset_mon(struct mpam_resctrl_mon *mon, struct mpam_componen= t *mon_comp, int mon_idx, enum resctrl_conf_type cdp_type, u32 closid, u32 rmid) @@ -509,6 +531,27 @@ void resctrl_arch_reset_rmid(struct rdt_resource *r, s= truct rdt_mon_domain *d, reset_mon_cdp_safe(mon, mon_comp, USE_PRE_ALLOCATED, closid, rmid); } =20 +/* Reset an assigned counter */ +void resctrl_arch_reset_cntr(struct rdt_resource *r, struct rdt_mon_domain= *d, + u32 closid, u32 rmid, int cntr_id, + enum resctrl_event_id eventid) +{ + struct mpam_resctrl_mon *mon =3D &mpam_resctrl_counters[eventid]; + struct mpam_resctrl_dom *l3_dom; + struct mpam_component *mon_comp; + + if (!mpam_is_enabled()) + return; + + if (eventid =3D=3D QOS_L3_OCCUP_EVENT_ID || !mon->class) + return; + + l3_dom =3D container_of(d, struct mpam_resctrl_dom, resctrl_mon_dom); + mon_comp =3D l3_dom->mon_comp[eventid]; + + reset_mon_cdp_safe(mon, mon_comp, USE_PRE_ALLOCATED, closid, rmid); +} + static bool cache_has_usable_cpor(struct mpam_class *class) { struct mpam_props *cprops =3D &class->props; --=20 2.39.5 From nobody Tue Dec 16 07:34:20 2025 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 1E2492FF642 for ; Fri, 5 Dec 2025 22:01:19 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764972080; cv=none; b=I/04ti0o6a9AUMaZS9lnTY+LtoiEll0RHuht7hPVbcbPe1R7Ze2JE8cPAtcIcDM8/B+nRLbDHkhb1upU+axJA9cuwl7D2B146wljhdvOwFwr8DBleHx/YzC+RjyskjCss7N6fGq0BbsLoK8dnxOhhytjp2Gjqrzp9tf6n35kDsQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764972080; c=relaxed/simple; bh=1SjkrpGXk8jc+wWeQb/7D2TAD77rdSK5/1mwkJx7mVc=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=J23TU7sMuyT8WtlMBChRUawGnhikLm8pGa20lhae3atsR6XehRB1mhT97ZH0Q+KhQ0kbCjvYGBEFAT+2vTSvT32DqHqt6DoQ+uBV0sta0IBLv2k5GAK8gRaiT5XpuT5xsLQL1x7XwNQoVO3B2CIhVyR3onqz9TSd0QpDeN24ecs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id D95C81BCA; Fri, 5 Dec 2025 14:01:10 -0800 (PST) Received: from merodach.members.linode.com (usa-sjc-mx-foss1.foss.arm.com [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 75DCF3F740; Fri, 5 Dec 2025 14:01:14 -0800 (PST) From: James Morse To: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: James Morse , D Scott Phillips OS , carl@os.amperecomputing.com, lcherian@marvell.com, bobo.shaobowang@huawei.com, tan.shaopeng@fujitsu.com, baolin.wang@linux.alibaba.com, Jamie Iles , Xin Hao , peternewman@google.com, dfustini@baylibre.com, amitsinght@marvell.com, David Hildenbrand , Dave Martin , Koba Ko , Shanker Donthineni , fenghuay@nvidia.com, baisheng.gao@unisoc.com, Jonathan Cameron , Gavin Shan , Ben Horgan , rohit.mathew@arm.com, reinette.chatre@intel.com, Punit Agrawal Subject: [RFC PATCH 27/38] arm_mpam: resctrl: Add empty definitions for assorted resctrl functions Date: Fri, 5 Dec 2025 21:58:50 +0000 Message-Id: <20251205215901.17772-28-james.morse@arm.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20251205215901.17772-1-james.morse@arm.com> References: <20251205215901.17772-1-james.morse@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" A few resctrl features and hooks need to be provided, but aren't needed or supported on MPAM platforms. resctrl has individual hooks to separately enable and disable the closid/partid and rmid/pmg context switching code. For MPAM this is all the same thing, as the value in struct task_struct is used to cache the value that should be written to hardware. arm64's context switching code is enabled once MPAM is usable, but doesn't touch the hardware unless the value has changed. For now event configuration is not supported, and can be turned off by returning 'false' from resctrl_arch_is_evt_configurable(). Add this, and empty definitions for the other hooks. Signed-off-by: James Morse --- drivers/resctrl/mpam_resctrl.c | 17 +++++++++++++++++ include/linux/arm_mpam.h | 9 +++++++++ 2 files changed, 26 insertions(+) diff --git a/drivers/resctrl/mpam_resctrl.c b/drivers/resctrl/mpam_resctrl.c index 1333dc40714a..00455de3efe9 100644 --- a/drivers/resctrl/mpam_resctrl.c +++ b/drivers/resctrl/mpam_resctrl.c @@ -85,6 +85,23 @@ bool resctrl_arch_mon_capable(void) return exposed_mon_capable; } =20 +bool resctrl_arch_is_evt_configurable(enum resctrl_event_id evt) +{ + return false; +} + +void resctrl_arch_mon_event_config_read(void *info) +{ +} + +void resctrl_arch_mon_event_config_write(void *info) +{ +} + +void resctrl_arch_reset_rmid_all(struct rdt_resource *r, struct rdt_mon_do= main *d) +{ +} + bool resctrl_arch_get_cdp_enabled(enum resctrl_res_level rid) { switch (rid) { diff --git a/include/linux/arm_mpam.h b/include/linux/arm_mpam.h index 86d5e326d2bd..f92a36187a52 100644 --- a/include/linux/arm_mpam.h +++ b/include/linux/arm_mpam.h @@ -67,6 +67,15 @@ struct rdt_resource; void *resctrl_arch_mon_ctx_alloc(struct rdt_resource *r, enum resctrl_even= t_id evtid); void resctrl_arch_mon_ctx_free(struct rdt_resource *r, enum resctrl_event_= id evtid, void *ctx); =20 +/* + * The CPU configuration for MPAM is cheap to write, and is only written i= f it + * has changed. No need for fine grained enables. + */ +static inline void resctrl_arch_enable_mon(void) { } +static inline void resctrl_arch_disable_mon(void) { } +static inline void resctrl_arch_enable_alloc(void) { } +static inline void resctrl_arch_disable_alloc(void) { } + static inline unsigned int resctrl_arch_round_mon_val(unsigned int val) { return val; --=20 2.39.5 From nobody Tue Dec 16 07:34:20 2025 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id B7A192FFDD8 for ; Fri, 5 Dec 2025 22:01:22 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764972084; cv=none; b=QJ5AoafY9bouj2/SiJNPZ4vmGWWzst3llJxFQ6sVdtcJxyt66+yCYZJwJBV9Tmv3FBlaSeF1ILwrPuGKeahyj2iV+pcxibdYStjO4bbsKhT+nXOOQU/rDBfHBr5On+tS/667fpPjefjRbykVv8ZoxM8ft1YxRJirYLT0u9VEYts= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764972084; c=relaxed/simple; bh=SDncmVZpWqRPJvO9Y1gy2vaUf/z9roHOhg8eEqy+8Kc=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=FkB6acq9cVLZg9N6wjK6brhhJMDf/3aK4an9Fp0ALqbtGCwNHsUGG57AwmsF+RTi7mpr3KNc8D4upTuSpoh7pA2pe2bf0jvAso/+sLswSV0SPX5kAK/2Ll+7N50AhQ7QAlf+LgE8ztSAt67GyB12WsZcvLRY7A9iIOC46vj1umw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 0104B1AC1; Fri, 5 Dec 2025 14:01:15 -0800 (PST) Received: from merodach.members.linode.com (usa-sjc-mx-foss1.foss.arm.com [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 810FE3F740; Fri, 5 Dec 2025 14:01:18 -0800 (PST) From: James Morse To: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: James Morse , D Scott Phillips OS , carl@os.amperecomputing.com, lcherian@marvell.com, bobo.shaobowang@huawei.com, tan.shaopeng@fujitsu.com, baolin.wang@linux.alibaba.com, Jamie Iles , Xin Hao , peternewman@google.com, dfustini@baylibre.com, amitsinght@marvell.com, David Hildenbrand , Dave Martin , Koba Ko , Shanker Donthineni , fenghuay@nvidia.com, baisheng.gao@unisoc.com, Jonathan Cameron , Gavin Shan , Ben Horgan , rohit.mathew@arm.com, reinette.chatre@intel.com, Punit Agrawal Subject: [RFC PATCH 28/38] arm64: mpam: Select ARCH_HAS_CPU_RESCTRL Date: Fri, 5 Dec 2025 21:58:51 +0000 Message-Id: <20251205215901.17772-29-james.morse@arm.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20251205215901.17772-1-james.morse@arm.com> References: <20251205215901.17772-1-james.morse@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Enough MPAM support is present to enable ARCH_HAS_CPU_RESCTRL. Let it rip^Wlink! ARCH_HAS_CPU_RESCTRL indicates resctrl can be enabled. It is enabled by the arch code sipmly because it has 'arch' in its name. This removes ARM_CPU_RESCTRL as a mimic of X86_CPU_RESCTRL. While here, move the ACPI dependency to the driver's Kconfig file. Signed-off-by: James Morse --- arch/arm64/Kconfig | 4 ++-- arch/arm64/include/asm/resctrl.h | 2 ++ drivers/resctrl/Kconfig | 9 ++++++++- drivers/resctrl/Makefile | 2 +- 4 files changed, 13 insertions(+), 4 deletions(-) create mode 100644 arch/arm64/include/asm/resctrl.h diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig index 558baa9e7c08..e67885ac7717 100644 --- a/arch/arm64/Kconfig +++ b/arch/arm64/Kconfig @@ -2025,8 +2025,8 @@ config ARM64_TLB_RANGE =20 config ARM64_MPAM bool "Enable support for MPAM" - select ARM64_MPAM_DRIVER if EXPERT # does nothing yet - select ACPI_MPAM if ACPI + select ARM64_MPAM_DRIVER + select ARCH_HAS_CPU_RESCTRL help Memory System Resource Partitioning and Monitoring (MPAM) is an optional extension to the Arm architecture that allows each diff --git a/arch/arm64/include/asm/resctrl.h b/arch/arm64/include/asm/resc= trl.h new file mode 100644 index 000000000000..b506e95cf6e3 --- /dev/null +++ b/arch/arm64/include/asm/resctrl.h @@ -0,0 +1,2 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#include diff --git a/drivers/resctrl/Kconfig b/drivers/resctrl/Kconfig index c808e0470394..672abea3b03c 100644 --- a/drivers/resctrl/Kconfig +++ b/drivers/resctrl/Kconfig @@ -1,6 +1,7 @@ menuconfig ARM64_MPAM_DRIVER bool "MPAM driver" - depends on ARM64 && ARM64_MPAM && EXPERT + depends on ARM64 && ARM64_MPAM + select ACPI_MPAM if ACPI help Memory System Resource Partitioning and Monitoring (MPAM) driver for System IP, e.g. caches and memory controllers. @@ -22,3 +23,9 @@ config MPAM_KUNIT_TEST If unsure, say N. =20 endif + +config ARM64_MPAM_RESCTRL_FS + bool + default y if ARM64_MPAM_DRIVER && RESCTRL_FS + select RESCTRL_RMID_DEPENDS_ON_CLOSID + select RESCTRL_ASSIGN_FIXED diff --git a/drivers/resctrl/Makefile b/drivers/resctrl/Makefile index 40beaf999582..4f6d0e81f9b8 100644 --- a/drivers/resctrl/Makefile +++ b/drivers/resctrl/Makefile @@ -1,5 +1,5 @@ obj-$(CONFIG_ARM64_MPAM_DRIVER) +=3D mpam.o mpam-y +=3D mpam_devices.o -mpam-$(CONFIG_ARM_CPU_RESCTRL) +=3D mpam_resctrl.o +mpam-$(CONFIG_ARM64_MPAM_RESCTRL_FS) +=3D mpam_resctrl.o =20 ccflags-$(CONFIG_ARM64_MPAM_DRIVER_DEBUG) +=3D -DDEBUG --=20 2.39.5 From nobody Tue Dec 16 07:34:20 2025 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 8C70030101D for ; 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dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 0251F1BB2; Fri, 5 Dec 2025 14:01:19 -0800 (PST) Received: from merodach.members.linode.com (usa-sjc-mx-foss1.foss.arm.com [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 868D13F740; Fri, 5 Dec 2025 14:01:22 -0800 (PST) From: James Morse To: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: James Morse , D Scott Phillips OS , carl@os.amperecomputing.com, lcherian@marvell.com, bobo.shaobowang@huawei.com, tan.shaopeng@fujitsu.com, baolin.wang@linux.alibaba.com, Jamie Iles , Xin Hao , peternewman@google.com, dfustini@baylibre.com, amitsinght@marvell.com, David Hildenbrand , Dave Martin , Koba Ko , Shanker Donthineni , fenghuay@nvidia.com, baisheng.gao@unisoc.com, Jonathan Cameron , Gavin Shan , Ben Horgan , rohit.mathew@arm.com, reinette.chatre@intel.com, Punit Agrawal Subject: [RFC PATCH 29/38] arm_mpam: resctrl: Call resctrl_init() on platforms that can support resctrl Date: Fri, 5 Dec 2025 21:58:52 +0000 Message-Id: <20251205215901.17772-30-james.morse@arm.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20251205215901.17772-1-james.morse@arm.com> References: <20251205215901.17772-1-james.morse@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Now that MPAM links against resctrl, call resctrl_init() to register the filesystem and setup resctrl's strutures. Signed-off-by: James Morse --- drivers/resctrl/mpam_resctrl.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/resctrl/mpam_resctrl.c b/drivers/resctrl/mpam_resctrl.c index 00455de3efe9..eb3caee45470 100644 --- a/drivers/resctrl/mpam_resctrl.c +++ b/drivers/resctrl/mpam_resctrl.c @@ -1768,7 +1768,7 @@ int mpam_resctrl_setup(void) pr_warn("Number of PMG is not a power of 2! resctrl may misbehave"); } =20 - /* TODO: call resctrl_init() */ + err =3D resctrl_init(); } =20 return err; --=20 2.39.5 From nobody Tue Dec 16 07:34:20 2025 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id A76F330149B for ; Fri, 5 Dec 2025 22:01:30 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764972092; cv=none; b=Ocro6jT6QdG5qknU9KjxMWHYdytOpy1RPQQDOQSlET5HKbhG+qTk96GuOKuo3WlRKj+Kv5NX6CGv9Y0nout4cok7c2Z0wudhwtNLI4v4hPjI98+JnrQeGpHggNjAtM8GqP4JHeKuhBpcDOUd4SqbQGA/jIWxLy9yRYw4J/0yMWs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764972092; c=relaxed/simple; bh=ujDXU87fvjq7qsS1RSy+zAmyBIzLnNPPC+5zWV02rhk=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=dtIPmepOnU6fJ01cK+OGT3pMchsk6hbCK/QHCYnj4J1ienMZ4kcSu2t5CeotBPzHHLNyqtwhwnJchuqeDsuDyp5SLIagWNFDt6h1RQOq5J6eYtot/P+dhSVbngTa2JiDyEU5a0u5V8IgTa1eXa2XokmxpIB2Xq8tXHz+ZeXi2wc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id EB6F21AC1; Fri, 5 Dec 2025 14:01:22 -0800 (PST) Received: from merodach.members.linode.com (usa-sjc-mx-foss1.foss.arm.com [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 89EBB3F740; Fri, 5 Dec 2025 14:01:26 -0800 (PST) From: James Morse To: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: James Morse , D Scott Phillips OS , carl@os.amperecomputing.com, lcherian@marvell.com, bobo.shaobowang@huawei.com, tan.shaopeng@fujitsu.com, baolin.wang@linux.alibaba.com, Jamie Iles , Xin Hao , peternewman@google.com, dfustini@baylibre.com, amitsinght@marvell.com, David Hildenbrand , Dave Martin , Koba Ko , Shanker Donthineni , fenghuay@nvidia.com, baisheng.gao@unisoc.com, Jonathan Cameron , Gavin Shan , Ben Horgan , rohit.mathew@arm.com, reinette.chatre@intel.com, Punit Agrawal Subject: [RFC PATCH 30/38] arm_mpam: resctrl: Call resctrl_exit() in the event of errors Date: Fri, 5 Dec 2025 21:58:53 +0000 Message-Id: <20251205215901.17772-31-james.morse@arm.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20251205215901.17772-1-james.morse@arm.com> References: <20251205215901.17772-1-james.morse@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" All of MPAMs errors indicate a software bug, e.g. an out-of-bounds partid has been generated. When this happens, the mpam driver is disabled. If resctrl_init() succeeded, also call resctrl_exit() to remove resctrl. mpam_devices.c calls mpam_resctrl_teardown_class() when a class becomes incomplete, and can no longer be used by resctrl. If resctrl was using this class, then resctrl_exit() is called. This in turn removes the kernfs hierarchy from the filesystem and free()s memory that was allocated by resctrl. Signed-off-by: James Morse --- drivers/resctrl/mpam_devices.c | 32 +++++++++++-- drivers/resctrl/mpam_internal.h | 4 ++ drivers/resctrl/mpam_resctrl.c | 80 +++++++++++++++++++++++++++++++++ 3 files changed, 112 insertions(+), 4 deletions(-) diff --git a/drivers/resctrl/mpam_devices.c b/drivers/resctrl/mpam_devices.c index fccebfd980d8..1334093fc03e 100644 --- a/drivers/resctrl/mpam_devices.c +++ b/drivers/resctrl/mpam_devices.c @@ -73,6 +73,14 @@ static DECLARE_WORK(mpam_broken_work, &mpam_disable); /* When mpam is disabled, the printed reason to aid debugging */ static char *mpam_disable_reason; =20 +/* + * Whether resctrl has been setup. Used by cpuhp in preference to + * mpam_is_enabled(). The disable call after an error interrupt makes + * mpam_is_enabled() false before the cpuhp callbacks are made. + * Reads/writes should hold mpam_cpuhp_state_lock, (or be cpuhp callbacks). + */ +static bool mpam_resctrl_enabled; + /* * An MSC is a physical container for controls and monitors, each identifi= ed by * their RIS index. These share a base-address, interrupts and some MMIO @@ -1627,7 +1635,7 @@ static int mpam_cpu_online(unsigned int cpu) mpam_reprogram_msc(msc); } =20 - if (mpam_is_enabled()) + if (mpam_resctrl_enabled) mpam_resctrl_online_cpu(cpu); =20 return 0; @@ -1673,7 +1681,7 @@ static int mpam_cpu_offline(unsigned int cpu) { struct mpam_msc *msc; =20 - if (mpam_is_enabled()) + if (mpam_resctrl_enabled) mpam_resctrl_offline_cpu(cpu); =20 guard(srcu)(&mpam_srcu); @@ -2535,6 +2543,7 @@ static void mpam_enable_once(void) } =20 static_branch_enable(&mpam_enabled); + mpam_resctrl_enabled =3D true; mpam_register_cpuhp_callbacks(mpam_cpu_online, mpam_cpu_offline, "mpam:online"); =20 @@ -2594,24 +2603,39 @@ void mpam_reset_class(struct mpam_class *class) void mpam_disable(struct work_struct *ignored) { int idx; + bool do_resctrl_exit; struct mpam_class *class; struct mpam_msc *msc, *tmp; =20 + if (mpam_is_enabled()) + static_branch_disable(&mpam_enabled); + mutex_lock(&mpam_cpuhp_state_lock); if (mpam_cpuhp_state) { cpuhp_remove_state(mpam_cpuhp_state); mpam_cpuhp_state =3D 0; } + + /* + * Removing the cpuhp state called mpam_cpu_offline() and told resctrl + * all the CPUs are offline. + */ + do_resctrl_exit =3D mpam_resctrl_enabled; + mpam_resctrl_enabled =3D false; mutex_unlock(&mpam_cpuhp_state_lock); =20 - static_branch_disable(&mpam_enabled); + if (do_resctrl_exit) + mpam_resctrl_exit(); =20 mpam_unregister_irqs(); =20 idx =3D srcu_read_lock(&mpam_srcu); list_for_each_entry_srcu(class, &mpam_classes, classes_list, - srcu_read_lock_held(&mpam_srcu)) + srcu_read_lock_held(&mpam_srcu)) { mpam_reset_class(class); + if (do_resctrl_exit) + mpam_resctrl_teardown_class(class); + } srcu_read_unlock(&mpam_srcu, idx); =20 mutex_lock(&mpam_list_lock); diff --git a/drivers/resctrl/mpam_internal.h b/drivers/resctrl/mpam_interna= l.h index 3a68ebd498fa..b13d5e55e701 100644 --- a/drivers/resctrl/mpam_internal.h +++ b/drivers/resctrl/mpam_internal.h @@ -450,12 +450,16 @@ int mpam_get_cpumask_from_cache_id(unsigned long cach= e_id, u32 cache_level, =20 #ifdef CONFIG_RESCTRL_FS int mpam_resctrl_setup(void); +void mpam_resctrl_exit(void); int mpam_resctrl_online_cpu(unsigned int cpu); void mpam_resctrl_offline_cpu(unsigned int cpu); +void mpam_resctrl_teardown_class(struct mpam_class *class); #else static inline int mpam_resctrl_setup(void) { return 0; } +static inline void mpam_resctrl_exit(void) { } static inline int mpam_resctrl_online_cpu(unsigned int cpu) { return 0; } static inline void mpam_resctrl_offline_cpu(unsigned int cpu) { } +static inline void mpam_resctrl_teardown_class(struct mpam_class *class) {= } #endif /* CONFIG_RESCTRL_FS */ =20 /* diff --git a/drivers/resctrl/mpam_resctrl.c b/drivers/resctrl/mpam_resctrl.c index eb3caee45470..506063bd3348 100644 --- a/drivers/resctrl/mpam_resctrl.c +++ b/drivers/resctrl/mpam_resctrl.c @@ -52,6 +52,12 @@ static bool exposed_mon_capable; */ static bool cdp_enabled; =20 +/* + * If resctrl_init() succeeded, resctrl_exit() can be used to remove suppo= rt + * for the filesystem in the event of an error. + */ +static bool resctrl_enabled; + /* * L3 local/total may come from different classes - what is the number of = MBWU * 'on L3'? @@ -310,6 +316,9 @@ static int resctrl_arch_mon_ctx_alloc_no_wait(enum resc= trl_event_id evtid) { struct mpam_resctrl_mon *mon =3D &mpam_resctrl_counters[evtid]; =20 + if (!mpam_is_enabled()) + return -EINVAL; + if (!mon->class) return -EINVAL; =20 @@ -352,6 +361,9 @@ static void resctrl_arch_mon_ctx_free_no_wait(enum resc= trl_event_id evtid, { struct mpam_resctrl_mon *mon =3D &mpam_resctrl_counters[evtid]; =20 + if (!mpam_is_enabled()) + return; + if (!mon->class) return; =20 @@ -449,6 +461,9 @@ int resctrl_arch_rmid_read(struct rdt_resource *r, stru= ct rdt_mon_domain *d, =20 resctrl_arch_rmid_read_context_check(); =20 + if (!mpam_is_enabled()) + return -EINVAL; + if (eventid >=3D QOS_NUM_EVENTS || !mon->class) return -EINVAL; =20 @@ -1343,6 +1358,9 @@ int resctrl_arch_update_one(struct rdt_resource *r, s= truct rdt_ctrl_domain *d, lockdep_assert_cpus_held(); lockdep_assert_irqs_enabled(); =20 + if (!mpam_is_enabled()) + return -EINVAL; + /* * No need to check the CPU as mpam_apply_config() doesn't care, and * resctrl_arch_update_domains() relies on this. @@ -1408,6 +1426,9 @@ int resctrl_arch_update_domains(struct rdt_resource *= r, u32 closid) lockdep_assert_cpus_held(); lockdep_assert_irqs_enabled(); =20 + if (!mpam_is_enabled()) + return -EINVAL; + list_for_each_entry(d, &r->ctrl_domains, hdr.list) { for (t =3D 0; t < CDP_NUM_TYPES; t++) { cfg =3D &d->staged_config[t]; @@ -1769,11 +1790,70 @@ int mpam_resctrl_setup(void) } =20 err =3D resctrl_init(); + if (!err) + WRITE_ONCE(resctrl_enabled, true); } =20 return err; } =20 +void mpam_resctrl_exit(void) +{ + if (!READ_ONCE(resctrl_enabled)) + return; + + WRITE_ONCE(resctrl_enabled, false); + resctrl_exit(); +} + +static void mpam_resctrl_teardown_mon(struct mpam_resctrl_mon *mon, struct= mpam_class *class) +{ + u32 num_mbwu_mon =3D l3_num_allocated_mbwu; + + if (!mon->mbwu_idx_to_mon) + return; + + if (mon->assigned_counters) { + __free_mbwu_mon(class, mon->assigned_counters, num_mbwu_mon); + mon->assigned_counters =3D NULL; + kfree(mon->mbwu_idx_to_mon); + } else { + __free_mbwu_mon(class, mon->mbwu_idx_to_mon, num_mbwu_mon); + } + mon->mbwu_idx_to_mon =3D NULL; +} + +/* + * The driver is detaching an MSC from this class, if resctrl was using it, + * pull on resctrl_exit(). + */ +void mpam_resctrl_teardown_class(struct mpam_class *class) +{ + int i; + struct mpam_resctrl_res *res; + struct mpam_resctrl_mon *mon; + + might_sleep(); + + for (i =3D 0; i < RDT_NUM_RESOURCES; i++) { + res =3D &mpam_resctrl_controls[i]; + if (res->class =3D=3D class) { + res->class =3D NULL; + break; + } + } + for (i =3D 0; i < QOS_NUM_EVENTS; i++) { + mon =3D &mpam_resctrl_counters[i]; + if (mon->class =3D=3D class) { + mon->class =3D NULL; + + mpam_resctrl_teardown_mon(mon, class); + + break; + } + } +} + #ifdef CONFIG_MPAM_KUNIT_TEST #include "test_mpam_resctrl.c" #endif --=20 2.39.5 From nobody Tue Dec 16 07:34:20 2025 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id E4CDC30216F for ; Fri, 5 Dec 2025 22:01:34 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764972096; cv=none; b=kDTAfCgUHS24iCHIpjskBfWMbIdv0dsx2Pae9L2Rm2ZcHMVcw3xBY0bhRaSqVbh11iMm74WeKNQR4StvJpUvh4bH2kks/8BRxrpy3uy4A71D5JKit49ieRFRu+Bixy/7PFMC+J83bF1FGS1MbL6nwMWTVidgLrQwBFPt3QB6AnU= ARC-Message-Signature: i=1; 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Fri, 5 Dec 2025 14:01:30 -0800 (PST) From: James Morse To: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: James Morse , D Scott Phillips OS , carl@os.amperecomputing.com, lcherian@marvell.com, bobo.shaobowang@huawei.com, tan.shaopeng@fujitsu.com, baolin.wang@linux.alibaba.com, Jamie Iles , Xin Hao , peternewman@google.com, dfustini@baylibre.com, amitsinght@marvell.com, David Hildenbrand , Dave Martin , Koba Ko , Shanker Donthineni , fenghuay@nvidia.com, baisheng.gao@unisoc.com, Jonathan Cameron , Gavin Shan , Ben Horgan , rohit.mathew@arm.com, reinette.chatre@intel.com, Punit Agrawal Subject: [RFC PATCH 31/38] arm_mpam: resctrl: Update the rmid reallocation limit Date: Fri, 5 Dec 2025 21:58:54 +0000 Message-Id: <20251205215901.17772-32-james.morse@arm.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20251205215901.17772-1-james.morse@arm.com> References: <20251205215901.17772-1-james.morse@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" resctrl's limbo code needs to be told when the data left in a cache is small enough for the partid+pmg value to be re-allocated. x86 uses the cache size divided by the number of rmid users the cache may have. Do the same, but for the smallest cache, and with the number of partid-and-pmg users. Querying the cache size can't happen until after cacheinfo_sysfs_init() has run, so mpam_resctrl_setup() must wait until then. Signed-off-by: James Morse --- drivers/resctrl/mpam_resctrl.c | 54 ++++++++++++++++++++++++++++++++++ 1 file changed, 54 insertions(+) diff --git a/drivers/resctrl/mpam_resctrl.c b/drivers/resctrl/mpam_resctrl.c index 506063bd3348..ccdf8db742c9 100644 --- a/drivers/resctrl/mpam_resctrl.c +++ b/drivers/resctrl/mpam_resctrl.c @@ -16,6 +16,7 @@ #include #include #include +#include =20 #include =20 @@ -58,6 +59,13 @@ static bool cdp_enabled; */ static bool resctrl_enabled; =20 +/* + * mpam_resctrl_pick_caches() needs to know the size of the caches. cachei= nfo + * populates this from a device_initcall(). mpam_resctrl_setup() must wait. + */ +static bool cacheinfo_ready; +static DECLARE_WAIT_QUEUE_HEAD(wait_cacheinfo_ready); + /* * L3 local/total may come from different classes - what is the number of = MBWU * 'on L3'? @@ -584,6 +592,38 @@ void resctrl_arch_reset_cntr(struct rdt_resource *r, s= truct rdt_mon_domain *d, reset_mon_cdp_safe(mon, mon_comp, USE_PRE_ALLOCATED, closid, rmid); } =20 +/* + * The rmid realloc threshold should be for the smallest cache exposed to + * resctrl. + */ +static int update_rmid_limits(struct mpam_class *class) +{ + u32 num_unique_pmg =3D resctrl_arch_system_num_rmid_idx(); + struct mpam_props *cprops =3D &class->props; + struct cacheinfo *ci; + + lockdep_assert_cpus_held(); + + /* Assume cache levels are the same size for all CPUs... */ + ci =3D get_cpu_cacheinfo_level(smp_processor_id(), class->level); + if (!ci || ci->size =3D=3D 0) { + pr_debug("Could not read cache size for class %u\n", + class->level); + return -EINVAL; + } + + if (!mpam_has_feature(mpam_feat_msmon_csu, cprops)) + return 0; + + if (!resctrl_rmid_realloc_limit || + ci->size < resctrl_rmid_realloc_limit) { + resctrl_rmid_realloc_limit =3D ci->size; + resctrl_rmid_realloc_threshold =3D ci->size / num_unique_pmg; + } + + return 0; +} + static bool cache_has_usable_cpor(struct mpam_class *class) { struct mpam_props *cprops =3D &class->props; @@ -1025,6 +1065,9 @@ static void mpam_resctrl_pick_counters(void) /* CSU counters only make sense on a cache. */ switch (class->type) { case MPAM_CLASS_CACHE: + if (update_rmid_limits(class)) + continue; + counter_update_class(QOS_L3_OCCUP_EVENT_ID, class); return; default: @@ -1731,6 +1774,8 @@ int mpam_resctrl_setup(void) struct mpam_resctrl_res *res; struct mpam_resctrl_mon *mon; =20 + wait_event(wait_cacheinfo_ready, cacheinfo_ready); + cpus_read_lock(); for (i =3D 0; i < RDT_NUM_RESOURCES; i++) { res =3D &mpam_resctrl_controls[i]; @@ -1854,6 +1899,15 @@ void mpam_resctrl_teardown_class(struct mpam_class *= class) } } =20 +static int __init __cacheinfo_ready(void) +{ + cacheinfo_ready =3D true; + wake_up(&wait_cacheinfo_ready); + + return 0; +} +device_initcall_sync(__cacheinfo_ready); + #ifdef CONFIG_MPAM_KUNIT_TEST #include "test_mpam_resctrl.c" #endif --=20 2.39.5 From nobody Tue Dec 16 07:34:20 2025 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 71E3E303CAF for ; Fri, 5 Dec 2025 22:01:39 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764972100; 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Fri, 5 Dec 2025 14:01:31 -0800 (PST) Received: from merodach.members.linode.com (usa-sjc-mx-foss1.foss.arm.com [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 9BCC13F740; Fri, 5 Dec 2025 14:01:34 -0800 (PST) From: James Morse To: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: James Morse , D Scott Phillips OS , carl@os.amperecomputing.com, lcherian@marvell.com, bobo.shaobowang@huawei.com, tan.shaopeng@fujitsu.com, baolin.wang@linux.alibaba.com, Jamie Iles , Xin Hao , peternewman@google.com, dfustini@baylibre.com, amitsinght@marvell.com, David Hildenbrand , Dave Martin , Koba Ko , Shanker Donthineni , fenghuay@nvidia.com, baisheng.gao@unisoc.com, Jonathan Cameron , Gavin Shan , Ben Horgan , rohit.mathew@arm.com, reinette.chatre@intel.com, Punit Agrawal Subject: [RFC PATCH 32/38] arm_mpam: resctrl: Sort the order of the domain lists Date: Fri, 5 Dec 2025 21:58:55 +0000 Message-Id: <20251205215901.17772-33-james.morse@arm.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20251205215901.17772-1-james.morse@arm.com> References: <20251205215901.17772-1-james.morse@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" resctrl documents that the domains appear in numeric order in the schemata file. This means a little more work is needed when bringing a domain online. Add the support for this, using resctrl_find_domain() to find the point to insert in the list. Signed-off-by: James Morse --- drivers/resctrl/mpam_resctrl.c | 21 +++++++++++++++++---- 1 file changed, 17 insertions(+), 4 deletions(-) diff --git a/drivers/resctrl/mpam_resctrl.c b/drivers/resctrl/mpam_resctrl.c index ccdf8db742c9..84ef3c1b4f53 100644 --- a/drivers/resctrl/mpam_resctrl.c +++ b/drivers/resctrl/mpam_resctrl.c @@ -1547,6 +1547,21 @@ static struct mpam_component *find_component(struct = mpam_class *victim, int cpu) return NULL; } =20 +static void mpam_resctrl_domain_insert(struct list_head *list, + struct rdt_domain_hdr *new) +{ + struct rdt_domain_hdr *err; + struct list_head *pos =3D NULL; + + lockdep_assert_held(&domain_list_lock); + + err =3D resctrl_find_domain(list, new->id, &pos); + if (WARN_ON_ONCE(err)) + return; + + list_add_tail_rcu(&new->list, pos); +} + static struct mpam_resctrl_dom * mpam_resctrl_alloc_domain(unsigned int cpu, struct mpam_resctrl_res *res) { @@ -1584,8 +1599,7 @@ mpam_resctrl_alloc_domain(unsigned int cpu, struct mp= am_resctrl_res *res) ctrl_d =3D &dom->resctrl_ctrl_dom; mpam_resctrl_domain_hdr_init(cpu, ctrl_comp, &ctrl_d->hdr); ctrl_d->hdr.type =3D RESCTRL_CTRL_DOMAIN; - /* TODO: this list should be sorted */ - list_add_tail_rcu(&ctrl_d->hdr.list, &r->ctrl_domains); + mpam_resctrl_domain_insert(&r->ctrl_domains, &ctrl_d->hdr); err =3D resctrl_online_ctrl_domain(r, ctrl_d); if (err) { dom =3D ERR_PTR(err); @@ -1623,8 +1637,7 @@ mpam_resctrl_alloc_domain(unsigned int cpu, struct mp= am_resctrl_res *res) mon_d =3D &dom->resctrl_mon_dom; mpam_resctrl_domain_hdr_init(cpu, any_mon_comp, &mon_d->hdr); mon_d->hdr.type =3D RESCTRL_MON_DOMAIN; - /* TODO: this list should be sorted */ - list_add_tail_rcu(&mon_d->hdr.list, &r->mon_domains); + mpam_resctrl_domain_insert(&r->mon_domains, &mon_d->hdr); err =3D resctrl_online_mon_domain(r, mon_d); if (err) { dom =3D ERR_PTR(err); --=20 2.39.5 From nobody Tue Dec 16 07:34:20 2025 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 60A36305070 for ; Fri, 5 Dec 2025 22:01:43 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764972105; cv=none; b=r6XvHLKCs7OI7j8E1DRpWILWHjZbOIujFTLbiFPtChgvZoQM+PjFNm51qI6mGfK7CZM0Td0Ulf0mlmLQZSokZSss3rboKGlG4axDpwRWE5mJ5DZbexg72GI7+zu60VfWys+uMm8IYoywQYd4lOhNbPNKF8n2RzlFVhSLMUIj4R8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764972105; c=relaxed/simple; bh=ElkCqRj0/DPz6KdegKAc1lVXKhtLnyDWjkjOj/1Hv6g=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=T550qm7s2AU0BX/QHT2fyWw6UxTDnKhWgIW3Ng0rpnasj+xxHT6whKzhs943D73JovPhGpmqMTFwXAkmR5U340TZLRGdsjOLobshyps8UTlsfXho7142obZQ6iLZzpBHeh5333kBFqY4d2t3a32BBNuvo/FSC+i+S7nFSislRDQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 2F2541BC0; Fri, 5 Dec 2025 14:01:35 -0800 (PST) Received: from merodach.members.linode.com (usa-sjc-mx-foss1.foss.arm.com [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id A45663F740; Fri, 5 Dec 2025 14:01:38 -0800 (PST) From: James Morse To: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: James Morse , D Scott Phillips OS , carl@os.amperecomputing.com, lcherian@marvell.com, bobo.shaobowang@huawei.com, tan.shaopeng@fujitsu.com, baolin.wang@linux.alibaba.com, Jamie Iles , Xin Hao , peternewman@google.com, dfustini@baylibre.com, amitsinght@marvell.com, David Hildenbrand , Dave Martin , Koba Ko , Shanker Donthineni , fenghuay@nvidia.com, baisheng.gao@unisoc.com, Jonathan Cameron , Gavin Shan , Ben Horgan , rohit.mathew@arm.com, reinette.chatre@intel.com, Punit Agrawal , Zeng Heng Subject: [RFC PATCH 33/38] arm_mpam: Generate a configuration for min controls Date: Fri, 5 Dec 2025 21:58:56 +0000 Message-Id: <20251205215901.17772-34-james.morse@arm.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20251205215901.17772-1-james.morse@arm.com> References: <20251205215901.17772-1-james.morse@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" MPAM supports a minimum and maximum control for memory bandwidth. The purpose of the minimum control is to give priority to tasks that are below their minimum value. Resctrl only provides one value for the bandwidth configuration, which is used for the maximum. The minimum control is always programmed to zero on hardware that supports it. Generate a minimum bandwidth value that is 5% lower than the value provided by resctrl. This means tasks that are not receiving their target bandwidth can be prioritised by the hardware. CC: Zeng Heng Signed-off-by: James Morse --- drivers/resctrl/mpam_devices.c | 68 +++++++++++++++++++++++++++-- drivers/resctrl/mpam_internal.h | 2 + drivers/resctrl/test_mpam_devices.c | 66 ++++++++++++++++++++++++++++ 3 files changed, 132 insertions(+), 4 deletions(-) diff --git a/drivers/resctrl/mpam_devices.c b/drivers/resctrl/mpam_devices.c index 1334093fc03e..741e14e1e6cf 100644 --- a/drivers/resctrl/mpam_devices.c +++ b/drivers/resctrl/mpam_devices.c @@ -721,6 +721,13 @@ static void mpam_ris_hw_probe(struct mpam_msc_ris *ris) mpam_set_feature(mpam_feat_mbw_part, props); =20 props->bwa_wd =3D FIELD_GET(MPAMF_MBW_IDR_BWA_WD, mbw_features); + + /* + * The BWA_WD field can represent 0-63, but the control fields it + * describes have a maximum of 16 bits. + */ + props->bwa_wd =3D min(props->bwa_wd, 16); + if (props->bwa_wd && FIELD_GET(MPAMF_MBW_IDR_HAS_MAX, mbw_features)) mpam_set_feature(mpam_feat_mbw_max, props); =20 @@ -1387,7 +1394,7 @@ static void mpam_reprogram_ris_partid(struct mpam_msc= _ris *ris, u16 partid, =20 if (mpam_has_feature(mpam_feat_mbw_min, rprops) && mpam_has_feature(mpam_feat_mbw_min, cfg)) - mpam_write_partsel_reg(msc, MBW_MIN, 0); + mpam_write_partsel_reg(msc, MBW_MIN, cfg->mbw_min); =20 if (mpam_has_feature(mpam_feat_mbw_max, rprops) && mpam_has_feature(mpam_feat_mbw_max, cfg)) { @@ -2693,24 +2700,77 @@ static bool mpam_update_config(struct mpam_config *= cfg, maybe_update_config(cfg, mpam_feat_cpor_part, newcfg, cpbm, has_changes); maybe_update_config(cfg, mpam_feat_mbw_part, newcfg, mbw_pbm, has_changes= ); maybe_update_config(cfg, mpam_feat_mbw_max, newcfg, mbw_max, has_changes); + maybe_update_config(cfg, mpam_feat_mbw_min, newcfg, mbw_min, has_changes); =20 return has_changes; } =20 +static void mpam_extend_config(struct mpam_class *class, struct mpam_confi= g *cfg) +{ + struct mpam_props *cprops =3D &class->props; + u16 min, min_hw_granule, delta; + u16 max_hw_value, res0_bits; + + /* + * MAX and MIN should be set together. If only one is provided, + * generate a configuration for the other. If only one control + * type is supported, the other value will be ignored. + * + * Resctrl can only configure the MAX. + */ + if (mpam_has_feature(mpam_feat_mbw_max, cfg) && + !mpam_has_feature(mpam_feat_mbw_min, cfg)) { + /* + * Calculate the values the 'min' control can hold. + * e.g. on a platform with bwa_wd =3D 8, min_hw_granule is 0x00ff + * because those bits are RES0. Configurations of this value + * are effectively zero. But configurations need to saturate + * at min_hw_granule on systems with mismatched bwa_wd, where + * the 'less than 0' values are implemented on some MSC, but + * not others. + */ + res0_bits =3D 16 - cprops->bwa_wd; + max_hw_value =3D ((1 << cprops->bwa_wd) - 1) << res0_bits; + min_hw_granule =3D ~max_hw_value; + + delta =3D ((5 * MPAMCFG_MBW_MAX_MAX) / 100) - 1; + if (cfg->mbw_max > delta) + min =3D cfg->mbw_max - delta; + else + min =3D 0; + + cfg->mbw_min =3D max(min, min_hw_granule); + mpam_set_feature(mpam_feat_mbw_min, cfg); + } +} + int mpam_apply_config(struct mpam_component *comp, u16 partid, - struct mpam_config *cfg) + struct mpam_config *user_cfg) { struct mpam_write_config_arg arg; struct mpam_msc_ris *ris; + struct mpam_config cfg; struct mpam_vmsc *vmsc; struct mpam_msc *msc; =20 lockdep_assert_cpus_held(); =20 + /* Don't pass in the current config! */ - WARN_ON_ONCE(&comp->cfg[partid] =3D=3D cfg); + WARN_ON_ONCE(&comp->cfg[partid] =3D=3D user_cfg); =20 - if (!mpam_update_config(&comp->cfg[partid], cfg)) + /* + * Copy the config to avoid writing back the 'extended' version to + * the caller. + * This avoids mpam_devices.c setting a mbm_min that mpam_resctrl.c + * is unaware of ... when it then changes mbm_max to be lower than + * mbm_min. + */ + cfg =3D *user_cfg; + + mpam_extend_config(comp->class, &cfg); + + if (!mpam_update_config(&comp->cfg[partid], &cfg)) return 0; =20 arg.comp =3D comp; diff --git a/drivers/resctrl/mpam_internal.h b/drivers/resctrl/mpam_interna= l.h index b13d5e55e701..d381906545ed 100644 --- a/drivers/resctrl/mpam_internal.h +++ b/drivers/resctrl/mpam_internal.h @@ -277,6 +277,7 @@ struct mpam_config { u32 cpbm; u32 mbw_pbm; u16 mbw_max; + u16 mbw_min; =20 bool reset_cpbm; bool reset_mbw_pbm; @@ -618,6 +619,7 @@ static inline void mpam_resctrl_teardown_class(struct m= pam_class *class) { } * MPAMCFG_MBW_MAX - MPAM memory maximum bandwidth partitioning configurat= ion * register */ +#define MPAMCFG_MBW_MAX_MAX_NR_BITS 16 #define MPAMCFG_MBW_MAX_MAX GENMASK(15, 0) #define MPAMCFG_MBW_MAX_HARDLIM BIT(31) =20 diff --git a/drivers/resctrl/test_mpam_devices.c b/drivers/resctrl/test_mpa= m_devices.c index 3e8d564a0c64..2f802fd9f249 100644 --- a/drivers/resctrl/test_mpam_devices.c +++ b/drivers/resctrl/test_mpam_devices.c @@ -322,6 +322,71 @@ static void test_mpam_enable_merge_features(struct kun= it *test) mutex_unlock(&mpam_list_lock); } =20 +static void test_mpam_extend_config(struct kunit *test) +{ + struct mpam_config fake_cfg =3D { }; + struct mpam_class fake_class =3D { }; + + /* Configurations with both are not modified */ + fake_class.props.bwa_wd =3D 16; + fake_cfg.mbw_max =3D 0xfeef; + fake_cfg.mbw_min =3D 0xfeef; + bitmap_zero(fake_cfg.features, MPAM_FEATURE_LAST); + mpam_set_feature(mpam_feat_mbw_max, &fake_cfg); + mpam_set_feature(mpam_feat_mbw_min, &fake_cfg); + mpam_extend_config(&fake_class, &fake_cfg); + KUNIT_EXPECT_TRUE(test, mpam_has_feature(mpam_feat_mbw_max, &fake_cfg)); + KUNIT_EXPECT_TRUE(test, mpam_has_feature(mpam_feat_mbw_min, &fake_cfg)); + KUNIT_EXPECT_EQ(test, fake_cfg.mbw_max, 0xfeef); + KUNIT_EXPECT_EQ(test, fake_cfg.mbw_min, 0xfeef); + + /* When a min is missing, it is generated */ + fake_class.props.bwa_wd =3D 16; + fake_cfg.mbw_max =3D 0xfeef; + fake_cfg.mbw_min =3D 0; + bitmap_zero(fake_cfg.features, MPAM_FEATURE_LAST); + mpam_set_feature(mpam_feat_mbw_max, &fake_cfg); + mpam_extend_config(&fake_class, &fake_cfg); + KUNIT_EXPECT_TRUE(test, mpam_has_feature(mpam_feat_mbw_max, &fake_cfg)); + KUNIT_EXPECT_TRUE(test, mpam_has_feature(mpam_feat_mbw_min, &fake_cfg)); + KUNIT_EXPECT_EQ(test, fake_cfg.mbw_max, 0xfeef); + KUNIT_EXPECT_EQ(test, fake_cfg.mbw_min, 0xf224); + + fake_class.props.bwa_wd =3D 8; + fake_cfg.mbw_max =3D 0xfeef; + fake_cfg.mbw_min =3D 0; + bitmap_zero(fake_cfg.features, MPAM_FEATURE_LAST); + mpam_set_feature(mpam_feat_mbw_max, &fake_cfg); + mpam_extend_config(&fake_class, &fake_cfg); + KUNIT_EXPECT_TRUE(test, mpam_has_feature(mpam_feat_mbw_max, &fake_cfg)); + KUNIT_EXPECT_TRUE(test, mpam_has_feature(mpam_feat_mbw_min, &fake_cfg)); + KUNIT_EXPECT_EQ(test, fake_cfg.mbw_max, 0xfeef); + KUNIT_EXPECT_EQ(test, fake_cfg.mbw_min, 0xf224); + + /* 5% below the minimum granule, is still the minimum granule */ + fake_class.props.bwa_wd =3D 12; + fake_cfg.mbw_max =3D 0xf; + fake_cfg.mbw_min =3D 0; + bitmap_zero(fake_cfg.features, MPAM_FEATURE_LAST); + mpam_set_feature(mpam_feat_mbw_max, &fake_cfg); + mpam_extend_config(&fake_class, &fake_cfg); + KUNIT_EXPECT_TRUE(test, mpam_has_feature(mpam_feat_mbw_max, &fake_cfg)); + KUNIT_EXPECT_TRUE(test, mpam_has_feature(mpam_feat_mbw_min, &fake_cfg)); + KUNIT_EXPECT_EQ(test, fake_cfg.mbw_max, 0xf); + KUNIT_EXPECT_EQ(test, fake_cfg.mbw_min, 0xf); + + fake_class.props.bwa_wd =3D 16; + fake_cfg.mbw_max =3D 0x4; + fake_cfg.mbw_min =3D 0; + bitmap_zero(fake_cfg.features, MPAM_FEATURE_LAST); + mpam_set_feature(mpam_feat_mbw_max, &fake_cfg); + mpam_extend_config(&fake_class, &fake_cfg); + KUNIT_EXPECT_TRUE(test, mpam_has_feature(mpam_feat_mbw_max, &fake_cfg)); + KUNIT_EXPECT_TRUE(test, mpam_has_feature(mpam_feat_mbw_min, &fake_cfg)); + KUNIT_EXPECT_EQ(test, fake_cfg.mbw_max, 0x4); + KUNIT_EXPECT_EQ(test, fake_cfg.mbw_min, 0x0); +} + static void test_mpam_reset_msc_bitmap(struct kunit *test) { char __iomem *buf =3D kunit_kzalloc(test, SZ_16K, GFP_KERNEL); @@ -378,6 +443,7 @@ static struct kunit_case mpam_devices_test_cases[] =3D { KUNIT_CASE(test_mpam_reset_msc_bitmap), KUNIT_CASE(test_mpam_enable_merge_features), KUNIT_CASE(test__props_mismatch), + KUNIT_CASE(test_mpam_extend_config), {} }; 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smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 482581BCB; Fri, 5 Dec 2025 14:01:39 -0800 (PST) Received: from merodach.members.linode.com (usa-sjc-mx-foss1.foss.arm.com [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id CA59E3F740; Fri, 5 Dec 2025 14:01:42 -0800 (PST) From: James Morse To: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: James Morse , D Scott Phillips OS , carl@os.amperecomputing.com, lcherian@marvell.com, bobo.shaobowang@huawei.com, tan.shaopeng@fujitsu.com, baolin.wang@linux.alibaba.com, Jamie Iles , Xin Hao , peternewman@google.com, dfustini@baylibre.com, amitsinght@marvell.com, David Hildenbrand , Dave Martin , Koba Ko , Shanker Donthineni , fenghuay@nvidia.com, baisheng.gao@unisoc.com, Jonathan Cameron , Gavin Shan , Ben Horgan , rohit.mathew@arm.com, reinette.chatre@intel.com, Punit Agrawal Subject: [RFC PATCH 34/38] arm_mpam: Add quirk framework Date: Fri, 5 Dec 2025 21:58:57 +0000 Message-Id: <20251205215901.17772-35-james.morse@arm.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20251205215901.17772-1-james.morse@arm.com> References: <20251205215901.17772-1-james.morse@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Shanker Donthineni The MPAM specification includes the MPAMF_IIDR, which serves to uniquely identify the MSC implementation through a combination of implementer details, product ID, variant, and revision. Certain hardware issues/errata can be resolved using software workarounds. Introduce a quirk framework to allow workarounds to be enabled based on the MPAMF_IIDR value. Signed-off-by: Shanker Donthineni [ morse: Stash the IIDR so this doesn't need an IPI, enable quirks only once, move the description to the callback so it can be pr_once()d, add an enum of workarounds for popular errata. Add macros for making lists of product/revision/vendor half readable ] Signed-off-by: James Morse --- drivers/resctrl/mpam_devices.c | 27 +++++++++++++++++++++++++++ drivers/resctrl/mpam_internal.h | 26 ++++++++++++++++++++++++++ 2 files changed, 53 insertions(+) diff --git a/drivers/resctrl/mpam_devices.c b/drivers/resctrl/mpam_devices.c index 741e14e1e6cf..f0f6f9b55ad4 100644 --- a/drivers/resctrl/mpam_devices.c +++ b/drivers/resctrl/mpam_devices.c @@ -630,6 +630,25 @@ static struct mpam_msc_ris *mpam_get_or_create_ris(str= uct mpam_msc *msc, return ERR_PTR(-ENOENT); } =20 +static const struct mpam_quirk mpam_quirks[] =3D { + { NULL }, /* Sentinel */ +}; + +static void mpam_enable_quirks(struct mpam_msc *msc) +{ + const struct mpam_quirk *quirk; + + for (quirk =3D &mpam_quirks[0]; quirk->iidr_mask; quirk++) { + if (quirk->iidr !=3D (msc->iidr & quirk->iidr_mask)) + continue; + + if (quirk->init) + quirk->init(msc, quirk); + else + mpam_set_quirk(quirk->workaround, msc); + } +} + /* * IHI009A.a has this nugget: "If a monitor does not support automatic beh= aviour * of NRDY, software can use this bit for any purpose" - so hardware might= not @@ -864,8 +883,11 @@ static int mpam_msc_hw_probe(struct mpam_msc *msc) /* Grab an IDR value to find out how many RIS there are */ mutex_lock(&msc->part_sel_lock); idr =3D mpam_msc_read_idr(msc); + msc->iidr =3D mpam_read_partsel_reg(msc, IIDR); mutex_unlock(&msc->part_sel_lock); =20 + mpam_enable_quirks(msc); + msc->ris_max =3D FIELD_GET(MPAMF_IDR_RIS_MAX, idr); =20 /* Use these values so partid/pmg always starts with a valid value */ @@ -1987,6 +2009,7 @@ static bool mpam_has_cmax_wd_feature(struct mpam_prop= s *props) * resulting safe value must be compatible with both. When merging values = in * the tree, all the aliasing resources must be handled first. * On mismatch, parent is modified. + * Quirks on an MSC will apply to all MSC in that class. */ static void __props_mismatch(struct mpam_props *parent, struct mpam_props *child, bool alias) @@ -2106,6 +2129,7 @@ static void __props_mismatch(struct mpam_props *paren= t, * nobble the class feature, as we can't configure all the resources. * e.g. The L3 cache is composed of two resources with 13 and 17 portion * bitmaps respectively. + * Quirks on an MSC will apply to all MSC in that class. */ static void __class_props_mismatch(struct mpam_class *class, struct mpam_vmsc *vmsc) @@ -2119,6 +2143,9 @@ __class_props_mismatch(struct mpam_class *class, stru= ct mpam_vmsc *vmsc) dev_dbg(dev, "Merging features for class:0x%lx &=3D vmsc:0x%lx\n", (long)cprops->features, (long)vprops->features); =20 + /* Merge quirks */ + class->quirks |=3D vmsc->msc->quirks; + /* Take the safe value for any common features */ __props_mismatch(cprops, vprops, false); } diff --git a/drivers/resctrl/mpam_internal.h b/drivers/resctrl/mpam_interna= l.h index d381906545ed..de3e5faa12b2 100644 --- a/drivers/resctrl/mpam_internal.h +++ b/drivers/resctrl/mpam_internal.h @@ -88,6 +88,8 @@ struct mpam_msc { u8 pmg_max; unsigned long ris_idxs; u32 ris_max; + u32 iidr; + u16 quirks; =20 /* * error_irq_lock is taken when registering/unregistering the error @@ -215,6 +217,29 @@ struct mpam_props { #define mpam_set_feature(_feat, x) set_bit(_feat, (x)->features) #define mpam_clear_feature(_feat, x) clear_bit(_feat, (x)->features) =20 +/* Workaround bits for msc->quirks */ +enum mpam_device_quirks { + MPAM_QUIRK_LAST, +}; + +#define mpam_has_quirk(_quirk, x) ((1 << (_quirk) & (x)->quirks)) +#define mpam_set_quirk(_quirk, x) ((x)->quirks |=3D (1 << (_quirk))) + +struct mpam_quirk { + void (*init)(struct mpam_msc *msc, const struct mpam_quirk *quirk); + + u32 iidr; + u32 iidr_mask; + + enum mpam_device_quirks workaround; +}; + +#define MPAM_IIDR_MATCH_ONE FIELD_PREP_CONST(MPAMF_IIDR_PRODUCTID, 0xfff= ) | \ + FIELD_PREP_CONST(MPAMF_IIDR_VARIANT, 0xf ) | \ + FIELD_PREP_CONST(MPAMF_IIDR_REVISION, 0xf ) | \ + FIELD_PREP_CONST(MPAMF_IIDR_IMPLEMENTER, 0xfff) + + /* The values for MSMON_CFG_MBWU_FLT.RWBW */ enum mon_filter_options { COUNT_BOTH =3D 0, @@ -258,6 +283,7 @@ struct mpam_class { =20 struct mpam_props props; u32 nrdy_usec; + u16 quirks; u8 level; enum mpam_class_types type; =20 --=20 2.39.5 From nobody Tue Dec 16 07:34:20 2025 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id BCC6230ACEE for ; Fri, 5 Dec 2025 22:01:51 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764972113; cv=none; b=a78/AE7tdO/dMmsbjEJHcHOnHw5GI3Wz4CYImmLYe8IqGuu2Sepl/dm+8cdVrxBKb7/2aEY6riirel6oVWfHdn7+oaywWlVS3IErJhmoeDYwsIvwp0xOpo7SRv77PjkV0vEbJxLbWn9g/fVvAZBEY65C5E0nqh2FYthKbmQ0hrg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764972113; c=relaxed/simple; bh=o++RdOwQER57jlLAFS+OwIG9ElYP39Btf8jPfDLWFDg=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=fyOmlddhXjDs5kiqyx2rfpAa9rfq87i9R6/vL1o2aGi7DPm58AHel8761Ar6+hzBNS9gQdeHebTIGD6LSGP4vf0Stp+iKaaYG+wBgusfZ4dtGrGsMTngCXzIoPE7g+0Nzw65ofkfu7C6KPETDYgjbl64YTO/VyyiQ6dFCiPT+pQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 5EF911BF3; Fri, 5 Dec 2025 14:01:43 -0800 (PST) Received: from merodach.members.linode.com (usa-sjc-mx-foss1.foss.arm.com [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id D0B3A3F740; Fri, 5 Dec 2025 14:01:46 -0800 (PST) From: James Morse To: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: James Morse , D Scott Phillips OS , carl@os.amperecomputing.com, lcherian@marvell.com, bobo.shaobowang@huawei.com, tan.shaopeng@fujitsu.com, baolin.wang@linux.alibaba.com, Jamie Iles , Xin Hao , peternewman@google.com, dfustini@baylibre.com, amitsinght@marvell.com, David Hildenbrand , Dave Martin , Koba Ko , Shanker Donthineni , fenghuay@nvidia.com, baisheng.gao@unisoc.com, Jonathan Cameron , Gavin Shan , Ben Horgan , rohit.mathew@arm.com, reinette.chatre@intel.com, Punit Agrawal Subject: [RFC PATCH 35/38] arm_mpam: Add workaround for T241-MPAM-1 Date: Fri, 5 Dec 2025 21:58:58 +0000 Message-Id: <20251205215901.17772-36-james.morse@arm.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20251205215901.17772-1-james.morse@arm.com> References: <20251205215901.17772-1-james.morse@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Shanker Donthineni The MPAM bandwidth partitioning controls will not be correctly configured, and hardware will retain default configuration register values, meaning generally that bandwidth will remain unprovisioned. To address the issue, follow the below steps after updating the MBW_MIN and/or MBW_MAX registers. - Perform 64b reads from all 12 bridge MPAM shadow registers at offsets (0x360048 + slice*0x10000 + partid*8). These registers are read-only. - Continue iterating until all 12 shadow register values match in a loop. pr_warn_once if the values fail to match within the loop count 1000. - Perform 64b writes with the value 0x0 to the two spare registers at offsets 0x1b0000 and 0x1c0000. In the hardware, writes to the MPAMCFG_MBW_MAX MPAMCFG_MBW_MIN registers are transformed into broadcast writes to the 12 shadow registers. The final two writes to the spare registers cause a final rank of downstream micro-architectural MPAM registers to be updated from the shadow copies. The intervening loop to read the 12 shadow registers helps avoid a race condition where writes to the spare registers occur before all shadow registers have been updated. Signed-off-by: Shanker Donthineni [ morse: Merged the min/max update into a single mpam_quirk_post_config_change() helper. Stashed the t241_id in the msc instead of carrying the physical address around. Test the msc quirk bit instead of a static key. ] Signed-off-by: James Morse --- Documentation/arch/arm64/silicon-errata.rst | 2 + drivers/resctrl/mpam_devices.c | 87 +++++++++++++++++++++ drivers/resctrl/mpam_internal.h | 9 +++ 3 files changed, 98 insertions(+) diff --git a/Documentation/arch/arm64/silicon-errata.rst b/Documentation/ar= ch/arm64/silicon-errata.rst index a7ec57060f64..4e86b85fe3d6 100644 --- a/Documentation/arch/arm64/silicon-errata.rst +++ b/Documentation/arch/arm64/silicon-errata.rst @@ -246,6 +246,8 @@ stable kernels. +----------------+-----------------+-----------------+--------------------= ---------+ | NVIDIA | T241 GICv3/4.x | T241-FABRIC-4 | N/A = | +----------------+-----------------+-----------------+--------------------= ---------+ +| NVIDIA | T241 MPAM | T241-MPAM-1 | N/A = | ++----------------+-----------------+-----------------+--------------------= ---------+ +----------------+-----------------+-----------------+--------------------= ---------+ | Freescale/NXP | LS2080A/LS1043A | A-008585 | FSL_ERRATUM_A008585= | +----------------+-----------------+-----------------+--------------------= ---------+ diff --git a/drivers/resctrl/mpam_devices.c b/drivers/resctrl/mpam_devices.c index f0f6f9b55ad4..f1f03ceade0a 100644 --- a/drivers/resctrl/mpam_devices.c +++ b/drivers/resctrl/mpam_devices.c @@ -29,6 +29,16 @@ =20 #include "mpam_internal.h" =20 +/* Values for the T241 errata workaround */ +#define T241_CHIPS_MAX 4 +#define T241_CHIP_NSLICES 12 +#define T241_SPARE_REG0_OFF 0x1b0000 +#define T241_SPARE_REG1_OFF 0x1c0000 +#define T241_CHIP_ID(phys) FIELD_GET(GENMASK_ULL(44, 43), phys) +#define T241_SHADOW_REG_OFF(sidx, pid) (0x360048 + (sidx) * 0x10000 + (pid= ) * 8) +#define SMCCC_SOC_ID_T241 0x036b0241 +static void __iomem *t241_scratch_regs[T241_CHIPS_MAX]; + /* * mpam_list_lock protects the SRCU lists when writing. Once the * mpam_enabled key is enabled these lists are read-only, @@ -630,7 +640,44 @@ static struct mpam_msc_ris *mpam_get_or_create_ris(str= uct mpam_msc *msc, return ERR_PTR(-ENOENT); } =20 +static void mpam_enable_quirk_nvidia_t241(struct mpam_msc *msc, + const struct mpam_quirk *quirk) +{ + s32 soc_id =3D arm_smccc_get_soc_id_version(); + struct resource *r; + phys_addr_t phys; + + /* + * A mapping to a device other than the MSC is needed, check + * SOC_ID is NVIDIA T241 chip (036b:0241) + */ + if (soc_id < 0 || soc_id !=3D SMCCC_SOC_ID_T241) + return; + + r =3D platform_get_resource(msc->pdev, IORESOURCE_MEM, 0); + if (!r) + return; + + /* Find the internal registers base addr from the CHIP ID */ + msc->t241_id =3D T241_CHIP_ID(r->start); + phys =3D FIELD_PREP(GENMASK_ULL(45, 44), msc->t241_id) | 0x19000000ULL; + + t241_scratch_regs[msc->t241_id] =3D ioremap(phys, SZ_8M); + if (WARN_ON_ONCE(!t241_scratch_regs[msc->t241_id])) + return; + + mpam_set_quirk(quirk->workaround, msc); + pr_info_once("Enabled workaround for NVIDIA T241 erratum T241-MPAM-1\n"); +} + static const struct mpam_quirk mpam_quirks[] =3D { + { + /* NVIDIA t241 erratum T241-MPAM-1 */ + .init =3D mpam_enable_quirk_nvidia_t241, + .iidr =3D MPAM_IIDR_NVIDIA_T421, + .iidr_mask =3D MPAM_IIDR_MATCH_ONE, + .workaround =3D T241_SCRUB_SHADOW_REGS, + }, { NULL }, /* Sentinel */ }; =20 @@ -1372,6 +1419,44 @@ static void mpam_reset_msc_bitmap(struct mpam_msc *m= sc, u16 reg, u16 wd) __mpam_write_reg(msc, reg, bm); } =20 +static void mpam_apply_t241_erratum(struct mpam_msc_ris *ris, u16 partid) +{ + int sidx, i, lcount =3D 1000; + void __iomem *regs; + u64 val0, val; + + regs =3D t241_scratch_regs[ris->vmsc->msc->t241_id]; + + for (i =3D 0; i < lcount; i++) { + /* Read the shadow register at index 0 */ + val0 =3D readq_relaxed(regs + T241_SHADOW_REG_OFF(0, partid)); + + /* Check if all the shadow registers have the same value */ + for (sidx =3D 1; sidx < T241_CHIP_NSLICES; sidx++) { + val =3D readq_relaxed(regs + + T241_SHADOW_REG_OFF(sidx, partid)); + if (val !=3D val0) + break; + } + if (sidx =3D=3D T241_CHIP_NSLICES) + break; + } + + if (i =3D=3D lcount) + pr_warn_once("t241: inconsistent values in shadow regs"); + + /* Write a value zero to spare registers to take effect of MBW conf */ + writeq_relaxed(0, regs + T241_SPARE_REG0_OFF); + writeq_relaxed(0, regs + T241_SPARE_REG1_OFF); +} + +static void mpam_quirk_post_config_change(struct mpam_msc_ris *ris, u16 pa= rtid, + struct mpam_config *cfg) +{ + if (mpam_has_quirk(T241_SCRUB_SHADOW_REGS, ris->vmsc->msc)) + mpam_apply_t241_erratum(ris, partid); +} + /* Called via IPI. Call while holding an SRCU reference */ static void mpam_reprogram_ris_partid(struct mpam_msc_ris *ris, u16 partid, struct mpam_config *cfg) @@ -1455,6 +1540,8 @@ static void mpam_reprogram_ris_partid(struct mpam_msc= _ris *ris, u16 partid, mpam_write_partsel_reg(msc, PRI, pri_val); } =20 + mpam_quirk_post_config_change(ris, partid, cfg); + mutex_unlock(&msc->part_sel_lock); } =20 diff --git a/drivers/resctrl/mpam_internal.h b/drivers/resctrl/mpam_interna= l.h index de3e5faa12b2..70b78cfd1f5b 100644 --- a/drivers/resctrl/mpam_internal.h +++ b/drivers/resctrl/mpam_internal.h @@ -133,6 +133,9 @@ struct mpam_msc { void __iomem *mapped_hwpage; size_t mapped_hwpage_sz; =20 + /* Values only used on some platforms for quirks */ + u32 t241_id; + struct mpam_garbage garbage; }; =20 @@ -219,6 +222,7 @@ struct mpam_props { =20 /* Workaround bits for msc->quirks */ enum mpam_device_quirks { + T241_SCRUB_SHADOW_REGS, MPAM_QUIRK_LAST, }; =20 @@ -239,6 +243,11 @@ struct mpam_quirk { FIELD_PREP_CONST(MPAMF_IIDR_REVISION, 0xf ) | \ FIELD_PREP_CONST(MPAMF_IIDR_IMPLEMENTER, 0xfff) =20 +#define MPAM_IIDR_NVIDIA_T421 FIELD_PREP_CONST(MPAMF_IIDR_PRODUCTID, 0= x241) | \ + FIELD_PREP_CONST(MPAMF_IIDR_VARIANT, 0 ) | \ + FIELD_PREP_CONST(MPAMF_IIDR_REVISION, 0 ) | \ + FIELD_PREP_CONST(MPAMF_IIDR_IMPLEMENTER, 0x36b) + =20 /* The values for MSMON_CFG_MBWU_FLT.RWBW */ enum mon_filter_options { --=20 2.39.5 From nobody Tue Dec 16 07:34:20 2025 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 36D0D30C600 for ; Fri, 5 Dec 2025 22:01:55 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764972116; cv=none; b=OONsh7/pVpfs/DtURiukKNuBsfoh4q96oXR8X5QDZdG79njvgtcjOqmHlRluIVj35MiZpWE4YndZPCkqur+a2y36RaJNJdc6jtQg0tIPd6H6YB+5XeUFu1c9HlYmBtaon6ASTtIhv9HWLunjRp1eITq0M4PllhYqe21qBtcwBYQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764972116; c=relaxed/simple; bh=JDi7JVCrq9PMyvQ/D650zdseEpNkQwbZtvfeqNix8XU=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=vDv2gydm2ipRLvlxKO9D34LFZ7c9wnF5G/PYapJXqGeCUVTKGuF6kMGpcUBCpVh1ot3e/Kmbb9v4m0OLu9rcfN/LlA3MLe6XbnKWdWxnFGwaGcX6JoXpRmbPol+Rs0UhR4Y77isSpuhMeOKJDFj7tT3Uef2Qo9rJ5ZaDu6DdJCI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 657E41C00; Fri, 5 Dec 2025 14:01:47 -0800 (PST) Received: from merodach.members.linode.com (usa-sjc-mx-foss1.foss.arm.com [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id E5F883F740; Fri, 5 Dec 2025 14:01:50 -0800 (PST) From: James Morse To: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: James Morse , D Scott Phillips OS , carl@os.amperecomputing.com, lcherian@marvell.com, bobo.shaobowang@huawei.com, tan.shaopeng@fujitsu.com, baolin.wang@linux.alibaba.com, Jamie Iles , Xin Hao , peternewman@google.com, dfustini@baylibre.com, amitsinght@marvell.com, David Hildenbrand , Dave Martin , Koba Ko , Shanker Donthineni , fenghuay@nvidia.com, baisheng.gao@unisoc.com, Jonathan Cameron , Gavin Shan , Ben Horgan , rohit.mathew@arm.com, reinette.chatre@intel.com, Punit Agrawal Subject: [RFC PATCH 36/38] arm_mpam: Add workaround for T241-MPAM-4 Date: Fri, 5 Dec 2025 21:58:59 +0000 Message-Id: <20251205215901.17772-37-james.morse@arm.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20251205215901.17772-1-james.morse@arm.com> References: <20251205215901.17772-1-james.morse@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Shanker Donthineni In the T241 implementation of memory-bandwidth partitioning, in the absence of contention for bandwidth, the minimum bandwidth setting can affect the amount of achieved bandwidth. Specifically, the achieved bandwidth in the absence of contention can settle to any value between the values of MPAMCFG_MBW_MIN and MPAMCFG_MBW_MAX. Also, if MPAMCFG_MBW_MIN is set zero (below 0.78125%), once a core enters a throttled state, it will never leave that state. The first issue is not a cocern if the MPAM software allows to program MPAMCFG_MBW_MIN through the sysfs interface. This patch ensures program MBW_MIN=3D1 (0.78125%) whenever MPAMCFG_MBW_MIN=3D0 is programmed. In the scenario where the resctrl doesn't support the MBW_MIN interface via sysfs, to achieve bandwidth closer to MW_MAX in the absence of contention, software should configure a relatively narrow gap between MBW_MIN and MBW_MAX. The recommendation is to use a 5% gap to mitigate the problem. Signed-off-by: Shanker Donthineni [ morse: Added as second quirk, adapted to use the new intermediate values in mpam_extend_config() ] Signed-off-by: James Morse --- Documentation/arch/arm64/silicon-errata.rst | 2 + drivers/resctrl/mpam_devices.c | 60 ++++++++++++++++----- drivers/resctrl/mpam_internal.h | 1 + 3 files changed, 49 insertions(+), 14 deletions(-) diff --git a/Documentation/arch/arm64/silicon-errata.rst b/Documentation/ar= ch/arm64/silicon-errata.rst index 4e86b85fe3d6..b18bc704d4a1 100644 --- a/Documentation/arch/arm64/silicon-errata.rst +++ b/Documentation/arch/arm64/silicon-errata.rst @@ -248,6 +248,8 @@ stable kernels. +----------------+-----------------+-----------------+--------------------= ---------+ | NVIDIA | T241 MPAM | T241-MPAM-1 | N/A = | +----------------+-----------------+-----------------+--------------------= ---------+ +| NVIDIA | T241 MPAM | T241-MPAM-4 | N/A = | ++----------------+-----------------+-----------------+--------------------= ---------+ +----------------+-----------------+-----------------+--------------------= ---------+ | Freescale/NXP | LS2080A/LS1043A | A-008585 | FSL_ERRATUM_A008585= | +----------------+-----------------+-----------------+--------------------= ---------+ diff --git a/drivers/resctrl/mpam_devices.c b/drivers/resctrl/mpam_devices.c index f1f03ceade0a..5ba0aa703807 100644 --- a/drivers/resctrl/mpam_devices.c +++ b/drivers/resctrl/mpam_devices.c @@ -678,6 +678,12 @@ static const struct mpam_quirk mpam_quirks[] =3D { .iidr_mask =3D MPAM_IIDR_MATCH_ONE, .workaround =3D T241_SCRUB_SHADOW_REGS, }, + { + /* NVIDIA t241 erratum T241-MPAM-4 */ + .iidr =3D MPAM_IIDR_NVIDIA_T421, + .iidr_mask =3D MPAM_IIDR_MATCH_ONE, + .workaround =3D T241_FORCE_MBW_MIN_TO_ONE, + }, { NULL }, /* Sentinel */ }; =20 @@ -1622,6 +1628,22 @@ static void mpam_init_reset_cfg(struct mpam_config *= reset_cfg) bitmap_fill(reset_cfg->features, MPAM_FEATURE_LAST); } =20 +/* + * This is not part of mpam_init_reset_cfg() as high level callers have the + * class, and low level callers a ris. + */ +static void mpam_wa_t241_force_mbw_min_to_one(struct mpam_config *cfg, + struct mpam_props *props) +{ + u16 max_hw_value, min_hw_granule, res0_bits; + + res0_bits =3D 16 - props->bwa_wd; + max_hw_value =3D ((1 << props->bwa_wd) - 1) << res0_bits; + min_hw_granule =3D ~max_hw_value; + + cfg->mbw_min =3D min_hw_granule + 1; +} + /* * Called via smp_call_on_cpu() to prevent migration, while still being * pre-emptible. Caller must hold mpam_srcu. @@ -2524,7 +2546,8 @@ static void __destroy_component_cfg(struct mpam_compo= nent *comp) static void mpam_reset_component_cfg(struct mpam_component *comp) { int i; - struct mpam_props *cprops =3D &comp->class->props; + struct mpam_class *class =3D comp->class; + struct mpam_props *cprops =3D &class->props; =20 mpam_assert_partid_sizes_fixed(); =20 @@ -2539,6 +2562,10 @@ static void mpam_reset_component_cfg(struct mpam_com= ponent *comp) comp->cfg[i].mbw_pbm =3D GENMASK(cprops->mbw_pbm_bits - 1, 0); if (cprops->bwa_wd) comp->cfg[i].mbw_max =3D GENMASK(15, 16 - cprops->bwa_wd); + + if (mpam_has_quirk(T241_FORCE_MBW_MIN_TO_ONE, class)) + mpam_wa_t241_force_mbw_min_to_one(&comp->cfg[i], + &class->props); } } =20 @@ -2825,6 +2852,18 @@ static void mpam_extend_config(struct mpam_class *cl= ass, struct mpam_config *cfg u16 min, min_hw_granule, delta; u16 max_hw_value, res0_bits; =20 + /* + * Calculate the values the 'min' control can hold. + * e.g. on a platform with bwa_wd =3D 8, min_hw_granule is 0x00ff because + * those bits are RES0. Configurations of this value are effectively + * zero. But configurations need to saturate at min_hw_granule on + * systems with mismatched bwa_wd, where the 'less than 0' values are + * implemented on some MSC, but not others. + */ + res0_bits =3D 16 - cprops->bwa_wd; + max_hw_value =3D ((1 << cprops->bwa_wd) - 1) << res0_bits; + min_hw_granule =3D ~max_hw_value; + /* * MAX and MIN should be set together. If only one is provided, * generate a configuration for the other. If only one control @@ -2834,19 +2873,6 @@ static void mpam_extend_config(struct mpam_class *cl= ass, struct mpam_config *cfg */ if (mpam_has_feature(mpam_feat_mbw_max, cfg) && !mpam_has_feature(mpam_feat_mbw_min, cfg)) { - /* - * Calculate the values the 'min' control can hold. - * e.g. on a platform with bwa_wd =3D 8, min_hw_granule is 0x00ff - * because those bits are RES0. Configurations of this value - * are effectively zero. But configurations need to saturate - * at min_hw_granule on systems with mismatched bwa_wd, where - * the 'less than 0' values are implemented on some MSC, but - * not others. - */ - res0_bits =3D 16 - cprops->bwa_wd; - max_hw_value =3D ((1 << cprops->bwa_wd) - 1) << res0_bits; - min_hw_granule =3D ~max_hw_value; - delta =3D ((5 * MPAMCFG_MBW_MAX_MAX) / 100) - 1; if (cfg->mbw_max > delta) min =3D cfg->mbw_max - delta; @@ -2856,6 +2882,12 @@ static void mpam_extend_config(struct mpam_class *cl= ass, struct mpam_config *cfg cfg->mbw_min =3D max(min, min_hw_granule); mpam_set_feature(mpam_feat_mbw_min, cfg); } + + if (mpam_has_quirk(T241_FORCE_MBW_MIN_TO_ONE, class) && + cfg->mbw_min <=3D min_hw_granule) { + cfg->mbw_min =3D min_hw_granule + 1; + mpam_set_feature(mpam_feat_mbw_min, cfg); + } } =20 int mpam_apply_config(struct mpam_component *comp, u16 partid, diff --git a/drivers/resctrl/mpam_internal.h b/drivers/resctrl/mpam_interna= l.h index 70b78cfd1f5b..01882f0acee2 100644 --- a/drivers/resctrl/mpam_internal.h +++ b/drivers/resctrl/mpam_internal.h @@ -223,6 +223,7 @@ struct mpam_props { /* Workaround bits for msc->quirks */ enum mpam_device_quirks { T241_SCRUB_SHADOW_REGS, + T241_FORCE_MBW_MIN_TO_ONE, MPAM_QUIRK_LAST, }; =20 --=20 2.39.5 From nobody Tue Dec 16 07:34:20 2025 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 938AF30F539 for ; Fri, 5 Dec 2025 22:01:59 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764972121; cv=none; b=S/Yp7o4ry2q5EIvy6Bf3y8EqQha9fFKpNsMyW5mRcHvKGn2/ywRwKVq76q8UnR7UD2145vsT3gnnpLHD1ucRf6Pm61qtcm8QUA0LDXrnxGJPEZFkIjVCpcMC5XQsvQDVGgMm6nQ2AzDJn3DSoqUl865ZA6noskKt0UBXFQCB3S4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764972121; c=relaxed/simple; bh=GSRe8/33WlW8qJEjSVpETt7F++nFtfHIe9I7Vw8QgOg=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=Vr+Ev6b4CK7ICm/hy1RTgbhyXCjGL3KIsuHAEAbgpVE7dknSfxq82GcV6L1GIxcxORszK3giTU+Lf/gCveDL9uyBaOXDyQoyJzH7xFLjBoSFuLwwHkFyLFkxDl+KV3F7hr5Ax44sPfgPHLqXPrXUqZroHwNz9YSmd2mWfzqXykY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 6B26D1C0A; Fri, 5 Dec 2025 14:01:51 -0800 (PST) Received: from merodach.members.linode.com (usa-sjc-mx-foss1.foss.arm.com [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id F040B3F740; Fri, 5 Dec 2025 14:01:54 -0800 (PST) From: James Morse To: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: James Morse , D Scott Phillips OS , carl@os.amperecomputing.com, lcherian@marvell.com, bobo.shaobowang@huawei.com, tan.shaopeng@fujitsu.com, baolin.wang@linux.alibaba.com, Jamie Iles , Xin Hao , peternewman@google.com, dfustini@baylibre.com, amitsinght@marvell.com, David Hildenbrand , Dave Martin , Koba Ko , Shanker Donthineni , fenghuay@nvidia.com, baisheng.gao@unisoc.com, Jonathan Cameron , Gavin Shan , Ben Horgan , rohit.mathew@arm.com, reinette.chatre@intel.com, Punit Agrawal Subject: [RFC PATCH 37/38] arm_mpam: Add workaround for T241-MPAM-6 Date: Fri, 5 Dec 2025 21:59:00 +0000 Message-Id: <20251205215901.17772-38-james.morse@arm.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20251205215901.17772-1-james.morse@arm.com> References: <20251205215901.17772-1-james.morse@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Shanker Donthineni The registers MSMON_MBWU_L and MSMON_MBWU return the number of requests rather than the number of bytes transferred. Bandwidth resource monitoring is performed at the last level cache, where each request arrive in 64Byte granularity. The current implementation returns the number of transactions received at the last level cache but does not provide the value in bytes. Scaling by 64 gives an accurate byte count to match the MPAM specification for the MSMON_MBWU and MSMON_MBWU_L registers. This patch fixes the issue by reporting the actual number of bytes instead of the number of transactions from __ris_msmon_read(). Signed-off-by: Shanker Donthineni Signed-off-by: James Morse --- Documentation/arch/arm64/silicon-errata.rst | 2 ++ drivers/resctrl/mpam_devices.c | 24 +++++++++++++++++++-- drivers/resctrl/mpam_internal.h | 1 + 3 files changed, 25 insertions(+), 2 deletions(-) diff --git a/Documentation/arch/arm64/silicon-errata.rst b/Documentation/ar= ch/arm64/silicon-errata.rst index b18bc704d4a1..e810b2a8f40e 100644 --- a/Documentation/arch/arm64/silicon-errata.rst +++ b/Documentation/arch/arm64/silicon-errata.rst @@ -250,6 +250,8 @@ stable kernels. +----------------+-----------------+-----------------+--------------------= ---------+ | NVIDIA | T241 MPAM | T241-MPAM-4 | N/A = | +----------------+-----------------+-----------------+--------------------= ---------+ +| NVIDIA | T241 MPAM | T241-MPAM-6 | N/A = | ++----------------+-----------------+-----------------+--------------------= ---------+ +----------------+-----------------+-----------------+--------------------= ---------+ | Freescale/NXP | LS2080A/LS1043A | A-008585 | FSL_ERRATUM_A008585= | +----------------+-----------------+-----------------+--------------------= ---------+ diff --git a/drivers/resctrl/mpam_devices.c b/drivers/resctrl/mpam_devices.c index 5ba0aa703807..c17a6fdea982 100644 --- a/drivers/resctrl/mpam_devices.c +++ b/drivers/resctrl/mpam_devices.c @@ -684,6 +684,12 @@ static const struct mpam_quirk mpam_quirks[] =3D { .iidr_mask =3D MPAM_IIDR_MATCH_ONE, .workaround =3D T241_FORCE_MBW_MIN_TO_ONE, }, + { + /* NVIDIA t241 erratum T241-MPAM-6 */ + .iidr =3D MPAM_IIDR_NVIDIA_T421, + .iidr_mask =3D MPAM_IIDR_MATCH_ONE, + .workaround =3D T241_MBW_COUNTER_SCALE_64, + }, { NULL }, /* Sentinel */ }; =20 @@ -1140,7 +1146,7 @@ static void write_msmon_ctl_flt_vals(struct mon_read = *m, u32 ctl_val, } } =20 -static u64 mpam_msmon_overflow_val(enum mpam_device_features type) +static u64 __mpam_msmon_overflow_val(enum mpam_device_features type) { /* TODO: implement scaling counters */ switch (type) { @@ -1155,6 +1161,17 @@ static u64 mpam_msmon_overflow_val(enum mpam_device_= features type) } } =20 +static u64 mpam_msmon_overflow_val(enum mpam_device_features type, + struct mpam_msc *msc) +{ + u64 overflow_val =3D __mpam_msmon_overflow_val(type); + + if (mpam_has_quirk(T241_MBW_COUNTER_SCALE_64, msc)) + overflow_val *=3D 64; + + return overflow_val; +} + static void __ris_msmon_read(void *arg) { u64 now; @@ -1245,13 +1262,16 @@ static void __ris_msmon_read(void *arg) now =3D FIELD_GET(MSMON___VALUE, now); } =20 + if (mpam_has_quirk(T241_MBW_COUNTER_SCALE_64, msc)) + now *=3D 64; + if (nrdy) break; =20 mbwu_state =3D &ris->mbwu_state[ctx->mon]; =20 if (overflow) - mbwu_state->correction +=3D mpam_msmon_overflow_val(m->type); + mbwu_state->correction +=3D mpam_msmon_overflow_val(m->type, msc); =20 /* * Include bandwidth consumed before the last hardware reset and diff --git a/drivers/resctrl/mpam_internal.h b/drivers/resctrl/mpam_interna= l.h index 01882f0acee2..108a8373901c 100644 --- a/drivers/resctrl/mpam_internal.h +++ b/drivers/resctrl/mpam_internal.h @@ -224,6 +224,7 @@ struct mpam_props { enum mpam_device_quirks { T241_SCRUB_SHADOW_REGS, T241_FORCE_MBW_MIN_TO_ONE, + T241_MBW_COUNTER_SCALE_64, MPAM_QUIRK_LAST, }; =20 --=20 2.39.5 From nobody Tue Dec 16 07:34:20 2025 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 84D0D310771 for ; Fri, 5 Dec 2025 22:02:03 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764972125; cv=none; b=cYnT9+dMZENPF5CU/gwxcx7UfrgdtaI/nUunNPbrR7kY/JcX4OnzOry0pHOiwByflVBoz2LDb44fNH5/4RcuWTIj0n0yZP1+DfsUxNJq+DzUSaYWrpd3Tcgbm2grqzw9uxH2rGzs/e3u+Ov3zQNKzClIgXWxmRwrJ6oD8puqG2g= ARC-Message-Signature: i=1; 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Fri, 5 Dec 2025 14:01:58 -0800 (PST) From: James Morse To: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: James Morse , D Scott Phillips OS , carl@os.amperecomputing.com, lcherian@marvell.com, bobo.shaobowang@huawei.com, tan.shaopeng@fujitsu.com, baolin.wang@linux.alibaba.com, Jamie Iles , Xin Hao , peternewman@google.com, dfustini@baylibre.com, amitsinght@marvell.com, David Hildenbrand , Dave Martin , Koba Ko , Shanker Donthineni , fenghuay@nvidia.com, baisheng.gao@unisoc.com, Jonathan Cameron , Gavin Shan , Ben Horgan , rohit.mathew@arm.com, reinette.chatre@intel.com, Punit Agrawal Subject: [RFC PATCH 38/38] arm_mpam: Quirk CMN-650's CSU NRDY behaviour Date: Fri, 5 Dec 2025 21:59:01 +0000 Message-Id: <20251205215901.17772-39-james.morse@arm.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20251205215901.17772-1-james.morse@arm.com> References: <20251205215901.17772-1-james.morse@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" CMN-650 is afflicted with an erratum where the CSU NRDY bit never clears. This tells us the monitor never finishes scanning the cache. The erratum document says to wait the maximum time, then ignore the field. Add a flag to indicate whether this is the final attempt to read the counter, and when this quirk is applied, ignore the NRDY field. This means accesses to this counter will always retry, even if the counter was previously programmed to the same values. The counter value is not expected to be stable, it drifts up and down with each allocation and eviction. The CSU register provides the value for a point in time. Signed-off-by: James Morse --- Documentation/arch/arm64/silicon-errata.rst | 3 +++ drivers/resctrl/mpam_devices.c | 12 ++++++++++++ drivers/resctrl/mpam_internal.h | 5 +++++ 3 files changed, 20 insertions(+) diff --git a/Documentation/arch/arm64/silicon-errata.rst b/Documentation/ar= ch/arm64/silicon-errata.rst index e810b2a8f40e..3667650036fb 100644 --- a/Documentation/arch/arm64/silicon-errata.rst +++ b/Documentation/arch/arm64/silicon-errata.rst @@ -213,6 +213,9 @@ stable kernels. | ARM | GIC-700 | #2941627 | ARM64_ERRATUM_29416= 27 | +----------------+-----------------+-----------------+--------------------= ---------+ +----------------+-----------------+-----------------+--------------------= ---------+ +| ARM | CMN-650 | #3642720 | N/A = | ++----------------+-----------------+-----------------+--------------------= ---------+ ++----------------+-----------------+-----------------+--------------------= ---------+ | Broadcom | Brahma-B53 | N/A | ARM64_ERRATUM_84571= 9 | +----------------+-----------------+-----------------+--------------------= ---------+ | Broadcom | Brahma-B53 | N/A | ARM64_ERRATUM_84341= 9 | diff --git a/drivers/resctrl/mpam_devices.c b/drivers/resctrl/mpam_devices.c index c17a6fdea982..174a0224ed62 100644 --- a/drivers/resctrl/mpam_devices.c +++ b/drivers/resctrl/mpam_devices.c @@ -690,6 +690,12 @@ static const struct mpam_quirk mpam_quirks[] =3D { .iidr_mask =3D MPAM_IIDR_MATCH_ONE, .workaround =3D T241_MBW_COUNTER_SCALE_64, }, + { + /* ARM CMN-650 CSU erratum 3642720 */ + .iidr =3D MPAM_IIDR_ARM_CMN_650, + .iidr_mask =3D MPAM_IIDR_MATCH_ONE, + .workaround =3D IGNORE_CSU_NRDY, + }, { NULL }, /* Sentinel */ }; =20 @@ -997,6 +1003,7 @@ struct mon_read { enum mpam_device_features type; u64 *val; int err; + bool waited_timeout; }; =20 static bool mpam_ris_has_mbwu_long_counter(struct mpam_msc_ris *ris) @@ -1242,6 +1249,10 @@ static void __ris_msmon_read(void *arg) if (mpam_has_feature(mpam_feat_msmon_csu_hw_nrdy, rprops)) nrdy =3D now & MSMON___NRDY; now =3D FIELD_GET(MSMON___VALUE, now); + + if (mpam_has_quirk(IGNORE_CSU_NRDY, msc) && m->waited_timeout) + nrdy =3D false; + break; case mpam_feat_msmon_mbwu_31counter: case mpam_feat_msmon_mbwu_44counter: @@ -1377,6 +1388,7 @@ int mpam_msmon_read(struct mpam_component *comp, stru= ct mon_cfg *ctx, .ctx =3D ctx, .type =3D type, .val =3D val, + .waited_timeout =3D true, }; *val =3D 0; =20 diff --git a/drivers/resctrl/mpam_internal.h b/drivers/resctrl/mpam_interna= l.h index 108a8373901c..00a61e4277f5 100644 --- a/drivers/resctrl/mpam_internal.h +++ b/drivers/resctrl/mpam_internal.h @@ -225,6 +225,7 @@ enum mpam_device_quirks { T241_SCRUB_SHADOW_REGS, T241_FORCE_MBW_MIN_TO_ONE, T241_MBW_COUNTER_SCALE_64, + IGNORE_CSU_NRDY, MPAM_QUIRK_LAST, }; =20 @@ -250,6 +251,10 @@ struct mpam_quirk { FIELD_PREP_CONST(MPAMF_IIDR_REVISION, 0 ) | \ FIELD_PREP_CONST(MPAMF_IIDR_IMPLEMENTER, 0x36b) =20 +#define MPAM_IIDR_ARM_CMN_650 FIELD_PREP_CONST(MPAMF_IIDR_PRODUCTID, 0= ) | \ + FIELD_PREP_CONST(MPAMF_IIDR_VARIANT, 0 ) | \ + FIELD_PREP_CONST(MPAMF_IIDR_REVISION, 0 ) | \ + FIELD_PREP_CONST(MPAMF_IIDR_IMPLEMENTER, 0x43b) =20 /* The values for MSMON_CFG_MBWU_FLT.RWBW */ enum mon_filter_options { --=20 2.39.5