From nobody Tue Dec 16 07:41:28 2025 Received: from mail-pl1-f181.google.com (mail-pl1-f181.google.com [209.85.214.181]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0D8192DCF46 for ; Fri, 5 Dec 2025 20:28:22 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.214.181 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764966505; cv=none; b=I1VwAgyQnvKXFUVdG/aSs4gA4w1eZ5DbBL/eqpUQJtjBMB4V7EtlL+L8LvhLlaGTKoX2CClhIcBg84PQEbVTZ/FH1tDQtpNv+2ll0mlpMXMsGyumZ7jolAgwPEfecdHlKSSfPhCw7dR3hOPokqPiVL0aVeoj40cDo9ZjJlbGszs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764966505; c=relaxed/simple; bh=VhjRdW4KfUHyNC/C+mtuazEPEEU4C1nG1wSKWcNKCz8=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=u5R6gHAm6whbuNKEmU/9sp3gtT0dFlfJydzXakcTuH/0MAlcIkjd5k55L95+uE6Z2Y8qwXlUs0HTjx30aqrcDuTBpXPJrO2a82zW80DFP3WkaB4ToLqiH8iovcw07ZYfguZisUEzbg/QggDjZX6NK+RvwnhUiyqbE+8Ez4AG6Dc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=MKn1o3tU; arc=none smtp.client-ip=209.85.214.181 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="MKn1o3tU" Received: by mail-pl1-f181.google.com with SMTP id d9443c01a7336-29568d93e87so25668725ad.2 for ; Fri, 05 Dec 2025 12:28:22 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1764966502; x=1765571302; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=E1kT6K3Ob3aEghOazhmPBd7i4Md15BQDt3Jsih2JLy4=; b=MKn1o3tUnHf9twNB9HPSWc72dHvYzvEZMSPZXLxM5ktt1RAM41qAwCqwxXhlebs4Ua 2WzKVwjK4gnZYZ9e+DIURGJu3+tUZXvcwhFdML7bZ8z6nlfkU+9Fbp1ubJfxPf6OYQ9z JeN38YGOB7XOYh7TM9m9GkhKFTQZqX8yWUlT0kX992xjHPeRadtGqsqNbvnHgPbdjrYD dLx55JDxe+nJiklEk0yA0RzMKLx8tzMpIiEDWC4oMgzlv/H7kfaoDgFXdqTRApxemIn+ mMwuYcCMPgIjEKBTZMklSXLAPRWNOD6K95SbBph6c+XKJbzajGvBI5p5zVvof40/ESLp YWlA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1764966502; x=1765571302; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=E1kT6K3Ob3aEghOazhmPBd7i4Md15BQDt3Jsih2JLy4=; b=ggcNBaycOe9gcxi9YdDHWdVOcGYltXuXzIMYk+NImB5CFMEv806UHut1wTDZiHilk5 2oNmuFHIDmqqHLfl1SaTpFt1eB9+aPQ9aRKU5UoZ6tv6UXrTAz9TG2WdYOGUTBHPgTG6 foXLO4pAO4PyCr7RIdGcifvhoQ/DMKCDR4d7wrLPnQAUU9eyZWG/v208HxBx2Fp5hfc2 +xQr8JDXrZVZmeMsISLRDU8dXjAx0jRlxkT+iO9/nh2bN7nb7YYdMti4jhCX9f7HdLSf Yrs8AiN/Hw6J9ZLV0uZy6lCPcFjaaLw51pWaM/Z2Jp+YrcIeLjaR2g2j9uRIR8QPtPC4 KVPA== X-Forwarded-Encrypted: i=1; AJvYcCUUpsGtEfRjX62YS2pETnL0fkEyvY5kv/eXKHzhtbJ3IAxwk8ciOpSbvNdkUiIfmnNdjX6ryhlA/vJaycM=@vger.kernel.org X-Gm-Message-State: AOJu0YwHvLtaLlrcinwj0QhZTRpt+7UtXnNavttgF57VTllc75Ff1JNX PVQDd60E2BfP+zkuHqWEnsJkLo5fKhqP5NHQkhd6sH8NxR8vCiXP7+my X-Gm-Gg: ASbGncuZOmLdzBOYRj0nrcjyQkTA2b1VmwQavmM3X9kaxhOW9l3RXoa/IKI2Oq2MwMO NDxAMh1oMQoOvABqv1ztBR9F/glKmh0Ck7ksdOFvgMI9gnY/0Qpu0YWfj0G1Epf5chzRm3gMDGf Db/cpIhVFLvVK1Y4TRL2nbC1Z7I/F4oJXHDU60uH4ZghR86Nn87DJ2LKEsqzYtYPa+SX0JCIEnH NDmiYrdF1Fy1wAdd9f0kICQJ0x3DMj/TyaTHRv22pMpcgy33wriK1JkxDAWueSu4awKL4XyK2y+ KAgcYA3qNdmcj4zW5/X/IuMkoawLWkLMq1BnRJrRbSAE6FRc/Wt3vraoHxfqD3b+E1YJCUA0eTM oKjjB3eZhTvTpc8/2cJnUYcsQWWau8nzIhv2ZIpigdDB3jqez0dE4pdN669D/asdKbbZ2aS95Ge QTsb+uVZEaWncgQ1cbvCYbvGt/X6xuKNtxsZ2Vo9BDJsvKAVOFyU0sPhormX3zd3dsuS40v2zbn LkGTbL6V+Gzcz/FhGtoOtKtvDRsBj+zDVmNI0br8uWSRGEwQdez7InezBQhTczcyOCjRN18 X-Google-Smtp-Source: AGHT+IFTMT5Gqt3zxUUZz4Uief0KidTbdHtVVj8Bdg+zDGW3adOU9RZX8JRZKLTJtpJNPMg3XEQQqQ== X-Received: by 2002:a17:902:e783:b0:296:3f23:b93b with SMTP id d9443c01a7336-29df5a9d23fmr1726475ad.2.1764966502353; Fri, 05 Dec 2025 12:28:22 -0800 (PST) Received: from Lewboski.localdomain ([181.191.143.42]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-29dae99fa59sm57256845ad.58.2025.12.05.12.28.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 05 Dec 2025 12:28:22 -0800 (PST) From: Tomas Borquez To: Jonathan Cameron , Lars-Peter Clausen , Michael Hennerich , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Greg Kroah-Hartman Cc: David Lechner , =?UTF-8?q?Nuno=20S=C3=A1?= , Andy Shevchenko , linux-iio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-staging@lists.linux.dev, Tomas Borquez Subject: [RFC PATCH 1/3] staging: iio: ad9832: remove platform_data support Date: Fri, 5 Dec 2025 17:27:41 -0300 Message-ID: <20251205202743.10530-2-tomasborquez13@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20251205202743.10530-1-tomasborquez13@gmail.com> References: <20251205202743.10530-1-tomasborquez13@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Remove legacy platform_data support as there are no in tree users and this approach belongs to a long gone era. The policy decision on what to output is a userspace problem, not something that should be provided from firmware. The driver now initializes the device to a safe state (SLEEP|RESET|CLR) outputting nothing. Userspace can configure the desired frequencies and phases via the existing sysfs attributes once the device is ready to be=20 used. Original discussion started here [1]. Link: https://lore.kernel.org/linux-iio/20250628161040.3d21e2c4@jic23-huawe= i/ [1] Suggested-by: Jonathan Cameron Signed-off-by: Tomas Borquez Reviewed-by: Andy Shevchenko --- drivers/staging/iio/frequency/ad9832.c | 32 ------------------------- drivers/staging/iio/frequency/ad9832.h | 33 -------------------------- 2 files changed, 65 deletions(-) delete mode 100644 drivers/staging/iio/frequency/ad9832.h diff --git a/drivers/staging/iio/frequency/ad9832.c b/drivers/staging/iio/f= requency/ad9832.c index 49388da5a6..e2ad3e5a7a 100644 --- a/drivers/staging/iio/frequency/ad9832.c +++ b/drivers/staging/iio/frequency/ad9832.c @@ -23,8 +23,6 @@ #include #include =20 -#include "ad9832.h" - #include "dds.h" =20 /* Registers */ @@ -299,16 +297,10 @@ static const struct iio_info ad9832_info =3D { =20 static int ad9832_probe(struct spi_device *spi) { - struct ad9832_platform_data *pdata =3D dev_get_platdata(&spi->dev); struct iio_dev *indio_dev; struct ad9832_state *st; int ret; =20 - if (!pdata) { - dev_dbg(&spi->dev, "no platform data?\n"); - return -ENODEV; - } - indio_dev =3D devm_iio_device_alloc(&spi->dev, sizeof(*st)); if (!indio_dev) return -ENOMEM; @@ -379,30 +371,6 @@ static int ad9832_probe(struct spi_device *spi) return ret; } =20 - ret =3D ad9832_write_frequency(st, AD9832_FREQ0HM, pdata->freq0); - if (ret) - return ret; - - ret =3D ad9832_write_frequency(st, AD9832_FREQ1HM, pdata->freq1); - if (ret) - return ret; - - ret =3D ad9832_write_phase(st, AD9832_PHASE0H, pdata->phase0); - if (ret) - return ret; - - ret =3D ad9832_write_phase(st, AD9832_PHASE1H, pdata->phase1); - if (ret) - return ret; - - ret =3D ad9832_write_phase(st, AD9832_PHASE2H, pdata->phase2); - if (ret) - return ret; - - ret =3D ad9832_write_phase(st, AD9832_PHASE3H, pdata->phase3); - if (ret) - return ret; - return devm_iio_device_register(&spi->dev, indio_dev); } =20 diff --git a/drivers/staging/iio/frequency/ad9832.h b/drivers/staging/iio/f= requency/ad9832.h deleted file mode 100644 index d0d840edb8..0000000000 --- a/drivers/staging/iio/frequency/ad9832.h +++ /dev/null @@ -1,33 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * AD9832 SPI DDS driver - * - * Copyright 2011 Analog Devices Inc. - */ -#ifndef IIO_DDS_AD9832_H_ -#define IIO_DDS_AD9832_H_ - -/* - * TODO: struct ad9832_platform_data needs to go into include/linux/iio - */ - -/** - * struct ad9832_platform_data - platform specific information - * @freq0: power up freq0 tuning word in Hz - * @freq1: power up freq1 tuning word in Hz - * @phase0: power up phase0 value [0..4095] correlates with 0..2PI - * @phase1: power up phase1 value [0..4095] correlates with 0..2PI - * @phase2: power up phase2 value [0..4095] correlates with 0..2PI - * @phase3: power up phase3 value [0..4095] correlates with 0..2PI - */ - -struct ad9832_platform_data { - unsigned long freq0; - unsigned long freq1; - unsigned short phase0; - unsigned short phase1; - unsigned short phase2; - unsigned short phase3; -}; - -#endif /* IIO_DDS_AD9832_H_ */ --=20 2.43.0 From nobody Tue Dec 16 07:41:28 2025 Received: from mail-pl1-f169.google.com (mail-pl1-f169.google.com [209.85.214.169]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 931502D3A96 for ; Fri, 5 Dec 2025 20:28:28 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.214.169 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764966510; cv=none; b=PFdvPk0foCbwccmlfb94vMCYnGzuIFgoxKVnl0yWUdirm2ywRS7HFhs3MiOY7wF/ejQikZL9PUFofDeypcnjEnP+ArWKgqqUPF5tdMxFglXYwDGpidsa8C9Uqq3idt3Wv0N/VD4MunCwW6hSHhDSnrOLbV1nsjubU01reaeN8Bc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764966510; c=relaxed/simple; bh=fuS5ThsXhqrYsuTOSDf0ZJ72zB84bz5qASa0OMJmDbo=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=KP1K4GfnJ9xrSShReuqzmr3QnU1NGms0/XrsOv/3rpXCtujWQIdWV//wbLNbCXHRKsdb/W3g82EunIMNfmWbzzBDfOn0h0c1zDdlzl0abukYjIxjFZ6UDt8JnaGpJrq4VB1QmFLaBDL4+5SVyQSr8wLj1TSU/9s5nziwzMsF2hs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=CzfuRrA2; arc=none smtp.client-ip=209.85.214.169 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="CzfuRrA2" Received: by mail-pl1-f169.google.com with SMTP id d9443c01a7336-29586626fbeso31644025ad.0 for ; Fri, 05 Dec 2025 12:28:28 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1764966508; x=1765571308; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=dQNcQPNLKKY2BeCq1O0OFp8TedTaZIsxUpeca8Qcn0U=; b=CzfuRrA2syWwWyxiTu48XIP8EwQxVLs/wt4/++c+cnJYc4p7/HvhaqGkQNXHEhoEw2 veJriLCZYSK3Tl8/NEMxz/lPCe/mvePILEFFLdhPHaRJIv3lydycHy9DeXZX7rQTdUwJ EBCpI1IresFZjX3gCkohnEEICS8qcFb/PpZotwUhRbmbzcdPi2I6foL8ZSHRyL5nuimG WX9ffGuw51p7WcYkRaZrfWtS295GQqiFxeEnapN2UY8lzSvCxYYCXYrGgblKkbmru9r3 REZpMwqobiSvVroneMJKkx19YTi02+z9mnNb3Do6CtGerS4ZpJp2rqamC2cJQeOU+oRU P95A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1764966508; x=1765571308; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=dQNcQPNLKKY2BeCq1O0OFp8TedTaZIsxUpeca8Qcn0U=; b=HMs5YO130np1TDM0m/gvd1wgabg3gteXspkAvs15m4wkymfwWw+/+6MQzhqiFPTBE1 yPiGe2Ubbi/9sZkH0chkBd/LCC7b4qnMh7fxbcrzqOi6s9js+Naq2PKcHNiLcsv3fi1Q TbAXs5h5qOloYfwh1f/B8Tlf89C3Qxwl5lwKzpwl66aUQYxsWKxsmfAHLiFUF6cLvOsK Y76YPTu489uHdccepoC56FJiJJboMlD/CEUHHw+FVpDbbYVLBv9fCIRUV1ptx34yYYuk iJpCIu4Pn/tf6j+2jDpJ3FPKOhQ4KyGxYD5TNbvlFjQ5vDfuFudqHjGqr8kO8a0l8sUl 4A0A== X-Forwarded-Encrypted: i=1; AJvYcCVhtd9fv0P0Mp18Ae+O69Pq44lBx8jo2JcAQtYph/mH+h908h01Nfy/9mcadUWXLSLyN39Dloc5CjDfHSU=@vger.kernel.org X-Gm-Message-State: AOJu0Yz5XGpawFHPnKerPOST3UPtJRjUpylBcodUy1tlY9qvadp+tOeV n/W4q8RSSzNOD38HAHDnqXcHhA9dQamOREIr4BzuH1yCa1YGtrYiauz/ X-Gm-Gg: ASbGncuGtpCMXgJgsc2jb7gBrrvejAsy5kL9mDC95gGu4o3uOvrNitB941KrLsx9/v7 YwxreNGj9uL7PRMgcFx9Jo3mkTYH7poF+IhyFAvsYeQSp0TDQBz1bqhIF7DI7CMRY84qEVDYv1N a3cnuP8aYQkbYlqnI9Ul7u9Cl0gZYm225w9QXEljBJxOXutbuDpEbG1tJZupCbKLt8ijwVsmBvz OKymBoO7ivu1fGJJUMmZEuENVzWv9YKSHxohjV2azvHzdyVhK8eLnAWyhfxE1TFNvbP+X0FYfuK nvPUxYwuJStnkC3iboKPZpxY349x5DvXs/u1lQRS5sQoUrVYQQxkjVFIjlFhDWX8seOzmSPJTo1 B6vQfyAnPsVSrTUKB35aF4C3IjeS3e/Y4NqgPfDmG7OTwAyOUUlhFs1G251hv4ALPS+4cL1PYve qM2P3uabT6I19GCs+bUoGZ+oT6m0ZW5pqG9FnLw3rbsbQLLxaPOpzEWPE1YBvs7Vk499BPdIZd3 r3SYjE2vgJWWsQQJHGfZLEVcXYSCst55PUvD0e0NAXn3A7b5lCsmUSDhuuwutoK05N4kFw+ZQb5 UKfzHqM= X-Google-Smtp-Source: AGHT+IGLHZapmXgdKrIKPSCz1pMcaFW0HtbEIVANbV6SbOUsG6gLOejCmPAUZXk9+6nCOOKIUe5tbQ== X-Received: by 2002:a17:903:178b:b0:29d:f653:17c0 with SMTP id d9443c01a7336-29df6531a61mr1749905ad.12.1764966507675; Fri, 05 Dec 2025 12:28:27 -0800 (PST) Received: from Lewboski.localdomain ([181.191.143.42]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-29dae99fa59sm57256845ad.58.2025.12.05.12.28.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 05 Dec 2025 12:28:27 -0800 (PST) From: Tomas Borquez To: Jonathan Cameron , Lars-Peter Clausen , Michael Hennerich , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Greg Kroah-Hartman Cc: David Lechner , =?UTF-8?q?Nuno=20S=C3=A1?= , Andy Shevchenko , linux-iio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-staging@lists.linux.dev, Tomas Borquez Subject: [RFC PATCH 2/3] staging: iio: ad9832: convert to iio channels Date: Fri, 5 Dec 2025 17:27:42 -0300 Message-ID: <20251205202743.10530-3-tomasborquez13@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20251205202743.10530-1-tomasborquez13@gmail.com> References: <20251205202743.10530-1-tomasborquez13@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Replace the custom frequency and phase sysfs attributes with IIO channels using read_raw()/write_raw() callbacks, as well as removing the dds.h header. Changes: - Add iio_chan_spec definitions for 2 frequency and 4 phase channels. - Implement read_raw/write_raw for IIO_CHAN_INFO_FREQUENCY/PHASE. - Cache frequency and phase values in driver state for readback. - Remove dependency on dds.h macros for sysfs. - Use guard(mutex) for cleaner locking. - Add input validation and consistent error messages. NOTE: This changes the userspace ABI, see cover letter. Signed-off-by: Tomas Borquez --- drivers/staging/iio/frequency/ad9832.c | 232 ++++++++++++++++++------- 1 file changed, 168 insertions(+), 64 deletions(-) diff --git a/drivers/staging/iio/frequency/ad9832.c b/drivers/staging/iio/f= requency/ad9832.c index e2ad3e5a7a..79d26009d1 100644 --- a/drivers/staging/iio/frequency/ad9832.c +++ b/drivers/staging/iio/frequency/ad9832.c @@ -9,6 +9,7 @@ =20 #include #include +#include #include #include #include @@ -23,10 +24,7 @@ #include #include =20 -#include "dds.h" - /* Registers */ - #define AD9832_FREQ0LL 0x0 #define AD9832_FREQ0HL 0x1 #define AD9832_FREQ0LM 0x2 @@ -50,7 +48,6 @@ #define AD9832_OUTPUT_EN 0x13 =20 /* Command Control Bits */ - #define AD9832_CMD_PHA8BITSW 0x1 #define AD9832_CMD_PHA16BITSW 0x0 #define AD9832_CMD_FRE8BITSW 0x3 @@ -79,6 +76,8 @@ * @ctrl_fp: cached frequency/phase control word * @ctrl_ss: cached sync/selsrc control word * @ctrl_src: cached sleep/reset/clr word + * @freq: cached frequencies + * @phase: cached phases * @xfer: default spi transfer * @msg: default spi message * @freq_xfer: tuning word spi transfer @@ -90,13 +89,14 @@ * @phase_data: tuning word spi transmit buffer * @freq_data: tuning word spi transmit buffer */ - struct ad9832_state { struct spi_device *spi; struct clk *mclk; unsigned short ctrl_fp; unsigned short ctrl_ss; unsigned short ctrl_src; + u32 freq[2]; + u32 phase[4]; struct spi_transfer xfer; struct spi_message msg; struct spi_transfer freq_xfer[4]; @@ -115,7 +115,7 @@ struct ad9832_state { } __aligned(IIO_DMA_MINALIGN); }; =20 -static unsigned long ad9832_calc_freqreg(unsigned long mclk, unsigned long= fout) +static unsigned long ad9832_calc_freqreg(unsigned long mclk, u32 fout) { unsigned long long freqreg =3D (u64)fout * (u64)((u64)1L << AD9832_FREQ_BITS); @@ -124,12 +124,24 @@ static unsigned long ad9832_calc_freqreg(unsigned lon= g mclk, unsigned long fout) } =20 static int ad9832_write_frequency(struct ad9832_state *st, - unsigned int addr, unsigned long fout) + unsigned int addr, u32 fout) { unsigned long clk_freq; unsigned long regval; u8 regval_bytes[4]; u16 freq_cmd; + int ret, idx; + + switch (addr) { + case AD9832_FREQ0HM: + idx =3D 0; + break; + case AD9832_FREQ1HM: + idx =3D 1; + break; + default: + return -EINVAL; + } =20 clk_freq =3D clk_get_rate(st->mclk); =20 @@ -147,14 +159,37 @@ static int ad9832_write_frequency(struct ad9832_state= *st, FIELD_PREP(AD9832_DAT_MSK, regval_bytes[i])); } =20 - return spi_sync(st->spi, &st->freq_msg); + ret =3D spi_sync(st->spi, &st->freq_msg); + if (ret) + return ret; + + st->freq[idx] =3D fout; + return 0; } =20 static int ad9832_write_phase(struct ad9832_state *st, - unsigned long addr, unsigned long phase) + unsigned long addr, u32 phase) { u8 phase_bytes[2]; u16 phase_cmd; + int ret, idx; + + switch (addr) { + case AD9832_PHASE0H: + idx =3D 0; + break; + case AD9832_PHASE1H: + idx =3D 1; + break; + case AD9832_PHASE2H: + idx =3D 2; + break; + case AD9832_PHASE3H: + idx =3D 3; + break; + default: + return -EINVAL; + } =20 if (phase >=3D BIT(AD9832_PHASE_BITS)) return -EINVAL; @@ -169,10 +204,77 @@ static int ad9832_write_phase(struct ad9832_state *st, FIELD_PREP(AD9832_DAT_MSK, phase_bytes[i])); } =20 - return spi_sync(st->spi, &st->phase_msg); + ret =3D spi_sync(st->spi, &st->phase_msg); + if (ret) + return ret; + + st->phase[idx] =3D phase; + return 0; } =20 -static ssize_t ad9832_write(struct device *dev, struct device_attribute *a= ttr, +static int ad9832_write_raw(struct iio_dev *indio_dev, + struct iio_chan_spec const *chan, + int val, int val2, long mask) +{ + struct ad9832_state *st =3D iio_priv(indio_dev); + + if (val < 0) + return -EINVAL; + + guard(mutex)(&st->lock); + switch (mask) { + case IIO_CHAN_INFO_FREQUENCY: + return ad9832_write_frequency(st, chan->address, val); + case IIO_CHAN_INFO_PHASE: + return ad9832_write_phase(st, chan->address, val); + default: + return -EINVAL; + } +} + +static int ad9832_read_raw(struct iio_dev *indio_dev, + struct iio_chan_spec const *chan, + int *val, int *val2, long mask) +{ + struct ad9832_state *st =3D iio_priv(indio_dev); + + guard(mutex)(&st->lock); + switch (mask) { + case IIO_CHAN_INFO_FREQUENCY: + switch (chan->address) { + case AD9832_FREQ0HM: + *val =3D st->freq[0]; + return IIO_VAL_INT; + case AD9832_FREQ1HM: + *val =3D st->freq[1]; + return IIO_VAL_INT; + default: + return -EINVAL; + } + case IIO_CHAN_INFO_PHASE: + switch (chan->address) { + case AD9832_PHASE0H: + *val =3D st->phase[0]; + return IIO_VAL_INT; + case AD9832_PHASE1H: + *val =3D st->phase[1]; + return IIO_VAL_INT; + case AD9832_PHASE2H: + *val =3D st->phase[2]; + return IIO_VAL_INT; + case AD9832_PHASE3H: + *val =3D st->phase[3]; + return IIO_VAL_INT; + default: + return -EINVAL; + } + default: + return -EINVAL; + } +} + +static ssize_t ad9832_store(struct device *dev, + struct device_attribute *attr, const char *buf, size_t len) { struct iio_dev *indio_dev =3D dev_to_iio_dev(dev); @@ -183,20 +285,10 @@ static ssize_t ad9832_write(struct device *dev, struc= t device_attribute *attr, =20 ret =3D kstrtoul(buf, 10, &val); if (ret) - goto error_ret; + return ret; =20 - mutex_lock(&st->lock); - switch ((u32)this_attr->address) { - case AD9832_FREQ0HM: - case AD9832_FREQ1HM: - ret =3D ad9832_write_frequency(st, this_attr->address, val); - break; - case AD9832_PHASE0H: - case AD9832_PHASE1H: - case AD9832_PHASE2H: - case AD9832_PHASE3H: - ret =3D ad9832_write_phase(st, this_attr->address, val); - break; + guard(mutex)(&st->lock); + switch (this_attr->address) { case AD9832_PINCTRL_EN: st->ctrl_ss &=3D ~AD9832_SELSRC; st->ctrl_ss |=3D FIELD_PREP(AD9832_SELSRC, val ? 0 : 1); @@ -206,13 +298,13 @@ static ssize_t ad9832_write(struct device *dev, struc= t device_attribute *attr, ret =3D spi_sync(st->spi, &st->msg); break; case AD9832_FREQ_SYM: - if (val =3D=3D 1 || val =3D=3D 0) { - st->ctrl_fp &=3D ~AD9832_FREQ; - st->ctrl_fp |=3D FIELD_PREP(AD9832_FREQ, val ? 1 : 0); - } else { + if (val !=3D 1 && val !=3D 0) { ret =3D -EINVAL; break; } + + st->ctrl_fp &=3D ~AD9832_FREQ; + st->ctrl_fp |=3D FIELD_PREP(AD9832_FREQ, val); st->data =3D cpu_to_be16(FIELD_PREP(AD9832_CMD_MSK, AD9832_CMD_FPSELECT)= | st->ctrl_fp); ret =3D spi_sync(st->spi, &st->msg); @@ -243,47 +335,56 @@ static ssize_t ad9832_write(struct device *dev, struc= t device_attribute *attr, default: ret =3D -ENODEV; } - mutex_unlock(&st->lock); =20 -error_ret: return ret ? ret : len; } =20 -/* - * see dds.h for further information - */ +#define AD9832_CHAN_FREQ(_channel, _addr) { \ + .type =3D IIO_ALTVOLTAGE, \ + .output =3D 1, \ + .indexed =3D 1, \ + .channel =3D _channel, \ + .address =3D _addr, \ + .info_mask_separate =3D BIT(IIO_CHAN_INFO_FREQUENCY), \ +} =20 -static IIO_DEV_ATTR_FREQ(0, 0, 0200, NULL, ad9832_write, AD9832_FREQ0HM); -static IIO_DEV_ATTR_FREQ(0, 1, 0200, NULL, ad9832_write, AD9832_FREQ1HM); -static IIO_DEV_ATTR_FREQSYMBOL(0, 0200, NULL, ad9832_write, AD9832_FREQ_SY= M); -static IIO_CONST_ATTR_FREQ_SCALE(0, "1"); /* 1Hz */ +#define AD9832_CHAN_PHASE(_channel, _addr) { \ + .type =3D IIO_ALTVOLTAGE, \ + .output =3D 1, \ + .indexed =3D 1, \ + .channel =3D _channel, \ + .address =3D _addr, \ + .info_mask_separate =3D BIT(IIO_CHAN_INFO_PHASE), \ +} + +static const struct iio_chan_spec ad9832_channels[] =3D { + AD9832_CHAN_FREQ(0, AD9832_FREQ0HM), + AD9832_CHAN_FREQ(1, AD9832_FREQ1HM), + AD9832_CHAN_PHASE(2, AD9832_PHASE0H), + AD9832_CHAN_PHASE(3, AD9832_PHASE1H), + AD9832_CHAN_PHASE(4, AD9832_PHASE2H), + AD9832_CHAN_PHASE(5, AD9832_PHASE3H), +}; =20 -static IIO_DEV_ATTR_PHASE(0, 0, 0200, NULL, ad9832_write, AD9832_PHASE0H); -static IIO_DEV_ATTR_PHASE(0, 1, 0200, NULL, ad9832_write, AD9832_PHASE1H); -static IIO_DEV_ATTR_PHASE(0, 2, 0200, NULL, ad9832_write, AD9832_PHASE2H); -static IIO_DEV_ATTR_PHASE(0, 3, 0200, NULL, ad9832_write, AD9832_PHASE3H); -static IIO_DEV_ATTR_PHASESYMBOL(0, 0200, NULL, - ad9832_write, AD9832_PHASE_SYM); -static IIO_CONST_ATTR_PHASE_SCALE(0, "0.0015339808"); /* 2PI/2^12 rad*/ +static IIO_CONST_ATTR(out_altvoltage_frequency_scale, "1"); /* 1Hz */ +static IIO_CONST_ATTR(out_altvoltage_phase_scale, "0.0015339808"); /* 2PI = / 2^12 rad */ =20 -static IIO_DEV_ATTR_PINCONTROL_EN(0, 0200, NULL, - ad9832_write, AD9832_PINCTRL_EN); -static IIO_DEV_ATTR_OUT_ENABLE(0, 0200, NULL, - ad9832_write, AD9832_OUTPUT_EN); +static IIO_DEVICE_ATTR(out_altvoltage_frequencysymbol, 0200, NULL, + ad9832_store, AD9832_FREQ_SYM); +static IIO_DEVICE_ATTR(out_altvoltage_phasesymbol, 0200, NULL, + ad9832_store, AD9832_PHASE_SYM); +static IIO_DEVICE_ATTR(out_altvoltage_out_enable, 0200, NULL, + ad9832_store, AD9832_OUTPUT_EN); +static IIO_DEVICE_ATTR(out_altvoltage_pincontrol_en, 0200, NULL, + ad9832_store, AD9832_PINCTRL_EN); =20 static struct attribute *ad9832_attributes[] =3D { - &iio_dev_attr_out_altvoltage0_frequency0.dev_attr.attr, - &iio_dev_attr_out_altvoltage0_frequency1.dev_attr.attr, - &iio_const_attr_out_altvoltage0_frequency_scale.dev_attr.attr, - &iio_dev_attr_out_altvoltage0_phase0.dev_attr.attr, - &iio_dev_attr_out_altvoltage0_phase1.dev_attr.attr, - &iio_dev_attr_out_altvoltage0_phase2.dev_attr.attr, - &iio_dev_attr_out_altvoltage0_phase3.dev_attr.attr, - &iio_const_attr_out_altvoltage0_phase_scale.dev_attr.attr, - &iio_dev_attr_out_altvoltage0_pincontrol_en.dev_attr.attr, - &iio_dev_attr_out_altvoltage0_frequencysymbol.dev_attr.attr, - &iio_dev_attr_out_altvoltage0_phasesymbol.dev_attr.attr, - &iio_dev_attr_out_altvoltage0_out_enable.dev_attr.attr, + &iio_const_attr_out_altvoltage_frequency_scale.dev_attr.attr, + &iio_const_attr_out_altvoltage_phase_scale.dev_attr.attr, + &iio_dev_attr_out_altvoltage_frequencysymbol.dev_attr.attr, + &iio_dev_attr_out_altvoltage_phasesymbol.dev_attr.attr, + &iio_dev_attr_out_altvoltage_out_enable.dev_attr.attr, + &iio_dev_attr_out_altvoltage_pincontrol_en.dev_attr.attr, NULL, }; =20 @@ -292,6 +393,8 @@ static const struct attribute_group ad9832_attribute_gr= oup =3D { }; =20 static const struct iio_info ad9832_info =3D { + .write_raw =3D ad9832_write_raw, + .read_raw =3D ad9832_read_raw, .attrs =3D &ad9832_attribute_group, }; =20 @@ -309,15 +412,15 @@ static int ad9832_probe(struct spi_device *spi) =20 ret =3D devm_regulator_get_enable(&spi->dev, "avdd"); if (ret) - return dev_err_probe(&spi->dev, ret, "failed to enable specified AVDD vo= ltage\n"); + return dev_err_probe(&spi->dev, ret, "failed to enable AVDD supply\n"); =20 ret =3D devm_regulator_get_enable(&spi->dev, "dvdd"); if (ret) - return dev_err_probe(&spi->dev, ret, "Failed to enable specified DVDD su= pply\n"); + return dev_err_probe(&spi->dev, ret, "failed to enable DVDD supply\n"); =20 st->mclk =3D devm_clk_get_enabled(&spi->dev, "mclk"); if (IS_ERR(st->mclk)) - return PTR_ERR(st->mclk); + return dev_err_probe(&spi->dev, PTR_ERR(st->mclk), "failed to enable MCL= K\n"); =20 st->spi =3D spi; mutex_init(&st->lock); @@ -325,9 +428,10 @@ static int ad9832_probe(struct spi_device *spi) indio_dev->name =3D spi_get_device_id(spi)->name; indio_dev->info =3D &ad9832_info; indio_dev->modes =3D INDIO_DIRECT_MODE; + indio_dev->channels =3D ad9832_channels; + indio_dev->num_channels =3D ARRAY_SIZE(ad9832_channels); =20 /* Setup default messages */ - st->xfer.tx_buf =3D &st->data; st->xfer.len =3D 2; =20 --=20 2.43.0 From nobody Tue Dec 16 07:41:28 2025 Received: from mail-pl1-f180.google.com (mail-pl1-f180.google.com [209.85.214.180]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 977EE2DF146 for ; Fri, 5 Dec 2025 20:28:34 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.214.180 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764966517; cv=none; b=byitB4L+OBTaxs67guQKtnpfmC+A9BwhZeb+kbOokXsS8cgXOMmrSe6iMSZXQn6vpwurdyeM5clw1j+i5hjox7XbskcYD+dbv8YdYroA37eKxyM15hNSXeEvAcREdC3iQP5CAzibuJMDY19050dSwfu7KtfHQ22oPtfF7b7NG7g= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764966517; c=relaxed/simple; bh=azE6/sKR/pDr9h9pZaYF+h/EQIlraEjWOI9ZhVf1gRY=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=gsvzSaNZ8FZab3UqPMFnIu+qYDpx2H2GCsuianzeLmFfnLGcaaKS2hZnZOdXz3N3aFXCn1SEyhThnqV7GRNRseRR84ixdJ/OzKevhDkGx2UuQQc/UKxG7GAp8/IZYzUWu90iAV2S5rO7Dt2fKUAkpxy6Y6qBguRgaD7ei+eFei8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=npHRtsDJ; arc=none smtp.client-ip=209.85.214.180 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="npHRtsDJ" Received: by mail-pl1-f180.google.com with SMTP id d9443c01a7336-2981f9ce15cso34109885ad.1 for ; Fri, 05 Dec 2025 12:28:34 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1764966514; x=1765571314; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=ZogGanCrO7NukEfQvdNpvWFAmgObDEJxIVV+nj78Ze8=; b=npHRtsDJp48VnC2VrZNWvGLIH9YiQ+JDzbwASp334iq87bDXzW3/MYuQNRvkJxWciK TXmXJ6qkjHnOXTLZL7F57F/XdX+Twg+IaY5KOnEU2V5JVlM9ZZTQIWpM0maL0IROGSgE N1miSjXh3rswK66brjmxSDvSbuQcbLpD3DXYLskI60IxDRfZUAtioxEaFR9mdWsfj1F5 +EH6DmxZdW3L9uwdaP5r8TgQrCPwfPNY3x9mrnK53VNR0DIly0+vmxuOd+x5Nav7SOua 3MCQ3K+NqXi0ss5T0huP2ATCmC333c8+2WLhP/KF5ROTWGL3tAaGMKHqMnEpwrvFPkby 7fbA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1764966514; x=1765571314; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=ZogGanCrO7NukEfQvdNpvWFAmgObDEJxIVV+nj78Ze8=; b=xGLbljxC6cr37WRnq0I1IIGboXQVtMMUTK05QpE4BRs8B7jeXF/fEDFH5yhJ2V52YG ZDCLWjwb2hoOVd0XvXqj/EWNvDKyO/+68+f3WVqQWMGo0oBp70l66CV/7ZBKxmmh6SkR GSqpPveaZ+2QSE+JSkfRwttNjZTXVIjaamvul6G1EJOLwQ3Q4I/wwDB77eVEUR7KfB30 MUQuRRTwL1XufwWrUiU6plL8a78JhsOKqFSacGFbHNCSanA9uY+N1L4ISN54wZbeH+U1 Nywgfqkec2yzRVboZCVeZesnF0CsxSBsJKAWBZw4ixk0BqeAGQsZOuoOR5EzpVFpxA19 aqYA== X-Forwarded-Encrypted: i=1; AJvYcCVbHBDVNZ046l86aDFc2ybRGjLTXW/bARh1bpCkSg/Yy3mTQq2A2iQKrpQnWFuHI2jdctb7SaMtoNc5zDM=@vger.kernel.org X-Gm-Message-State: AOJu0YwORAVB3yunVhvcnJLzCt0DMb5m5Z5ewv9jUfNHgiWGHHCFvNGI 1cYPkWrLWoNKhdq5RRKi6C+ik1XmeGZ54JyZI7v7AMMcmTwwJHHEBFYr X-Gm-Gg: ASbGncsDImsj/0Vz2JBn9uxWGEMruQDSBSxmbHcfConKmR//vHjCCC2A9ublRgErkP3 Fw38EVxfZZqBs/OC2Q7blZYGV79IEk4DaHwTqI4vDLAANjkmRZBfHTlPvQ89M8yzOnr8qiDAthP IqSyP2UhHJ1cXW0v4TjkEGqKW508EoJcaS5ACz1z+ez81VZj+CbtTLQfFsvhUl8YwWelMM5KiNE 5cqqzBOwulj3xDLFH2UazzFmhYoW21njGL7g15Csbd708Dh4q9Id9xu7eiiDE/xLusbsIrl3HoY qeECpfIMfYB1FsEevaWUQqDS4qM+h2WXGtqXQwITe0Zbs/EaBft3Lymw8fSeWYpl0EULZllkn+9 psC0JHNQxCy+LT39HsFmCb1yPI1rR/GBWHWKnGSohqyTQphWg9PjD8Y7NA56dRHq0Umvr7tL5PO sU8469EzROBJz0U3Flf65UTVeAdnxurSXNEWSp3EmOfY/kb6Ek2T6Q92EU5zKeS7jrClq8iKOyO swPk7A1AgEXZB0dgbvJhFc8Q0ggos3J/GXkwy2NBuplVr/K8ZuCnvMd2ypBzp7G+3q3BHm/ X-Google-Smtp-Source: AGHT+IF1wT7Td3ZI2BC55SXXYAJaxCzsMe1hAMjfGfhAUPysLAPT7MMB+HubIzcEFfpLuQKK5R0Glg== X-Received: by 2002:a17:902:cf0b:b0:297:fbff:fab8 with SMTP id d9443c01a7336-29df54761c4mr2295905ad.21.1764966513935; Fri, 05 Dec 2025 12:28:33 -0800 (PST) Received: from Lewboski.localdomain ([181.191.143.42]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-29dae99fa59sm57256845ad.58.2025.12.05.12.28.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 05 Dec 2025 12:28:33 -0800 (PST) From: Tomas Borquez To: Jonathan Cameron , Lars-Peter Clausen , Michael Hennerich , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Greg Kroah-Hartman Cc: David Lechner , =?UTF-8?q?Nuno=20S=C3=A1?= , Andy Shevchenko , linux-iio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-staging@lists.linux.dev, Tomas Borquez Subject: [RFC PATCH 3/3] dt-bindings: iio: add analog devices ad9832/ad9835 Date: Fri, 5 Dec 2025 17:27:43 -0300 Message-ID: <20251205202743.10530-4-tomasborquez13@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20251205202743.10530-1-tomasborquez13@gmail.com> References: <20251205202743.10530-1-tomasborquez13@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add devicetree binding documentation for the AD9832 and AD9835 Digital Synthesizer chips. Signed-off-by: Tomas Borquez --- .../bindings/iio/frequency/adi,ad9832.yaml | 65 +++++++++++++++++++ 1 file changed, 65 insertions(+) create mode 100644 Documentation/devicetree/bindings/iio/frequency/adi,ad9= 832.yaml diff --git a/Documentation/devicetree/bindings/iio/frequency/adi,ad9832.yam= l b/Documentation/devicetree/bindings/iio/frequency/adi,ad9832.yaml new file mode 100644 index 0000000000..f14e054ab2 --- /dev/null +++ b/Documentation/devicetree/bindings/iio/frequency/adi,ad9832.yaml @@ -0,0 +1,65 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/iio/frequency/adi,ad9832.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Analog Devices AD9832/AD9835 Direct Digital Synthesizer + +maintainers: + - Michael Hennerich + +properties: + compatible: + enum: + - adi,ad9832 + - adi,ad9835 + + reg: + maxItems: 1 + + spi-max-frequency: + maximum: 20000000 + + clocks: + maxItems: 1 + + clock-names: + const: mclk + + avdd-supply: + description: Analog power supply. + + dvdd-supply: + description: Digital power supply. + +required: + - compatible + - reg + - clocks + - clock-names + - avdd-supply + - dvdd-supply + +allOf: + - $ref: /schemas/spi/spi-peripheral-props.yaml# + +unevaluatedProperties: false + +examples: + - | + spi { + #address-cells =3D <1>; + #size-cells =3D <0>; + + dds@0 { + compatible =3D "adi,ad9832"; + reg =3D <0>; + spi-max-frequency =3D <20000000>; + clocks =3D <&dds_clk>; + clock-names =3D "mclk"; + avdd-supply =3D <&avdd_reg>; + dvdd-supply =3D <&dvdd_reg>; + }; + }; +... --=20 2.43.0