From nobody Tue Dec 16 07:33:17 2025 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.10]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1AB6928851F for ; Fri, 5 Dec 2025 17:45:30 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.10 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764956732; cv=none; b=aPoUKodSHvw30jmMgWXcC4V2tYZ6Jqmq+3hu3Ls6I3Yw1zG0DS3jFR/PB1VEf97hmDBVauM7FT0lZSnDp6BdzhvbPzBZvehX7axezqVEQoxv1oERwzbewiARtKcRe3X1bZ6xRHG09B73S2T8k6bx0X+1/te9v31CfU4w8kKr6Vk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764956732; c=relaxed/simple; bh=bwAM52dGKCSUSKbTWwoR+i/+4Nb3HPYbu+Rsv00YyMM=; h=From:To:Cc:Subject:Date:Message-ID:MIME-Version; b=nszQdNrrj7PUUTj/hoED4cC+LG7tALEeIQ821Mniz7dnGQDkjK40/03zI+CaVJttF/4V4JYXb4jxlRV2e9eW+Za2Hib9uM4yxouDnj/VrO+BWOiEFFM6weNVBsPmQ3pqOfAXVzBXuXinrakeXiY2Oa7GgV8CY2i5d0lz19f3A4M= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=pass smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=Vl/3ezGN; arc=none smtp.client-ip=192.198.163.10 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="Vl/3ezGN" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1764956731; x=1796492731; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=bwAM52dGKCSUSKbTWwoR+i/+4Nb3HPYbu+Rsv00YyMM=; b=Vl/3ezGNd5ZmXUAZ8q6r9TloXnX4mlARmVrT0+aJlftBX8KSHv2Ti64A Z28sVDbmu5iIph1ok4YKOo5v1KIyqkwHj1dVATMljRLNdw9WmRwi+usoz H5LP8xy9tFJvHPTE12t3FPDHA9ZjahUABJO74YftMz73pw0sNghoA6eAg loW/hXYbzQo1FHMThuKzw3RVEI4S4D62fpxoUfP8JLGZFqs7SFVPVXf7J GNh4+Xitw3OyrMmMJrLhLW8HrNd6FTt7QKqM211020jm8bX1vwOjdmlpu LGTDDN7HNhl9A44RDWoxfXiStX67B9tD7xReZwAuwtQCihNIvVGGdGZxI w==; X-CSE-ConnectionGUID: L4BccacYSraah61XkcEarw== X-CSE-MsgGUID: cRb2R16nR7KSwPDvVdmKGQ== X-IronPort-AV: E=McAfee;i="6800,10657,11633"; a="78345574" X-IronPort-AV: E=Sophos;i="6.20,252,1758610800"; d="scan'208";a="78345574" Received: from fmviesa001.fm.intel.com ([10.60.135.141]) by fmvoesa104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 Dec 2025 09:45:30 -0800 X-CSE-ConnectionGUID: yY3alNtOSgizrkn6Gl6LAw== X-CSE-MsgGUID: t6levzb0QceDF/nCUS1pJA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.20,252,1758610800"; d="scan'208";a="226354799" Received: from tassilo.jf.intel.com ([10.54.38.190]) by smtpauth.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 Dec 2025 09:45:30 -0800 From: Andi Kleen To: linux-kernel@vger.kernel.org Cc: x86@kernel.org, andrew.cooper3@citrix.com, Andi Kleen , ggherdovich@suse.cz, Peter Zijlstra , rafael.j.wysocki@intel.com Subject: [PATCH v2] x86/aperfmperf: Don't disable scheduler APERF/MPERF on bad samples Date: Fri, 5 Dec 2025 09:45:17 -0800 Message-ID: <20251205174517.1861818-1-ak@linux.intel.com> X-Mailer: git-send-email 2.51.1 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The APERF and MPERF MSRs get read together and the ratio between the two is used to scale the scheduler capacity with frequency. Since e2b0d619b400 when there is ever an over/underflow of the APERF/MPERF computation the sampling gets completely disabled, under the assumption that there is a problem with the hardware. However this can happen without any malfunction when there is a long enough interruption between the two MSR reads, for example due to an unlucky NMI or SMI or other system event causing delays. We saw it when a delay resulted in Acnt_Delta << Mcnt_Delta (about ~4k for acnt_delta and 2M for MCnt_Delta) In this case the ratio computation underflows, which is detected, but then APERF/MPERF usage gets incorrectly disabled forever. Remove the code to completely disable APERF/MPERF on a bad sample. Instead when any over/underflow happens return the fallback full capacity. In theory could have a threshold to disable, but since delays could happen randomly it's unclear what a good threshold would be. If the hardware is truly broken this will result in using a few more cycles to read the bogus samples, but they will be all still rejected. Cc: ggherdovich@suse.cz Cc: Peter Zijlstra Cc: rafael.j.wysocki@intel.com Fixes: e2b0d619b400 ("x86, sched: check for counters overflow ...") Signed-off-by: Andi Kleen --- v2: Move freq_scale initialization to cover all cases (thanks 0day bot!) --- arch/x86/kernel/cpu/aperfmperf.c | 35 +++++++++----------------------- 1 file changed, 10 insertions(+), 25 deletions(-) diff --git a/arch/x86/kernel/cpu/aperfmperf.c b/arch/x86/kernel/cpu/aperfmp= erf.c index a315b0627dfb..3c89d3c43772 100644 --- a/arch/x86/kernel/cpu/aperfmperf.c +++ b/arch/x86/kernel/cpu/aperfmperf.c @@ -330,23 +330,6 @@ static void __init bp_init_freq_invariance(void) } } =20 -static void disable_freq_invariance_workfn(struct work_struct *work) -{ - int cpu; - - static_branch_disable(&arch_scale_freq_key); - - /* - * Set arch_freq_scale to a default value on all cpus - * This negates the effect of scaling - */ - for_each_possible_cpu(cpu) - per_cpu(arch_freq_scale, cpu) =3D SCHED_CAPACITY_SCALE; -} - -static DECLARE_WORK(disable_freq_invariance_work, - disable_freq_invariance_workfn); - DEFINE_PER_CPU(unsigned long, arch_freq_scale) =3D SCHED_CAPACITY_SCALE; EXPORT_PER_CPU_SYMBOL_GPL(arch_freq_scale); =20 @@ -437,8 +420,14 @@ static void scale_freq_tick(u64 acnt, u64 mcnt) if (!arch_scale_freq_invariant()) return; =20 + /* + * On any over/underflow just ignore the sample. It could + * be due to an unlucky NMI or similar between the + * APERF and MPERF reads. + */ + freq_scale =3D SCHED_CAPACITY_SCALE; if (check_shl_overflow(acnt, 2*SCHED_CAPACITY_SHIFT, &acnt)) - goto error; + goto out; =20 if (static_branch_unlikely(&arch_hybrid_cap_scale_key)) freq_ratio =3D READ_ONCE(this_cpu_ptr(arch_cpu_scale)->freq_ratio); @@ -446,21 +435,17 @@ static void scale_freq_tick(u64 acnt, u64 mcnt) freq_ratio =3D arch_max_freq_ratio; =20 if (check_mul_overflow(mcnt, freq_ratio, &mcnt) || !mcnt) - goto error; + goto out; =20 freq_scale =3D div64_u64(acnt, mcnt); if (!freq_scale) - goto error; + goto out; =20 if (freq_scale > SCHED_CAPACITY_SCALE) freq_scale =3D SCHED_CAPACITY_SCALE; =20 +out: this_cpu_write(arch_freq_scale, freq_scale); - return; - -error: - pr_warn("Scheduler frequency invariance went wobbly, disabling!\n"); - schedule_work(&disable_freq_invariance_work); } #else static inline void bp_init_freq_invariance(void) { } --=20 2.51.1