From nobody Fri Dec 19 15:04:49 2025 Received: from relmlie6.idc.renesas.com (relmlor2.renesas.com [210.160.252.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 595422DAFB5; Fri, 5 Dec 2025 15:03:32 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.160.252.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764947018; cv=none; b=fkD/BMjScoMFYA+6pxXAun3x6Ip1ZU37MwLHYJ5B3XwyH8oY8bwD9Hv1uUBpggti7bQPvo9JkMwCno5laxYy/h9Y8qV+amABTK0GRFDuKh6L7pM71QzhrxyHZvXurJI3OgDPirS6pUrXw7d+zokR4MnMbDipb5bxE9IzCc2D9sA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764947018; c=relaxed/simple; bh=EBpnXAVaSaqytYfPPWXECpG67N1Y1OCQkWaK/o3gftE=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=CjkF1nmiBiW5WKJvepPV67lRR7ZiqgRaA5a4O0qBcGhGpigbYgr/7Hod8riJWxtIc125qejsJhrJeSCqEZYDVdZ3R1dRYoJ/+UqcHyVbqhASYSH8LDZlRSXPBf4BW41kMc+TAzaM9qXo2wAns5macgzsc+6kEq533vYzZCCyLA8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=renesas.com; spf=pass smtp.mailfrom=renesas.com; arc=none smtp.client-ip=210.160.252.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=renesas.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=renesas.com X-CSE-ConnectionGUID: YhkQBUooQS2L7oAlJpTxoQ== X-CSE-MsgGUID: 8ubxXUDVS7+q1qf8g0xx9Q== Received: from unknown (HELO relmlir6.idc.renesas.com) ([10.200.68.152]) by relmlie6.idc.renesas.com with ESMTP; 06 Dec 2025 00:03:30 +0900 Received: from demon-pc.localdomain (unknown [10.226.93.202]) by relmlir6.idc.renesas.com (Postfix) with ESMTP id 5265F427BFED; Sat, 6 Dec 2025 00:03:27 +0900 (JST) From: Cosmin Tanislav To: Geert Uytterhoeven , Linus Walleij , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Magnus Damm , Lad Prabhakar Cc: linux-renesas-soc@vger.kernel.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Cosmin Tanislav Subject: [PATCH v2 1/8] pinctrl: renesas: rzt2h: move GPIO enable/disable into separate function Date: Fri, 5 Dec 2025 17:02:27 +0200 Message-ID: <20251205150234.2958140-2-cosmin-gabriel.tanislav.xa@renesas.com> X-Mailer: git-send-email 2.52.0 In-Reply-To: <20251205150234.2958140-1-cosmin-gabriel.tanislav.xa@renesas.com> References: <20251205150234.2958140-1-cosmin-gabriel.tanislav.xa@renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" GPIO is enabled or disabled in multiple places, simplify code by moving this logic into a separate function. Signed-off-by: Cosmin Tanislav --- V2: * no changes drivers/pinctrl/renesas/pinctrl-rzt2h.c | 24 ++++++++++++++++-------- 1 file changed, 16 insertions(+), 8 deletions(-) diff --git a/drivers/pinctrl/renesas/pinctrl-rzt2h.c b/drivers/pinctrl/rene= sas/pinctrl-rzt2h.c index 4826ff91cd90..c8ca5e13bba7 100644 --- a/drivers/pinctrl/renesas/pinctrl-rzt2h.c +++ b/drivers/pinctrl/renesas/pinctrl-rzt2h.c @@ -119,6 +119,19 @@ static int rzt2h_validate_pin(struct rzt2h_pinctrl *pc= trl, unsigned int offset) return (pincfg & BIT(pin)) ? 0 : -EINVAL; } =20 +static void rzt2h_pinctrl_set_gpio_en(struct rzt2h_pinctrl *pctrl, + u8 port, u8 pin, bool en) +{ + u8 reg =3D rzt2h_pinctrl_readb(pctrl, port, PMC(port)); + + if (en) + reg &=3D ~BIT(pin); + else + reg |=3D BIT(pin); + + rzt2h_pinctrl_writeb(pctrl, port, reg, PMC(port)); +} + static void rzt2h_pinctrl_set_pfc_mode(struct rzt2h_pinctrl *pctrl, u8 port, u8 pin, u8 func) { @@ -133,8 +146,7 @@ static void rzt2h_pinctrl_set_pfc_mode(struct rzt2h_pin= ctrl *pctrl, rzt2h_pinctrl_writew(pctrl, port, reg16, PM(port)); =20 /* Temporarily switch to GPIO mode with PMC register */ - reg16 =3D rzt2h_pinctrl_readb(pctrl, port, PMC(port)); - rzt2h_pinctrl_writeb(pctrl, port, reg16 & ~BIT(pin), PMC(port)); + rzt2h_pinctrl_set_gpio_en(pctrl, port, pin, true); =20 /* Select Pin function mode with PFC register */ reg64 =3D rzt2h_pinctrl_readq(pctrl, port, PFC(port)); @@ -142,8 +154,7 @@ static void rzt2h_pinctrl_set_pfc_mode(struct rzt2h_pin= ctrl *pctrl, rzt2h_pinctrl_writeq(pctrl, port, reg64 | ((u64)func << (pin * 8)), PFC(p= ort)); =20 /* Switch to Peripheral pin function with PMC register */ - reg16 =3D rzt2h_pinctrl_readb(pctrl, port, PMC(port)); - rzt2h_pinctrl_writeb(pctrl, port, reg16 | BIT(pin), PMC(port)); + rzt2h_pinctrl_set_gpio_en(pctrl, port, pin, false); } =20 static int rzt2h_pinctrl_set_mux(struct pinctrl_dev *pctldev, @@ -447,7 +458,6 @@ static int rzt2h_gpio_request(struct gpio_chip *chip, u= nsigned int offset) u8 port =3D RZT2H_PIN_ID_TO_PORT(offset); u8 bit =3D RZT2H_PIN_ID_TO_PIN(offset); int ret; - u8 reg; =20 ret =3D rzt2h_validate_pin(pctrl, offset); if (ret) @@ -460,9 +470,7 @@ static int rzt2h_gpio_request(struct gpio_chip *chip, u= nsigned int offset) guard(spinlock_irqsave)(&pctrl->lock); =20 /* Select GPIO mode in PMC Register */ - reg =3D rzt2h_pinctrl_readb(pctrl, port, PMC(port)); - reg &=3D ~BIT(bit); - rzt2h_pinctrl_writeb(pctrl, port, reg, PMC(port)); + rzt2h_pinctrl_set_gpio_en(pctrl, port, bit, true); =20 return 0; } --=20 2.52.0 From nobody Fri Dec 19 15:04:49 2025 Received: from relmlie6.idc.renesas.com (relmlor2.renesas.com [210.160.252.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 4F2A533D6F5; Fri, 5 Dec 2025 15:03:37 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.160.252.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764947022; cv=none; b=mblI8z0E4xpJFatML8p1hCOhAEVrm2I1xxo3BA4jN3JFI9KhyUaog+M2wxeAYu5ThHFuKL5Vmx/mAMgrNe1qTYwgEHdeVoNU0GmoDkL+lZ2zrlwxfMK8Biw7yO+DgaYFkp6aqi+7KlJT/KUbVy3SSLke5vlI8/Uk/cTT0DijKBU= ARC-Message-Signature: i=1; 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Sat, 6 Dec 2025 00:03:31 +0900 (JST) From: Cosmin Tanislav To: Geert Uytterhoeven , Linus Walleij , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Magnus Damm , Lad Prabhakar Cc: linux-renesas-soc@vger.kernel.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Cosmin Tanislav Subject: [PATCH v2 2/8] pinctrl: renesas: rzt2h: allow .get_direction() for IRQ function GPIOs Date: Fri, 5 Dec 2025 17:02:28 +0200 Message-ID: <20251205150234.2958140-3-cosmin-gabriel.tanislav.xa@renesas.com> X-Mailer: git-send-email 2.52.0 In-Reply-To: <20251205150234.2958140-1-cosmin-gabriel.tanislav.xa@renesas.com> References: <20251205150234.2958140-1-cosmin-gabriel.tanislav.xa@renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Setting up an IRQ would normally be done in the .activate() and .deactivate() ops of the IRQ domain, but for hierarchical IRQ domains the .activate() and .deactivate() ops are overridden in the gpiochip_hierarchy_setup_domain_ops() function. As such, activating and deactivating need to be done in the .translate() and .free() ops of the IRQ domain. For RZ/T2H and RZ/N2H, interrupts go through the pin controller, into the ICU, which level-translates them and forwards them to the GIC. To use a GPIO as an interrupt it needs to be put into peripheral function mode 0, which will connect it to the IRQ lines of the ICU. The IRQ chip .child_to_parent_hwirq() callback is called as part of the IRQ fwspec parsing logic (as part of irq_create_of_mapping()) which happens before the IRQ is requested (as part of gpiochip_lock_as_irq()). gpiochip_lock_as_irq() calls gpiod_get_direction() if the .get_direction() callback is provided to ensure that the GPIO line is set up as input. In our case, IRQ function is separate from GPIO, and both cannot be true at the same time. Return GPIO_LINE_DIRECTION_IN even if pin is in IRQ function to allow this setup to work. Hold the spinlock to ensure atomicity between reading the PMC register (which determines whether the pin is in GPIO mode or not) and reading the function of the pin when it is not in GPIO mode. Signed-off-by: Cosmin Tanislav --- V2: * no changes drivers/pinctrl/renesas/pinctrl-rzt2h.c | 21 ++++++++++++++++++++- 1 file changed, 20 insertions(+), 1 deletion(-) diff --git a/drivers/pinctrl/renesas/pinctrl-rzt2h.c b/drivers/pinctrl/rene= sas/pinctrl-rzt2h.c index c8ca5e13bba7..722551723e06 100644 --- a/drivers/pinctrl/renesas/pinctrl-rzt2h.c +++ b/drivers/pinctrl/renesas/pinctrl-rzt2h.c @@ -51,6 +51,7 @@ =20 #define PFC_MASK GENMASK_ULL(5, 0) #define PFC_PIN_MASK(pin) (PFC_MASK << ((pin) * 8)) +#define PFC_FUNC_INTERRUPT 0 =20 /* * Use 16 lower bits [15:0] for pin identifier @@ -494,6 +495,7 @@ static int rzt2h_gpio_get_direction(struct gpio_chip *c= hip, unsigned int offset) struct rzt2h_pinctrl *pctrl =3D gpiochip_get_data(chip); u8 port =3D RZT2H_PIN_ID_TO_PORT(offset); u8 bit =3D RZT2H_PIN_ID_TO_PIN(offset); + u64 reg64; u16 reg; int ret; =20 @@ -501,8 +503,25 @@ static int rzt2h_gpio_get_direction(struct gpio_chip *= chip, unsigned int offset) if (ret) return ret; =20 - if (rzt2h_pinctrl_readb(pctrl, port, PMC(port)) & BIT(bit)) + guard(spinlock_irqsave)(&pctrl->lock); + + if (rzt2h_pinctrl_readb(pctrl, port, PMC(port)) & BIT(bit)) { + /* + * When a GPIO is being requested as an IRQ, the pinctrl + * framework expects to be able to read the GPIO's direction. + * IRQ function is separate from GPIO, and enabling it takes the + * pin out of GPIO mode. + * At this point, .child_to_parent_hwirq() has already been + * called to enable the IRQ function. + * Default to input direction for IRQ function. + */ + reg64 =3D rzt2h_pinctrl_readq(pctrl, port, PFC(port)); + reg64 =3D (reg64 >> (bit * 8)) & PFC_MASK; + if (reg64 =3D=3D PFC_FUNC_INTERRUPT) + return GPIO_LINE_DIRECTION_IN; + return -EINVAL; + } =20 reg =3D rzt2h_pinctrl_readw(pctrl, port, PM(port)); reg =3D (reg >> (bit * 2)) & PM_MASK; --=20 2.52.0 From nobody Fri Dec 19 15:04:49 2025 Received: from relmlie5.idc.renesas.com (relmlor1.renesas.com [210.160.252.171]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 4C7C133E378; Fri, 5 Dec 2025 15:03:42 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.160.252.171 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764947027; cv=none; b=Y8FvN5VxSXBT0eG4PbQD4AaoXCO9lGy4QSvCQjVT/TsVk+b731YE6WXkPdkTJYMl0bEb+jCfUJsiSteT+BCHUVB+fRNHz4Xl+2jYuohTWTwZou/7OE7JXqQRoyCdKxRds7mRaZWuxWgPla9gYLtVN/R6ve7PpD/oMX8qvFxUdxU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764947027; c=relaxed/simple; bh=h8k/DS8Gux03E64mIoumDEnoGPFTiylMCzLKCaNMtZ4=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=CYwiGFp9hWHew5GYx4yMAHfMtsgNegkCzqwtJyM5KvrdLWeyLFy5ni5nRb4s59to6WOYfUN8PL0p/rxgZkfPGSDj6iysX4r0YKwvUWbjHlnUUlmRQA8S6iU3irpDFA7wuw3P5bULQMj/ZMlp+i46Bc2jVhiKLkLHyb8PPHQoEMQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=renesas.com; spf=pass smtp.mailfrom=renesas.com; arc=none smtp.client-ip=210.160.252.171 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=renesas.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=renesas.com X-CSE-ConnectionGUID: yAL7x8YES2y67zWN+sgRkA== X-CSE-MsgGUID: dCgfaKj2Qn+3dQPlkRK2Fw== Received: from unknown (HELO relmlir6.idc.renesas.com) ([10.200.68.152]) by relmlie5.idc.renesas.com with ESMTP; 06 Dec 2025 00:03:40 +0900 Received: from demon-pc.localdomain (unknown [10.226.93.202]) by relmlir6.idc.renesas.com (Postfix) with ESMTP id EA351427BFF0; Sat, 6 Dec 2025 00:03:36 +0900 (JST) From: Cosmin Tanislav To: Geert Uytterhoeven , Linus Walleij , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Magnus Damm , Lad Prabhakar Cc: linux-renesas-soc@vger.kernel.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Cosmin Tanislav Subject: [PATCH v2 3/8] dt-bindings: pinctrl: renesas,r9a09g077-pinctrl: Document GPIO IRQ Date: Fri, 5 Dec 2025 17:02:29 +0200 Message-ID: <20251205150234.2958140-4-cosmin-gabriel.tanislav.xa@renesas.com> X-Mailer: git-send-email 2.52.0 In-Reply-To: <20251205150234.2958140-1-cosmin-gabriel.tanislav.xa@renesas.com> References: <20251205150234.2958140-1-cosmin-gabriel.tanislav.xa@renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The Renesas RZ/T2H (R9A09G077) and Renesas RZ/N2H (R9A09G087) SoCs have IRQ-capable pins handled by the ICU, which forwards them to the GIC. The ICU supports 16 IRQ lines, the pins map to these lines arbitrarily, and the mapping is not configurable. Document the required properties to handle GPIO IRQ. Signed-off-by: Cosmin Tanislav Reviewed-by: Linus Walleij Reviewed-by: Rob Herring (Arm) --- V2: * drop interrupt-controller and #interrupt-cells from required to keep compatibility .../bindings/pinctrl/renesas,r9a09g077-pinctrl.yaml | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/Documentation/devicetree/bindings/pinctrl/renesas,r9a09g077-pi= nctrl.yaml b/Documentation/devicetree/bindings/pinctrl/renesas,r9a09g077-pi= nctrl.yaml index 36d665971484..f049013a4e0c 100644 --- a/Documentation/devicetree/bindings/pinctrl/renesas,r9a09g077-pinctrl.y= aml +++ b/Documentation/devicetree/bindings/pinctrl/renesas,r9a09g077-pinctrl.y= aml @@ -49,6 +49,17 @@ properties: gpio-ranges: maxItems: 1 =20 + interrupt-controller: true + + '#interrupt-cells': + const: 2 + description: + The first cell contains the global GPIO port index, constructed usin= g the + RZT2H_GPIO() helper macro from + and the second cell is used to specify the flag. + E.g. "interrupts =3D ;" if P= 08_6 is + being used as an interrupt. + clocks: maxItems: 1 =20 @@ -139,6 +150,8 @@ examples: gpio-controller; #gpio-cells =3D <2>; gpio-ranges =3D <&pinctrl 0 0 288>; + interrupt-controller; + #interrupt-cells =3D <2>; power-domains =3D <&cpg>; =20 serial0-pins { --=20 2.52.0 From nobody Fri Dec 19 15:04:49 2025 Received: from relmlie5.idc.renesas.com (relmlor1.renesas.com [210.160.252.171]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 5129133F363; Fri, 5 Dec 2025 15:03:48 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.160.252.171 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764947034; cv=none; b=hdET+FQ89LqsBbPPyfs3HhEzWvIeFkTLYC88FapExi8kFkD7fSNUb2iuK0R7V3j9FhIUp6rPnXWOYz8GwbjuX7FhbE/whpw0L5lk6nH1gyh51M6kOHoBQIN1g0HvSRira/VolIxoT6JDdnPMoxG4uUc8tmZUvD3owQ1643VQyBg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764947034; c=relaxed/simple; bh=G2xPb17IIpif+cV/DxhvfGyxgmp1R2KiBn8ediNb/pc=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=FJHLk4VkkbZ2PtenygGH2aYgwdJNocfJ26UryDglBGF3G0s7jVFN5P3StnFzmbZgNYfLB3A2D4y59KL/5qcL9dRBy9O6uzVDruySW+1dK7gAerFzARIClUh3QO/yCaQOomAW/CcH8UbWhOqUiesF2kGNXLwFOX6fKBjqSjyiPGo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=renesas.com; spf=pass smtp.mailfrom=renesas.com; arc=none smtp.client-ip=210.160.252.171 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=renesas.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=renesas.com X-CSE-ConnectionGUID: thRXtSGhRzqUgHepbrMUnw== X-CSE-MsgGUID: P+rXtFjZQoi6JoUtCWVDuA== Received: from unknown (HELO relmlir6.idc.renesas.com) ([10.200.68.152]) by relmlie5.idc.renesas.com with ESMTP; 06 Dec 2025 00:03:48 +0900 Received: from demon-pc.localdomain (unknown [10.226.93.202]) by relmlir6.idc.renesas.com (Postfix) with ESMTP id 78714427BFF0; Sat, 6 Dec 2025 00:03:44 +0900 (JST) From: Cosmin Tanislav To: Geert Uytterhoeven , Linus Walleij , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Magnus Damm , Lad Prabhakar Cc: linux-renesas-soc@vger.kernel.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Cosmin Tanislav Subject: [PATCH v2 4/8] pinctrl: renesas: rzt2h: add GPIO IRQ chip to handle interrupts Date: Fri, 5 Dec 2025 17:02:30 +0200 Message-ID: <20251205150234.2958140-5-cosmin-gabriel.tanislav.xa@renesas.com> X-Mailer: git-send-email 2.52.0 In-Reply-To: <20251205150234.2958140-1-cosmin-gabriel.tanislav.xa@renesas.com> References: <20251205150234.2958140-1-cosmin-gabriel.tanislav.xa@renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The Renesas RZ/T2H (R9A09G077) and Renesas RZ/N2H (R9A09G087) SoCs have IRQ-capable pins handled by the ICU, which forwards them to the GIC. The ICU supports 16 IRQ lines, the pins map to these lines arbitrarily, and the mapping is not configurable. Add a GPIO IRQ chip to the pin controller that can be used to configure these pins as IRQ lines. The pin controller places the requested pins into IRQ function, disabling GPIO mode. A hierarchical IRQ domain is used to forward other functionality to the parent IRQ domain, the ICU. The ICU does level translation and then forwards other functionality to the GIC. Wakeup capability is implemented by placing the entire pin controller on the wakeup path if any pins are requested to be wakeup-capable. Signed-off-by: Cosmin Tanislav Reviewed-by: Linus Walleij --- V2: * select GPIOLIB_IRQCHIP * select IRQ_DOMAIN_HIERARCHY * add comment to clarify wakeup_path atomic usage * add more details to the commit message, including usage of the hierarchical IRQ domain and wakeup capability implementation drivers/pinctrl/renesas/Kconfig | 2 + drivers/pinctrl/renesas/pinctrl-rzt2h.c | 200 ++++++++++++++++++++++++ 2 files changed, 202 insertions(+) diff --git a/drivers/pinctrl/renesas/Kconfig b/drivers/pinctrl/renesas/Kcon= fig index 8cbd79a13414..d979e25e5088 100644 --- a/drivers/pinctrl/renesas/Kconfig +++ b/drivers/pinctrl/renesas/Kconfig @@ -308,9 +308,11 @@ config PINCTRL_RZT2H bool "pin control support for RZ/N2H and RZ/T2H" if COMPILE_TEST depends on 64BIT && OF select GPIOLIB + select GPIOLIB_IRQCHIP select GENERIC_PINCTRL_GROUPS select GENERIC_PINMUX_FUNCTIONS select GENERIC_PINCONF + select IRQ_DOMAIN_HIERARCHY help This selects GPIO and pinctrl driver for Renesas RZ/T2H platforms. diff --git a/drivers/pinctrl/renesas/pinctrl-rzt2h.c b/drivers/pinctrl/rene= sas/pinctrl-rzt2h.c index 722551723e06..c276cbd3f87a 100644 --- a/drivers/pinctrl/renesas/pinctrl-rzt2h.c +++ b/drivers/pinctrl/renesas/pinctrl-rzt2h.c @@ -18,6 +18,7 @@ #include #include #include +#include #include #include #include @@ -65,6 +66,9 @@ =20 #define RZT2H_MAX_SAFETY_PORTS 12 =20 +#define RZT2H_INTERRUPTS_START 16 +#define RZT2H_INTERRUPTS_NUM 17 + struct rzt2h_pinctrl_data { unsigned int n_port_pins; const u8 *port_pin_configs; @@ -80,9 +84,11 @@ struct rzt2h_pinctrl { struct device *dev; struct gpio_chip gpio_chip; struct pinctrl_gpio_range gpio_range; + DECLARE_BITMAP(used_irqs, RZT2H_INTERRUPTS_NUM); spinlock_t lock; /* lock read/write registers */ struct mutex mutex; /* serialize adding groups and functions */ bool safety_port_enabled; + atomic_t wakeup_path; }; =20 #define RZT2H_GET_BASE(pctrl, port) \ @@ -644,14 +650,194 @@ static const char * const rzt2h_gpio_names[] =3D { "P35_0", "P35_1", "P35_2", "P35_3", "P35_4", "P35_5", "P35_6", "P35_7", }; =20 +/* + * Interrupts 0-15 are for INTCPUn, which are not exposed externally. + * Interrupts 16-31 are for IRQn. SEI is 32. + * This table matches the information found in User Manual's Table 17.2, + * List of multiplexed pin configurations (5 of 51). + * RZ/N2H has the same GPIO to IRQ mapping, except for the pins which + * are not present. + */ +static const u8 rzt2h_gpio_irq_map[] =3D { + 32, 16, 17, 18, 19, 0, 20, 21, + 22, 0, 0, 0, 0, 0, 0, 0, + 23, 24, 25, 26, 27, 0, 0, 0, + 0, 0, 28, 29, 30, 31, 0, 0, + 0, 0, 0, 0, 0, 32, 16, 17, + 18, 19, 20, 21, 22, 0, 0, 0, + 0, 0, 24, 25, 26, 27, 0, 28, + 29, 30, 31, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 24, 32, 16, + 0, 0, 0, 0, 0, 0, 0, 0, + 20, 23, 17, 18, 19, 0, 16, 25, + 29, 20, 21, 22, 23, 0, 0, 0, + 0, 0, 0, 0, 17, 0, 0, 18, + 0, 0, 19, 0, 0, 20, 0, 30, + 21, 0, 0, 22, 0, 0, 24, 25, + 0, 0, 0, 0, 0, 16, 17, 0, + 18, 0, 0, 26, 27, 0, 0, 0, + 28, 29, 30, 31, 0, 0, 0, 0, + 23, 31, 32, 16, 17, 18, 19, 20, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 27, 0, 0, 21, 22, 23, 24, 25, + 26, 0, 0, 0, 0, 0, 0, 0, + 27, 28, 29, 30, 31, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 28, 32, 16, + 17, 18, 19, 0, 0, 0, 0, 20, + 21, 22, 23, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 24, 25, 0, 0, + 0, 0, 26, 27, 0, 0, 0, 30, + 0, 29, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 28, 29, 30, 31, 0, + 0, 0, 0, 0, 0, 0, 0, 30, + 0, 0, 0, 0, 0, 0, 0, 0, +}; + +static void rzt2h_gpio_irq_disable(struct irq_data *d) +{ + struct gpio_chip *gc =3D irq_data_get_irq_chip_data(d); + unsigned int hwirq =3D irqd_to_hwirq(d); + + irq_chip_disable_parent(d); + gpiochip_disable_irq(gc, hwirq); +} + +static void rzt2h_gpio_irq_enable(struct irq_data *d) +{ + struct gpio_chip *gc =3D irq_data_get_irq_chip_data(d); + unsigned int hwirq =3D irqd_to_hwirq(d); + + gpiochip_enable_irq(gc, hwirq); + irq_chip_enable_parent(d); +} + +static int rzt2h_gpio_irq_set_wake(struct irq_data *d, unsigned int on) +{ + struct gpio_chip *gc =3D irq_data_get_irq_chip_data(d); + struct rzt2h_pinctrl *pctrl =3D container_of(gc, struct rzt2h_pinctrl, gp= io_chip); + int ret; + + ret =3D irq_chip_set_wake_parent(d, on); + if (ret) + return ret; + + /* + * If any of the IRQs are in use, put the entire pin controller on the + * device wakeup path. + */ + if (on) + atomic_inc(&pctrl->wakeup_path); + else + atomic_dec(&pctrl->wakeup_path); + + return 0; +} + +static const struct irq_chip rzt2h_gpio_irqchip =3D { + .name =3D "rzt2h-gpio", + .irq_disable =3D rzt2h_gpio_irq_disable, + .irq_enable =3D rzt2h_gpio_irq_enable, + .irq_mask =3D irq_chip_mask_parent, + .irq_unmask =3D irq_chip_unmask_parent, + .irq_set_type =3D irq_chip_set_type_parent, + .irq_set_wake =3D rzt2h_gpio_irq_set_wake, + .irq_eoi =3D irq_chip_eoi_parent, + .irq_set_affinity =3D irq_chip_set_affinity_parent, + .flags =3D IRQCHIP_IMMUTABLE, + GPIOCHIP_IRQ_RESOURCE_HELPERS, +}; + +static int rzt2h_pinctrl_suspend_noirq(struct device *dev) +{ + struct rzt2h_pinctrl *pctrl =3D dev_get_drvdata(dev); + + if (atomic_read(&pctrl->wakeup_path)) + device_set_wakeup_path(dev); + + return 0; +} + +static int rzt2h_gpio_child_to_parent_hwirq(struct gpio_chip *gc, + unsigned int child, + unsigned int child_type, + unsigned int *parent, + unsigned int *parent_type) +{ + struct rzt2h_pinctrl *pctrl =3D gpiochip_get_data(gc); + u8 port =3D RZT2H_PIN_ID_TO_PORT(child); + u8 pin =3D RZT2H_PIN_ID_TO_PIN(child); + u8 parent_irq; + + parent_irq =3D rzt2h_gpio_irq_map[child]; + if (parent_irq < RZT2H_INTERRUPTS_START) + return -EINVAL; + + if (test_and_set_bit(parent_irq - RZT2H_INTERRUPTS_START, + pctrl->used_irqs)) + return -EBUSY; + + rzt2h_pinctrl_set_pfc_mode(pctrl, port, pin, PFC_FUNC_INTERRUPT); + + *parent =3D parent_irq; + *parent_type =3D child_type; + + return 0; +} + +static void rzt2h_gpio_irq_domain_free(struct irq_domain *domain, unsigned= int virq, + unsigned int nr_irqs) +{ + struct irq_data *d =3D irq_domain_get_irq_data(domain, virq); + struct gpio_chip *gc =3D irq_data_get_irq_chip_data(d); + struct rzt2h_pinctrl *pctrl =3D container_of(gc, struct rzt2h_pinctrl, gp= io_chip); + irq_hw_number_t hwirq =3D irqd_to_hwirq(d); + u8 port =3D RZT2H_PIN_ID_TO_PORT(hwirq); + u8 pin =3D RZT2H_PIN_ID_TO_PIN(hwirq); + + if (test_and_clear_bit(hwirq - RZT2H_INTERRUPTS_START, pctrl->used_irqs)) + rzt2h_pinctrl_set_gpio_en(pctrl, port, pin, false); + + irq_domain_free_irqs_common(domain, virq, nr_irqs); +} + +static void rzt2h_gpio_init_irq_valid_mask(struct gpio_chip *gc, + unsigned long *valid_mask, + unsigned int ngpios) +{ + struct rzt2h_pinctrl *pctrl =3D gpiochip_get_data(gc); + unsigned int offset; + + for (offset =3D 0; offset < ngpios; offset++) { + if (!rzt2h_gpio_irq_map[offset] || rzt2h_validate_pin(pctrl, offset)) + clear_bit(offset, valid_mask); + } +} + static int rzt2h_gpio_register(struct rzt2h_pinctrl *pctrl) { struct pinctrl_gpio_range *range =3D &pctrl->gpio_range; struct gpio_chip *chip =3D &pctrl->gpio_chip; + struct device_node *np =3D pctrl->dev->of_node; + struct irq_domain *parent_domain; struct device *dev =3D pctrl->dev; struct of_phandle_args of_args; + struct device_node *parent_np; + struct gpio_irq_chip *girq; int ret; =20 + parent_np =3D of_irq_find_parent(np); + if (!parent_np) + return -ENXIO; + + parent_domain =3D irq_find_host(parent_np); + of_node_put(parent_np); + if (!parent_domain) + return -EPROBE_DEFER; + ret =3D of_parse_phandle_with_fixed_args(dev->of_node, "gpio-ranges", 3, = 0, &of_args); if (ret) return dev_err_probe(dev, ret, "Unable to parse gpio-ranges\n"); @@ -675,6 +861,15 @@ static int rzt2h_gpio_register(struct rzt2h_pinctrl *p= ctrl) chip->set =3D rzt2h_gpio_set; chip->label =3D dev_name(dev); =20 + girq =3D &chip->irq; + gpio_irq_chip_set_chip(girq, &rzt2h_gpio_irqchip); + girq->fwnode =3D dev_fwnode(pctrl->dev); + girq->parent_domain =3D parent_domain; + girq->child_to_parent_hwirq =3D rzt2h_gpio_child_to_parent_hwirq; + girq->populate_parent_alloc_arg =3D gpiochip_populate_parent_fwspec_twoce= ll; + girq->child_irq_domain_ops.free =3D rzt2h_gpio_irq_domain_free; + girq->init_valid_mask =3D rzt2h_gpio_init_irq_valid_mask; + range->id =3D 0; range->pin_base =3D 0; range->base =3D 0; @@ -819,10 +1014,15 @@ static const struct of_device_id rzt2h_pinctrl_of_ta= ble[] =3D { { /* sentinel */ } }; =20 +static const struct dev_pm_ops rzt2h_pinctrl_pm_ops =3D { + NOIRQ_SYSTEM_SLEEP_PM_OPS(rzt2h_pinctrl_suspend_noirq, NULL) +}; + static struct platform_driver rzt2h_pinctrl_driver =3D { .driver =3D { .name =3D DRV_NAME, .of_match_table =3D of_match_ptr(rzt2h_pinctrl_of_table), + .pm =3D pm_sleep_ptr(&rzt2h_pinctrl_pm_ops), .suppress_bind_attrs =3D true, }, .probe =3D rzt2h_pinctrl_probe, --=20 2.52.0 From nobody Fri Dec 19 15:04:49 2025 Received: from relmlie6.idc.renesas.com (relmlor2.renesas.com [210.160.252.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 997922FD7AC; Fri, 5 Dec 2025 15:03:54 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.160.252.172 ARC-Seal: i=1; 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spf=pass smtp.mailfrom=renesas.com X-CSE-ConnectionGUID: QtplvdtVQNmSTFU8yIYYLw== X-CSE-MsgGUID: yCd5z+ntQSuAOJ3xuLVg6A== Received: from unknown (HELO relmlir6.idc.renesas.com) ([10.200.68.152]) by relmlie6.idc.renesas.com with ESMTP; 06 Dec 2025 00:03:53 +0900 Received: from demon-pc.localdomain (unknown [10.226.93.202]) by relmlir6.idc.renesas.com (Postfix) with ESMTP id 64308427BFF0; Sat, 6 Dec 2025 00:03:49 +0900 (JST) From: Cosmin Tanislav To: Geert Uytterhoeven , Linus Walleij , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Magnus Damm , Lad Prabhakar Cc: linux-renesas-soc@vger.kernel.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Cosmin Tanislav Subject: [PATCH v2 5/8] arm64: dts: renesas: r9a09g077: add GPIO IRQ support Date: Fri, 5 Dec 2025 17:02:31 +0200 Message-ID: <20251205150234.2958140-6-cosmin-gabriel.tanislav.xa@renesas.com> X-Mailer: git-send-email 2.52.0 In-Reply-To: <20251205150234.2958140-1-cosmin-gabriel.tanislav.xa@renesas.com> References: <20251205150234.2958140-1-cosmin-gabriel.tanislav.xa@renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The Renesas RZ/T2H (R9A09G077) SoC includes pins which can be routed via the ICU to generate interrupts. Add support for using the pin controller as an interrupt chip. Signed-off-by: Cosmin Tanislav --- V2: * no changes arch/arm64/boot/dts/renesas/r9a09g077.dtsi | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a09g077.dtsi b/arch/arm64/boot/d= ts/renesas/r9a09g077.dtsi index 0af41287e6a8..6812af127684 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g077.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a09g077.dtsi @@ -945,6 +945,9 @@ pinctrl: pinctrl@802c0000 { gpio-controller; #gpio-cells =3D <2>; gpio-ranges =3D <&pinctrl 0 0 288>; + #interrupt-cells =3D <2>; + interrupt-controller; + interrupt-parent =3D <&icu>; power-domains =3D <&cpg>; }; =20 --=20 2.52.0 From nobody Fri Dec 19 15:04:49 2025 Received: from relmlie6.idc.renesas.com (relmlor2.renesas.com [210.160.252.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 3FE7B340262; Fri, 5 Dec 2025 15:03:58 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.160.252.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764947046; cv=none; b=kO8B3DyTLnutU2MjVUwxW2Jus8RojVLfwmGmNqk7X05aU9L1r8/N/Lvz+lXdW74dep01cgbGVKlR4XacGZNK7HdNC0a51I/xMBGRkAZKV7jA28novsUg2pj2Uy3uIBkdX+G2GfSrXsM+AR3ydj/xWVH78TlmjFBcPtGpvdtnNh8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764947046; c=relaxed/simple; bh=H5axve/7IvRQD57JHWUxJtvg+9R4N7VzznbCzJw7t+k=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=Sb/QwagonPzWGM5CZy/7Bv+Yd4DsirQRKoBM8QpY5i/6iCHLX71ZGmw+oxd50lBDFVkEvae/9tumb7fmTiwd7c0nn5Xv2r+X7ANQaXDtv9mzM4plpk3VTxAEC+Qim9JedYa+79veGJ9wXr3FlycB2OZsfRX9uQp6Tb2t+K945x8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=renesas.com; spf=pass smtp.mailfrom=renesas.com; arc=none smtp.client-ip=210.160.252.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=renesas.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=renesas.com X-CSE-ConnectionGUID: wfeEnoPKSFSw6c9hSKrPvA== X-CSE-MsgGUID: jFYdbiGrQbG0Fp6mBmQrPA== Received: from unknown (HELO relmlir6.idc.renesas.com) ([10.200.68.152]) by relmlie6.idc.renesas.com with ESMTP; 06 Dec 2025 00:03:57 +0900 Received: from demon-pc.localdomain (unknown [10.226.93.202]) by relmlir6.idc.renesas.com (Postfix) with ESMTP id 308A4427BFF2; Sat, 6 Dec 2025 00:03:53 +0900 (JST) From: Cosmin Tanislav To: Geert Uytterhoeven , Linus Walleij , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Magnus Damm , Lad Prabhakar Cc: linux-renesas-soc@vger.kernel.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Cosmin Tanislav Subject: [PATCH v2 6/8] arm64: dts: renesas: r9a09g087: add GPIO IRQ support Date: Fri, 5 Dec 2025 17:02:32 +0200 Message-ID: <20251205150234.2958140-7-cosmin-gabriel.tanislav.xa@renesas.com> X-Mailer: git-send-email 2.52.0 In-Reply-To: <20251205150234.2958140-1-cosmin-gabriel.tanislav.xa@renesas.com> References: <20251205150234.2958140-1-cosmin-gabriel.tanislav.xa@renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The Renesas RZ/N2H (R9A09G087) SoC includes pins which can be routed via the ICU to generate interrupts. Add support for using the pin controller as an interrupt chip. Signed-off-by: Cosmin Tanislav --- V2: * no changes arch/arm64/boot/dts/renesas/r9a09g087.dtsi | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a09g087.dtsi b/arch/arm64/boot/d= ts/renesas/r9a09g087.dtsi index 6b5693e5c1f9..19475c72017f 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g087.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a09g087.dtsi @@ -948,6 +948,9 @@ pinctrl: pinctrl@802c0000 { gpio-controller; #gpio-cells =3D <2>; gpio-ranges =3D <&pinctrl 0 0 280>; + #interrupt-cells =3D <2>; + interrupt-controller; + interrupt-parent =3D <&icu>; power-domains =3D <&cpg>; }; =20 --=20 2.52.0 From nobody Fri Dec 19 15:04:49 2025 Received: from relmlie6.idc.renesas.com (relmlor2.renesas.com [210.160.252.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 03563340A6D; Fri, 5 Dec 2025 15:04:04 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.160.252.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764947049; cv=none; b=LL6Fz8kuro6AZ56KFnkvN2qxdNZDyXhrz9p7s+TJwqX2KyE/FZhOJcsmG6TNHXnBotZZk8ui/hb6kklLhzKO+sDj9/vFBVBMYRfABwq3Hg+ZKb1DR9sq2fPYEDmvQE392+sDWnjMXST3m+WrrxeH1j/YLKL7HD3QcjAbjB4dkj8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764947049; c=relaxed/simple; bh=lzhjc9GfCVjKFFXiYW2RNyHcVm6fRIxR/unxy+GSB4A=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=KlSvYrCiwrqMozMZUyaUF0SwYiXUbVfFBdbHBAR/VfNw6ggSta8Yes7BZb163IYJ5tdrJqvcT4AJUC6vsdsxfcsXuO+bFMWFtIATG8kd/cyxk9pZHKed0MsbhS2QA0bYVZyIJEKiaGDn0rsud6dFKjkKaHXpNfwsLXX/YNW6I2g= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=renesas.com; spf=pass smtp.mailfrom=renesas.com; arc=none smtp.client-ip=210.160.252.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=renesas.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=renesas.com X-CSE-ConnectionGUID: F8F0wSGwT7a930s6VbC8Ow== X-CSE-MsgGUID: RWkaoWS4QGSZdawq9MfR8Q== Received: from unknown (HELO relmlir6.idc.renesas.com) ([10.200.68.152]) by relmlie6.idc.renesas.com with ESMTP; 06 Dec 2025 00:04:04 +0900 Received: from demon-pc.localdomain (unknown [10.226.93.202]) by relmlir6.idc.renesas.com (Postfix) with ESMTP id CC3D9427BFF0; Sat, 6 Dec 2025 00:04:00 +0900 (JST) From: Cosmin Tanislav To: Geert Uytterhoeven , Linus Walleij , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Magnus Damm , Lad Prabhakar Cc: linux-renesas-soc@vger.kernel.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Cosmin Tanislav Subject: [PATCH v2 7/8] arm64: dts: renesas: r9a09g077m44-rzt2h-evk: add GPIO keys Date: Fri, 5 Dec 2025 17:02:33 +0200 Message-ID: <20251205150234.2958140-8-cosmin-gabriel.tanislav.xa@renesas.com> X-Mailer: git-send-email 2.52.0 In-Reply-To: <20251205150234.2958140-1-cosmin-gabriel.tanislav.xa@renesas.com> References: <20251205150234.2958140-1-cosmin-gabriel.tanislav.xa@renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The Renesas RZ/T2H Evaluation Kit has three user buttons connected to GPIOs that can be used as input keys. Add support for them. Signed-off-by: Cosmin Tanislav --- V2: * no changes .../dts/renesas/r9a09g077m44-rzt2h-evk.dts | 33 +++++++++++++++++++ 1 file changed, 33 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a09g077m44-rzt2h-evk.dts b/arch/= arm64/boot/dts/renesas/r9a09g077m44-rzt2h-evk.dts index d1474f1bd523..a2584a3afb01 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g077m44-rzt2h-evk.dts +++ b/arch/arm64/boot/dts/renesas/r9a09g077m44-rzt2h-evk.dts @@ -7,6 +7,8 @@ =20 /dts-v1/; =20 +#include + #include "r9a09g077m44.dtsi" =20 /* @@ -60,6 +62,37 @@ / { model =3D "Renesas RZ/T2H EVK Board based on r9a09g077m44"; compatible =3D "renesas,rzt2h-evk", "renesas,r9a09g077m44", "renesas,r9a0= 9g077"; =20 + keys { + compatible =3D "gpio-keys"; + +#if (!SD1_MICRO_SD) + /* SW2-3: ON */ + key-1 { + interrupts-extended =3D <&pinctrl RZT2H_GPIO(8, 6) IRQ_TYPE_EDGE_FALLIN= G>; + linux,code =3D ; + label =3D "SW9"; + wakeup-source; + debounce-interval =3D <20>; + }; +#endif + + key-2 { + interrupts-extended =3D <&pinctrl RZT2H_GPIO(0, 3) IRQ_TYPE_EDGE_FALLIN= G>; + linux,code =3D ; + label =3D "SW10"; + wakeup-source; + debounce-interval =3D <20>; + }; + + key-3 { + interrupts-extended =3D <&pinctrl RZT2H_GPIO(8, 7) IRQ_TYPE_EDGE_FALLIN= G>; + linux,code =3D ; + label =3D "SW11"; + wakeup-source; + debounce-interval =3D <20>; + }; + }; + leds { compatible =3D "gpio-leds"; =20 --=20 2.52.0 From nobody Fri Dec 19 15:04:49 2025 Received: from relmlie6.idc.renesas.com (relmlor2.renesas.com [210.160.252.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 6D824340A63; Fri, 5 Dec 2025 15:04:11 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.160.252.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764947056; cv=none; b=RuPbjgV/V7qqKwdEUxV+J5M8OaXY5sLpVenr6XuPvOPPWrNS889BWJjhmAsy1DrMkgeQOSwiaasatMuSmB/FjPOy36RRVo/mz5F7Yg7rtBLbAEK9yIBSXJyKdVofWM3zlU6QwytvCsSrl7PIDNCzGMnZcixqw6+mwNtKMxSCgxk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764947056; c=relaxed/simple; bh=KMHkYhnYmqxTtq3KX0FEI2BkPOZrHLaa+sDCYGbpFEI=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=QgY3hF6UndXSBz7GXb7282A5WzDbEoERngiYNaOiX/M/fOuiSMAYfDUyKcqsBNfWRu4qA+u/vT6Enp35yTXcGg233RsNx5lAjcar/7w/hNegoBz23l/9t9Q4RePAgUZ2+WB8712TdqMCGvkGHgzc/jxqpeDTIXP4kNKnDUDhqjA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=renesas.com; spf=pass smtp.mailfrom=renesas.com; arc=none smtp.client-ip=210.160.252.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=renesas.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=renesas.com X-CSE-ConnectionGUID: MVk5J+a2RneP26ActZfuIA== X-CSE-MsgGUID: kMxTbUWiQ02OBlWmN0e69Q== Received: from unknown (HELO relmlir6.idc.renesas.com) ([10.200.68.152]) by relmlie6.idc.renesas.com with ESMTP; 06 Dec 2025 00:04:09 +0900 Received: from demon-pc.localdomain (unknown [10.226.93.202]) by relmlir6.idc.renesas.com (Postfix) with ESMTP id F22DF427BFF8; Sat, 6 Dec 2025 00:04:05 +0900 (JST) From: Cosmin Tanislav To: Geert Uytterhoeven , Linus Walleij , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Magnus Damm , Lad Prabhakar Cc: linux-renesas-soc@vger.kernel.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Cosmin Tanislav Subject: [PATCH v2 8/8] arm64: dts: renesas: r9a09g087m44-rzn2h-evk: add GPIO keys Date: Fri, 5 Dec 2025 17:02:34 +0200 Message-ID: <20251205150234.2958140-9-cosmin-gabriel.tanislav.xa@renesas.com> X-Mailer: git-send-email 2.52.0 In-Reply-To: <20251205150234.2958140-1-cosmin-gabriel.tanislav.xa@renesas.com> References: <20251205150234.2958140-1-cosmin-gabriel.tanislav.xa@renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The Renesas RZ/N2H Evaluation Kit has three user buttons connected to GPIOs that can be used as input keys. Add support for them. Signed-off-by: Cosmin Tanislav --- V2: * no changes .../dts/renesas/r9a09g087m44-rzn2h-evk.dts | 30 +++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a09g087m44-rzn2h-evk.dts b/arch/= arm64/boot/dts/renesas/r9a09g087m44-rzn2h-evk.dts index eaf73868783b..252f1c21ff90 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g087m44-rzn2h-evk.dts +++ b/arch/arm64/boot/dts/renesas/r9a09g087m44-rzn2h-evk.dts @@ -7,6 +7,8 @@ =20 /dts-v1/; =20 +#include + #include "r9a09g087m44.dtsi" =20 /* @@ -77,6 +79,34 @@ / { model =3D "Renesas RZ/N2H EVK Board based on r9a09g087m44"; compatible =3D "renesas,rzn2h-evk", "renesas,r9a09g087m44", "renesas,r9a0= 9g087"; =20 + keys { + compatible =3D "gpio-keys"; + + key-1 { + interrupts-extended =3D <&pinctrl RZT2H_GPIO(18, 2) IRQ_TYPE_EDGE_FALLI= NG>; + linux,code =3D ; + label =3D "SW2"; + wakeup-source; + debounce-interval =3D <20>; + }; + + key-2 { + interrupts-extended =3D <&pinctrl RZT2H_GPIO(0, 4) IRQ_TYPE_EDGE_FALLIN= G>; + linux,code =3D ; + label =3D "SW3"; + wakeup-source; + debounce-interval =3D <20>; + }; + + key-3 { + interrupts-extended =3D <&pinctrl RZT2H_GPIO(18, 7) IRQ_TYPE_EDGE_FALLI= NG>; + linux,code =3D ; + label =3D "SW4"; + wakeup-source; + debounce-interval =3D <20>; + }; + }; + leds { compatible =3D "gpio-leds"; =20 --=20 2.52.0