From nobody Fri Dec 19 15:51:36 2025 Received: from out28-3.mail.aliyun.com (out28-3.mail.aliyun.com [115.124.28.3]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D7672309EFA; Fri, 5 Dec 2025 09:42:17 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=115.124.28.3 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764927747; cv=none; b=qt/8n37hoMXh9Tb17AsRU8sQ+70d4LQRvBmMn6z/ZfMMXBY83yEGcJ0XzF/K/WjGb/U6FYxgyTlupUYN0zjRci296QgW/+D7wh8GH4z4Bq8GLPfQU90bkantQ/4WE8nwyg+rzXyLMU0m2c6kTnHayy8fB1e0bwmvADq6VO07An8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764927747; c=relaxed/simple; bh=ppQPS0N9E/PJBcTSbSTk5MAHlDlKeG8mU7ofuh9dmOA=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=BJljXUsfT8eRmbPaevmo2+ZsTOVumljf5Tkczznr/p8OIg1hqA168G8n3AIRRzbPLzxx9A+ez7buCqcHJ4HPbfJGuhxsZEbnD6pHW8LZI53I5xq7kVgtTe+sllLJtk2LISiqn/LWEie3WxeoGjMnZ280BhIpc9XAZWHzv5sxj7c= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=open-hieco.net; spf=pass smtp.mailfrom=open-hieco.net; arc=none smtp.client-ip=115.124.28.3 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=open-hieco.net Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=open-hieco.net Received: from localhost.localdomain(mailfrom:shenxiaochen@open-hieco.net fp:SMTPD_---.fdWs0T0_1764926783 cluster:ay29) by smtp.aliyun-inc.com; Fri, 05 Dec 2025 17:26:26 +0800 From: Xiaochen Shen To: tony.luck@intel.com, reinette.chatre@intel.com, bp@alien8.de, fenghuay@nvidia.com, shuah@kernel.org, skhan@linuxfoundation.org Cc: babu.moger@amd.com, james.morse@arm.com, Dave.Martin@arm.com, x86@kernel.org, linux-kernel@vger.kernel.org, linux-kselftest@vger.kernel.org, shenxiaochen@open-hieco.net Subject: [PATCH v2 1/3] selftests/resctrl: Add CPU vendor detection for Hygon Date: Fri, 5 Dec 2025 17:25:42 +0800 Message-ID: <20251205092544.2685728-2-shenxiaochen@open-hieco.net> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20251205092544.2685728-1-shenxiaochen@open-hieco.net> References: <20251205092544.2685728-1-shenxiaochen@open-hieco.net> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The resctrl selftest currently fails on Hygon CPUs that support Platform QoS features, printing the error: "# Can not get vendor info..." This occurs because vendor detection is missing for Hygon CPUs. Fix this by extending the CPU vendor detection logic to include Hygon's vendor ID. Signed-off-by: Xiaochen Shen --- tools/testing/selftests/resctrl/resctrl.h | 6 ++++-- tools/testing/selftests/resctrl/resctrl_tests.c | 2 ++ 2 files changed, 6 insertions(+), 2 deletions(-) diff --git a/tools/testing/selftests/resctrl/resctrl.h b/tools/testing/self= tests/resctrl/resctrl.h index cd3adfc14969..411ee10380a5 100644 --- a/tools/testing/selftests/resctrl/resctrl.h +++ b/tools/testing/selftests/resctrl/resctrl.h @@ -23,6 +23,7 @@ #include #include #include +#include #include "../kselftest.h" =20 #define MB (1024 * 1024) @@ -36,8 +37,9 @@ * Define as bits because they're used for vendor_specific bitmask in * the struct resctrl_test. */ -#define ARCH_INTEL 1 -#define ARCH_AMD 2 +#define ARCH_INTEL BIT(0) +#define ARCH_AMD BIT(1) +#define ARCH_HYGON BIT(2) =20 #define END_OF_TESTS 1 =20 diff --git a/tools/testing/selftests/resctrl/resctrl_tests.c b/tools/testin= g/selftests/resctrl/resctrl_tests.c index 5154ffd821c4..9bf35f3beb6b 100644 --- a/tools/testing/selftests/resctrl/resctrl_tests.c +++ b/tools/testing/selftests/resctrl/resctrl_tests.c @@ -42,6 +42,8 @@ static int detect_vendor(void) vendor_id =3D ARCH_INTEL; else if (s && !strcmp(s, ": AuthenticAMD\n")) vendor_id =3D ARCH_AMD; + else if (s && !strcmp(s, ": HygonGenuine\n")) + vendor_id =3D ARCH_HYGON; =20 fclose(inf); free(res); --=20 2.47.3 From nobody Fri Dec 19 15:51:36 2025 Received: from out28-4.mail.aliyun.com (out28-4.mail.aliyun.com [115.124.28.4]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9D07B3043CF; Fri, 5 Dec 2025 09:26:34 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=115.124.28.4 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764926804; cv=none; b=NMKSJ7Nh8lDkkoHmCWiePMUZiTZ/UkzDfSjJhb9YAx35PaealkSsyPJGTuSgdxwdI1XFAIIQhFX/aVo8BdH5w5Zb+wlMA5jpatO8dtLiaDFu98Id0HUHJhzRmWh0gvfPZ3nJxOn5RpiqD4a/G5c2u6SVQMrVp5yXztwmFp0gH3U= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764926804; c=relaxed/simple; bh=WseTNk88/NYojYS1ySl2tLjv9eX/PweY/wlISWR/G8Y=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=HjZiwh2F8DYSi9p0/Nhu/vHit6mUqAVJh2/DekRFgrd8GB2W8T95dN0SRSkMjzPQDVwSxgqN8Zq+3eAlMH6o7zbspzX/bBpv5/tbHqVLR3zfC9h320fnM3jnopNb0Mtmi7o4+mZJDhaQuIDpRiQ2ZcxCeaOTMR/q7JyW00xvFVU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=open-hieco.net; spf=pass smtp.mailfrom=open-hieco.net; arc=none smtp.client-ip=115.124.28.4 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=open-hieco.net Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=open-hieco.net Received: from localhost.localdomain(mailfrom:shenxiaochen@open-hieco.net fp:SMTPD_---.fdWs0Y2_1764926787 cluster:ay29) by smtp.aliyun-inc.com; Fri, 05 Dec 2025 17:26:30 +0800 From: Xiaochen Shen To: tony.luck@intel.com, reinette.chatre@intel.com, bp@alien8.de, fenghuay@nvidia.com, shuah@kernel.org, skhan@linuxfoundation.org Cc: babu.moger@amd.com, james.morse@arm.com, Dave.Martin@arm.com, x86@kernel.org, linux-kernel@vger.kernel.org, linux-kselftest@vger.kernel.org, shenxiaochen@open-hieco.net Subject: [PATCH v2 2/3] selftests/resctrl: Fix a division by zero error on Hygon Date: Fri, 5 Dec 2025 17:25:43 +0800 Message-ID: <20251205092544.2685728-3-shenxiaochen@open-hieco.net> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20251205092544.2685728-1-shenxiaochen@open-hieco.net> References: <20251205092544.2685728-1-shenxiaochen@open-hieco.net> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Commit a1cd99e700ec ("selftests/resctrl: Adjust effective L3 cache size with SNC= enabled") introduced the snc_nodes_per_l3_cache() function to detect the Intel Sub-NUMA Clustering (SNC) feature by comparing #CPUs in node0 with #CPUs sharing LLC with CPU0. The function was designed to return: (1) >1: SNC mode is enabled. (2) 1: SNC mode is not enabled or not supported. However, on certain Hygon CPUs, #CPUs sharing LLC with CPU0 is actually less than #CPUs in node0. This results in snc_nodes_per_l3_cache() returning 0 (calculated as cache_cpus / node_cpus). This leads to a division by zero error in get_cache_size(): *cache_size /=3D snc_nodes_per_l3_cache(); Causing the resctrl selftest to fail with: "Floating point exception (core dumped)" Fix the issue by ensuring snc_nodes_per_l3_cache() returns 1 when SNC mode is not supported on the platform. Fixes: a1cd99e700ec ("selftests/resctrl: Adjust effective L3 cache size wit= h SNC enabled") Signed-off-by: Xiaochen Shen Reviewed-by: Reinette Chatre Reviewed-by: Fenghua Yu --- tools/testing/selftests/resctrl/resctrlfs.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/tools/testing/selftests/resctrl/resctrlfs.c b/tools/testing/se= lftests/resctrl/resctrlfs.c index 195f04c4d158..2b075e7334bf 100644 --- a/tools/testing/selftests/resctrl/resctrlfs.c +++ b/tools/testing/selftests/resctrl/resctrlfs.c @@ -243,6 +243,16 @@ int snc_nodes_per_l3_cache(void) } snc_mode =3D cache_cpus / node_cpus; =20 + /* + * On certain Hygon platforms: + * cache_cpus < node_cpus, the calculated snc_mode is 0. + * + * Set snc_mode =3D 1 to indicate that SNC mode is not + * supported on the platform. + */ + if (!snc_mode) + snc_mode =3D 1; + if (snc_mode > 1) ksft_print_msg("SNC-%d mode discovered.\n", snc_mode); } --=20 2.47.3 From nobody Fri Dec 19 15:51:36 2025 Received: from out198-22.us.a.mail.aliyun.com (out198-22.us.a.mail.aliyun.com [47.90.198.22]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A05F631E0F2; Fri, 5 Dec 2025 09:26:48 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=47.90.198.22 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764926816; cv=none; b=t/YWVuhe117Untn0IuTLcfzCj7xmrkbmO789hTn9TRdSUAYfQMFt5j/VDBCG4EG3gtJwJxP7zwTe233+jKajU8KQCnMmf8SPC+A6rCeA9hvTFM4qHKuklfjZqnntOAUjRsjoo1vdZoQRWbJ3AcpEJ6JLmy19BeEStACWP1QPaNQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764926816; c=relaxed/simple; bh=4Au5rdmQLVAEduwB6+M3lpqu37MV3Hl5yGpAXcNfPis=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=XEEw9Kmoc6Mhg//8bsoyswbx+gE1E3KnnEqsKODrauQbzowXx7l423CyTQtf4q8z/E2rpzM4pfEC7kCi0xDYKj6xEnl4C/hHAPuCI4AfDJfqY2RaCf0PUzKvCTl9OP267kFOs6V2RTB2iBhFphW97py7zWMm+1C5YbgpalzIC2s= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=open-hieco.net; spf=pass smtp.mailfrom=open-hieco.net; arc=none smtp.client-ip=47.90.198.22 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=open-hieco.net Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=open-hieco.net Received: from localhost.localdomain(mailfrom:shenxiaochen@open-hieco.net fp:SMTPD_---.fdWs0cR_1764926790 cluster:ay29) by smtp.aliyun-inc.com; Fri, 05 Dec 2025 17:26:34 +0800 From: Xiaochen Shen To: tony.luck@intel.com, reinette.chatre@intel.com, bp@alien8.de, fenghuay@nvidia.com, shuah@kernel.org, skhan@linuxfoundation.org Cc: babu.moger@amd.com, james.morse@arm.com, Dave.Martin@arm.com, x86@kernel.org, linux-kernel@vger.kernel.org, linux-kselftest@vger.kernel.org, shenxiaochen@open-hieco.net Subject: [PATCH v2 3/3] selftests/resctrl: Fix non-contiguous CBM check for Hygon Date: Fri, 5 Dec 2025 17:25:44 +0800 Message-ID: <20251205092544.2685728-4-shenxiaochen@open-hieco.net> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20251205092544.2685728-1-shenxiaochen@open-hieco.net> References: <20251205092544.2685728-1-shenxiaochen@open-hieco.net> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The resctrl selftest currently fails on Hygon CPUs that always supports non-contiguous CBM, printing the error: "# Hardware and kernel differ on non-contiguous CBM support!" This occurs because the arch_supports_noncont_cat() function lacks vendor detection for Hygon CPUs, preventing proper identification of their non-contiguous CBM capability. Fix this by adding Hygon vendor ID detection to arch_supports_noncont_cat(). Signed-off-by: Xiaochen Shen Reviewed-by: Reinette Chatre Reviewed-by: Fenghua Yu --- Maintainer note: Even though this is a fix it is not a candidate for backport since it is based on another patch series (x86/resctrl: Fix Platform QoS issues for Hygon) which is in process of being added to resctrl. tools/testing/selftests/resctrl/cat_test.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/tools/testing/selftests/resctrl/cat_test.c b/tools/testing/sel= ftests/resctrl/cat_test.c index 94cfdba5308d..59a0f80fdc5a 100644 --- a/tools/testing/selftests/resctrl/cat_test.c +++ b/tools/testing/selftests/resctrl/cat_test.c @@ -290,8 +290,8 @@ static int cat_run_test(const struct resctrl_test *test= , const struct user_param =20 static bool arch_supports_noncont_cat(const struct resctrl_test *test) { - /* AMD always supports non-contiguous CBM. */ - if (get_vendor() =3D=3D ARCH_AMD) + /* AMD and Hygon always supports non-contiguous CBM. */ + if (get_vendor() =3D=3D ARCH_AMD || get_vendor() =3D=3D ARCH_HYGON) return true; =20 #if defined(__i386__) || defined(__x86_64__) /* arch */ --=20 2.47.3