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Peter Anvin" Subject: [PATCH 06/10] KVM/x86: Use defines for APIC related MSR emulation Date: Fri, 5 Dec 2025 08:45:33 +0100 Message-ID: <20251205074537.17072-7-jgross@suse.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20251205074537.17072-1-jgross@suse.com> References: <20251205074537.17072-1-jgross@suse.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Spamd-Result: default: False [-2.80 / 50.00]; BAYES_HAM(-3.00)[100.00%]; NEURAL_HAM_LONG(-1.00)[-1.000]; MID_CONTAINS_FROM(1.00)[]; R_MISSING_CHARSET(0.50)[]; NEURAL_HAM_SHORT(-0.20)[-0.988]; MIME_GOOD(-0.10)[text/plain]; TO_MATCH_ENVRCPT_ALL(0.00)[]; ARC_NA(0.00)[]; RCVD_VIA_SMTP_AUTH(0.00)[]; FROM_HAS_DN(0.00)[]; TO_DN_SOME(0.00)[]; MIME_TRACE(0.00)[0:+]; DBL_BLOCKED_OPENRESOLVER(0.00)[imap1.dmz-prg2.suse.org:helo,suse.com:mid,suse.com:email]; FUZZY_RATELIMITED(0.00)[rspamd.com]; RCPT_COUNT_SEVEN(0.00)[11]; RCVD_COUNT_TWO(0.00)[2]; FROM_EQ_ENVFROM(0.00)[]; DKIM_SIGNED(0.00)[suse.com:s=susede1]; R_RATELIMIT(0.00)[to_ip_from(RLfdszjqhz8kzzb9uwpzdm8png)]; RCVD_TLS_ALL(0.00)[] X-Spam-Level: X-Spam-Flag: NO X-Spam-Score: -2.80 Content-Type: text/plain; charset="utf-8" Instead of "0" and "1" use the related KVM_MSR_RET_* defines in the emulation code of APIC related MSR registers. No change of functionality intended. Signed-off-by: Juergen Gross --- arch/x86/kvm/lapic.c | 48 ++++++++++++++++++++++---------------------- 1 file changed, 24 insertions(+), 24 deletions(-) diff --git a/arch/x86/kvm/lapic.c b/arch/x86/kvm/lapic.c index 0ae7f913d782..bd4c0768b270 100644 --- a/arch/x86/kvm/lapic.c +++ b/arch/x86/kvm/lapic.c @@ -2339,7 +2339,7 @@ static int get_lvt_index(u32 reg) =20 static int kvm_lapic_reg_write(struct kvm_lapic *apic, u32 reg, u32 val) { - int ret =3D 0; + int ret =3D KVM_MSR_RET_OK; =20 trace_kvm_apic_write(reg, val); =20 @@ -2348,7 +2348,7 @@ static int kvm_lapic_reg_write(struct kvm_lapic *apic= , u32 reg, u32 val) if (!apic_x2apic_mode(apic)) { kvm_apic_set_xapic_id(apic, val >> 24); } else { - ret =3D 1; + ret =3D KVM_MSR_RET_ERR; } break; =20 @@ -2365,14 +2365,14 @@ static int kvm_lapic_reg_write(struct kvm_lapic *ap= ic, u32 reg, u32 val) if (!apic_x2apic_mode(apic)) kvm_apic_set_ldr(apic, val & APIC_LDR_MASK); else - ret =3D 1; + ret =3D KVM_MSR_RET_ERR; break; =20 case APIC_DFR: if (!apic_x2apic_mode(apic)) kvm_apic_set_dfr(apic, val | 0x0FFFFFFF); else - ret =3D 1; + ret =3D KVM_MSR_RET_ERR; break; =20 case APIC_SPIV: { @@ -2403,7 +2403,7 @@ static int kvm_lapic_reg_write(struct kvm_lapic *apic= , u32 reg, u32 val) break; case APIC_ICR2: if (apic_x2apic_mode(apic)) - ret =3D 1; + ret =3D KVM_MSR_RET_ERR; else kvm_lapic_set_reg(apic, APIC_ICR2, val & 0xff000000); break; @@ -2418,7 +2418,7 @@ static int kvm_lapic_reg_write(struct kvm_lapic *apic= , u32 reg, u32 val) case APIC_LVTCMCI: { u32 index =3D get_lvt_index(reg); if (!kvm_lapic_lvt_supported(apic, index)) { - ret =3D 1; + ret =3D KVM_MSR_RET_ERR; break; } if (!kvm_apic_sw_enabled(apic)) @@ -2460,7 +2460,7 @@ static int kvm_lapic_reg_write(struct kvm_lapic *apic= , u32 reg, u32 val) } case APIC_ESR: if (apic_x2apic_mode(apic) && val !=3D 0) - ret =3D 1; + ret =3D KVM_MSR_RET_ERR; break; =20 case APIC_SELF_IPI: @@ -2469,12 +2469,12 @@ static int kvm_lapic_reg_write(struct kvm_lapic *ap= ic, u32 reg, u32 val) * the vector, everything else is reserved. */ if (!apic_x2apic_mode(apic) || (val & ~APIC_VECTOR_MASK)) - ret =3D 1; + ret =3D KVM_MSR_RET_ERR; else kvm_apic_send_ipi(apic, APIC_DEST_SELF | val, 0); break; default: - ret =3D 1; + ret =3D KVM_MSR_RET_ERR; break; } =20 @@ -2532,7 +2532,7 @@ EXPORT_SYMBOL_FOR_KVM_INTERNAL(kvm_lapic_set_eoi); static int __kvm_x2apic_icr_write(struct kvm_lapic *apic, u64 data, bool f= ast) { if (data & X2APIC_ICR_RESERVED_BITS) - return 1; + return KVM_MSR_RET_ERR; =20 /* * The BUSY bit is reserved on both Intel and AMD in x2APIC mode, but @@ -2565,7 +2565,7 @@ static int __kvm_x2apic_icr_write(struct kvm_lapic *a= pic, u64 data, bool fast) kvm_lapic_set_reg64(apic, APIC_ICR, data); } trace_kvm_apic_write(APIC_ICR, data); - return 0; + return KVM_MSR_RET_OK; } =20 static int kvm_x2apic_icr_write(struct kvm_lapic *apic, u64 data) @@ -2728,23 +2728,23 @@ int kvm_apic_set_base(struct kvm_vcpu *vcpu, u64 va= lue, bool host_initiated) enum lapic_mode new_mode =3D kvm_apic_mode(value); =20 if (vcpu->arch.apic_base =3D=3D value) - return 0; + return KVM_MSR_RET_OK; =20 u64 reserved_bits =3D kvm_vcpu_reserved_gpa_bits_raw(vcpu) | 0x2ff | (guest_cpu_cap_has(vcpu, X86_FEATURE_X2APIC) ? 0 : X2APIC_ENABLE); =20 if ((value & reserved_bits) !=3D 0 || new_mode =3D=3D LAPIC_MODE_INVALID) - return 1; + return KVM_MSR_RET_ERR; if (!host_initiated) { if (old_mode =3D=3D LAPIC_MODE_X2APIC && new_mode =3D=3D LAPIC_MODE_XAPI= C) - return 1; + return KVM_MSR_RET_ERR; if (old_mode =3D=3D LAPIC_MODE_DISABLED && new_mode =3D=3D LAPIC_MODE_X2= APIC) - return 1; + return KVM_MSR_RET_ERR; } =20 __kvm_apic_set_base(vcpu, value); kvm_recalculate_apic_map(vcpu->kvm); - return 0; + return KVM_MSR_RET_OK; } EXPORT_SYMBOL_FOR_KVM_INTERNAL(kvm_apic_set_base); =20 @@ -3362,15 +3362,15 @@ static int kvm_lapic_msr_read(struct kvm_lapic *api= c, u32 reg, u64 *data) =20 if (reg =3D=3D APIC_ICR) { *data =3D kvm_x2apic_icr_read(apic); - return 0; + return KVM_MSR_RET_OK; } =20 if (kvm_lapic_reg_read(apic, reg, 4, &low)) - return 1; + return KVM_MSR_RET_ERR; =20 *data =3D low; =20 - return 0; + return KVM_MSR_RET_OK; } =20 static int kvm_lapic_msr_write(struct kvm_lapic *apic, u32 reg, u64 data) @@ -3385,7 +3385,7 @@ static int kvm_lapic_msr_write(struct kvm_lapic *apic= , u32 reg, u64 data) =20 /* Bits 63:32 are reserved in all other registers. */ if (data >> 32) - return 1; + return KVM_MSR_RET_ERR; =20 return kvm_lapic_reg_write(apic, reg, (u32)data); } @@ -3396,7 +3396,7 @@ int kvm_x2apic_msr_write(struct kvm_vcpu *vcpu, u32 m= sr, u64 data) u32 reg =3D (msr - APIC_BASE_MSR) << 4; =20 if (!lapic_in_kernel(vcpu) || !apic_x2apic_mode(apic)) - return 1; + return KVM_MSR_RET_ERR; =20 return kvm_lapic_msr_write(apic, reg, data); } @@ -3407,7 +3407,7 @@ int kvm_x2apic_msr_read(struct kvm_vcpu *vcpu, u32 ms= r, u64 *data) u32 reg =3D (msr - APIC_BASE_MSR) << 4; =20 if (!lapic_in_kernel(vcpu) || !apic_x2apic_mode(apic)) - return 1; + return KVM_MSR_RET_ERR; =20 return kvm_lapic_msr_read(apic, reg, data); } @@ -3415,7 +3415,7 @@ int kvm_x2apic_msr_read(struct kvm_vcpu *vcpu, u32 ms= r, u64 *data) int kvm_hv_vapic_msr_write(struct kvm_vcpu *vcpu, u32 reg, u64 data) { if (!lapic_in_kernel(vcpu)) - return 1; + return KVM_MSR_RET_ERR; =20 return kvm_lapic_msr_write(vcpu->arch.apic, reg, data); } @@ -3423,7 +3423,7 @@ int kvm_hv_vapic_msr_write(struct kvm_vcpu *vcpu, u32= reg, u64 data) int kvm_hv_vapic_msr_read(struct kvm_vcpu *vcpu, u32 reg, u64 *data) { if (!lapic_in_kernel(vcpu)) - return 1; + return KVM_MSR_RET_ERR; =20 return kvm_lapic_msr_read(vcpu->arch.apic, reg, data); } --=20 2.51.0