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Peter Anvin" Subject: [PATCH 09/10] KVM/x86: Use defines for SVM related MSR emulation Date: Fri, 5 Dec 2025 08:45:36 +0100 Message-ID: <20251205074537.17072-10-jgross@suse.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20251205074537.17072-1-jgross@suse.com> References: <20251205074537.17072-1-jgross@suse.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Spamd-Result: default: False [-2.80 / 50.00]; BAYES_HAM(-3.00)[100.00%]; NEURAL_HAM_LONG(-1.00)[-1.000]; MID_CONTAINS_FROM(1.00)[]; R_MISSING_CHARSET(0.50)[]; NEURAL_HAM_SHORT(-0.20)[-0.988]; MIME_GOOD(-0.10)[text/plain]; TO_MATCH_ENVRCPT_ALL(0.00)[]; ARC_NA(0.00)[]; RCVD_VIA_SMTP_AUTH(0.00)[]; FROM_HAS_DN(0.00)[]; TO_DN_SOME(0.00)[]; MIME_TRACE(0.00)[0:+]; DBL_BLOCKED_OPENRESOLVER(0.00)[suse.com:mid,suse.com:email,imap1.dmz-prg2.suse.org:helo]; FUZZY_RATELIMITED(0.00)[rspamd.com]; RCPT_COUNT_SEVEN(0.00)[11]; RCVD_COUNT_TWO(0.00)[2]; FROM_EQ_ENVFROM(0.00)[]; DKIM_SIGNED(0.00)[suse.com:s=susede1]; R_RATELIMIT(0.00)[to_ip_from(RLfdszjqhz8kzzb9uwpzdm8png)]; RCVD_TLS_ALL(0.00)[] X-Spam-Level: X-Spam-Flag: NO X-Spam-Score: -2.80 Content-Type: text/plain; charset="utf-8" Instead of "0" and "1" use the related KVM_MSR_RET_* defines in the emulation code of SVM related MSR registers. No change of functionality intended. Signed-off-by: Juergen Gross --- arch/x86/kvm/svm/pmu.c | 12 ++++++------ arch/x86/kvm/svm/svm.c | 44 +++++++++++++++++++++--------------------- 2 files changed, 28 insertions(+), 28 deletions(-) diff --git a/arch/x86/kvm/svm/pmu.c b/arch/x86/kvm/svm/pmu.c index bc062285fbf5..c4b2fe77cc27 100644 --- a/arch/x86/kvm/svm/pmu.c +++ b/arch/x86/kvm/svm/pmu.c @@ -135,16 +135,16 @@ static int amd_pmu_get_msr(struct kvm_vcpu *vcpu, str= uct msr_data *msr_info) pmc =3D get_gp_pmc_amd(pmu, msr, PMU_TYPE_COUNTER); if (pmc) { msr_info->data =3D pmc_read_counter(pmc); - return 0; + return KVM_MSR_RET_OK; } /* MSR_EVNTSELn */ pmc =3D get_gp_pmc_amd(pmu, msr, PMU_TYPE_EVNTSEL); if (pmc) { msr_info->data =3D pmc->eventsel; - return 0; + return KVM_MSR_RET_OK; } =20 - return 1; + return KVM_MSR_RET_ERR; } =20 static int amd_pmu_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_inf= o) @@ -158,7 +158,7 @@ static int amd_pmu_set_msr(struct kvm_vcpu *vcpu, struc= t msr_data *msr_info) pmc =3D get_gp_pmc_amd(pmu, msr, PMU_TYPE_COUNTER); if (pmc) { pmc_write_counter(pmc, data); - return 0; + return KVM_MSR_RET_OK; } /* MSR_EVNTSELn */ pmc =3D get_gp_pmc_amd(pmu, msr, PMU_TYPE_EVNTSEL); @@ -168,10 +168,10 @@ static int amd_pmu_set_msr(struct kvm_vcpu *vcpu, str= uct msr_data *msr_info) pmc->eventsel =3D data; kvm_pmu_request_counter_reprogram(pmc); } - return 0; + return KVM_MSR_RET_OK; } =20 - return 1; + return KVM_MSR_RET_ERR; } =20 static void amd_pmu_refresh(struct kvm_vcpu *vcpu) diff --git a/arch/x86/kvm/svm/svm.c b/arch/x86/kvm/svm/svm.c index 7cbf4d686415..73ff38617311 100644 --- a/arch/x86/kvm/svm/svm.c +++ b/arch/x86/kvm/svm/svm.c @@ -2638,7 +2638,7 @@ static int svm_get_feature_msr(u32 msr, u64 *data) return KVM_MSR_RET_UNSUPPORTED; } =20 - return 0; + return KVM_MSR_RET_OK; } =20 static bool sev_es_prevent_msr_access(struct kvm_vcpu *vcpu, @@ -2655,14 +2655,14 @@ static int svm_get_msr(struct kvm_vcpu *vcpu, struc= t msr_data *msr_info) =20 if (sev_es_prevent_msr_access(vcpu, msr_info)) { msr_info->data =3D 0; - return vcpu->kvm->arch.has_protected_state ? -EINVAL : 0; + return vcpu->kvm->arch.has_protected_state ? -EINVAL : KVM_MSR_RET_OK; } =20 switch (msr_info->index) { case MSR_AMD64_TSC_RATIO: if (!msr_info->host_initiated && !guest_cpu_cap_has(vcpu, X86_FEATURE_TSCRATEMSR)) - return 1; + return KVM_MSR_RET_ERR; msr_info->data =3D svm->tsc_ratio_msr; break; case MSR_STAR: @@ -2737,7 +2737,7 @@ static int svm_get_msr(struct kvm_vcpu *vcpu, struct = msr_data *msr_info) case MSR_IA32_SPEC_CTRL: if (!msr_info->host_initiated && !guest_has_spec_ctrl_msr(vcpu)) - return 1; + return KVM_MSR_RET_ERR; =20 if (boot_cpu_has(X86_FEATURE_V_SPEC_CTRL)) msr_info->data =3D svm->vmcb->save.spec_ctrl; @@ -2747,7 +2747,7 @@ static int svm_get_msr(struct kvm_vcpu *vcpu, struct = msr_data *msr_info) case MSR_AMD64_VIRT_SPEC_CTRL: if (!msr_info->host_initiated && !guest_cpu_cap_has(vcpu, X86_FEATURE_VIRT_SSBD)) - return 1; + return KVM_MSR_RET_ERR; =20 msr_info->data =3D svm->virt_spec_ctrl; break; @@ -2774,7 +2774,7 @@ static int svm_get_msr(struct kvm_vcpu *vcpu, struct = msr_data *msr_info) default: return kvm_get_msr_common(vcpu, msr_info); } - return 0; + return KVM_MSR_RET_OK; } =20 static int svm_complete_emulated_msr(struct kvm_vcpu *vcpu, bool err) @@ -2793,7 +2793,7 @@ static int svm_set_vm_cr(struct kvm_vcpu *vcpu, u64 d= ata) int svm_dis, chg_mask; =20 if (data & ~SVM_VM_CR_VALID_MASK) - return 1; + return KVM_MSR_RET_ERR; =20 chg_mask =3D SVM_VM_CR_VALID_MASK; =20 @@ -2807,21 +2807,21 @@ static int svm_set_vm_cr(struct kvm_vcpu *vcpu, u64= data) =20 /* check for svm_disable while efer.svme is set */ if (svm_dis && (vcpu->arch.efer & EFER_SVME)) - return 1; + return KVM_MSR_RET_ERR; =20 - return 0; + return KVM_MSR_RET_OK; } =20 static int svm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr) { struct vcpu_svm *svm =3D to_svm(vcpu); - int ret =3D 0; + int ret =3D KVM_MSR_RET_OK; =20 u32 ecx =3D msr->index; u64 data =3D msr->data; =20 if (sev_es_prevent_msr_access(vcpu, msr)) - return vcpu->kvm->arch.has_protected_state ? -EINVAL : 0; + return vcpu->kvm->arch.has_protected_state ? -EINVAL : KVM_MSR_RET_OK; =20 switch (ecx) { case MSR_AMD64_TSC_RATIO: @@ -2829,7 +2829,7 @@ static int svm_set_msr(struct kvm_vcpu *vcpu, struct = msr_data *msr) if (!guest_cpu_cap_has(vcpu, X86_FEATURE_TSCRATEMSR)) { =20 if (!msr->host_initiated) - return 1; + return KVM_MSR_RET_ERR; /* * In case TSC scaling is not enabled, always * leave this MSR at the default value. @@ -2839,12 +2839,12 @@ static int svm_set_msr(struct kvm_vcpu *vcpu, struc= t msr_data *msr) * Ignore this value as well. */ if (data !=3D 0 && data !=3D svm->tsc_ratio_msr) - return 1; + return KVM_MSR_RET_ERR; break; } =20 if (data & SVM_TSC_RATIO_RSVD) - return 1; + return KVM_MSR_RET_ERR; =20 svm->tsc_ratio_msr =3D data; =20 @@ -2866,10 +2866,10 @@ static int svm_set_msr(struct kvm_vcpu *vcpu, struc= t msr_data *msr) case MSR_IA32_SPEC_CTRL: if (!msr->host_initiated && !guest_has_spec_ctrl_msr(vcpu)) - return 1; + return KVM_MSR_RET_ERR; =20 if (kvm_spec_ctrl_test_value(data)) - return 1; + return KVM_MSR_RET_ERR; =20 if (boot_cpu_has(X86_FEATURE_V_SPEC_CTRL)) svm->vmcb->save.spec_ctrl =3D data; @@ -2894,10 +2894,10 @@ static int svm_set_msr(struct kvm_vcpu *vcpu, struc= t msr_data *msr) case MSR_AMD64_VIRT_SPEC_CTRL: if (!msr->host_initiated && !guest_cpu_cap_has(vcpu, X86_FEATURE_VIRT_SSBD)) - return 1; + return KVM_MSR_RET_ERR; =20 if (data & ~SPEC_CTRL_SSBD) - return 1; + return KVM_MSR_RET_ERR; =20 svm->virt_spec_ctrl =3D data; break; @@ -2992,7 +2992,7 @@ static int svm_set_msr(struct kvm_vcpu *vcpu, struct = msr_data *msr) } =20 if (data & DEBUGCTL_RESERVED_BITS) - return 1; + return KVM_MSR_RET_ERR; =20 if (svm->vmcb->save.dbgctl =3D=3D data) break; @@ -3009,7 +3009,7 @@ static int svm_set_msr(struct kvm_vcpu *vcpu, struct = msr_data *msr) * originating from those kernels. */ if (!msr->host_initiated && !page_address_valid(vcpu, data)) - return 1; + return KVM_MSR_RET_ERR; =20 svm->nested.hsave_msr =3D data & PAGE_MASK; break; @@ -3022,10 +3022,10 @@ static int svm_set_msr(struct kvm_vcpu *vcpu, struc= t msr_data *msr) u64 supported_de_cfg; =20 if (svm_get_feature_msr(ecx, &supported_de_cfg)) - return 1; + return KVM_MSR_RET_ERR; =20 if (data & ~supported_de_cfg) - return 1; + return KVM_MSR_RET_ERR; =20 svm->msr_decfg =3D data; break; --=20 2.51.0