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Thu, 4 Dec 2025 22:58:55 -0800 From: Ashish Mhetre To: , , , , , , CC: , , , , , , , , , Ashish Mhetre Subject: [PATCH V4 1/3] iommu/arm-smmu-v3: Add device-tree support for CMDQV driver Date: Fri, 5 Dec 2025 06:58:48 +0000 Message-ID: <20251205065850.3841834-2-amhetre@nvidia.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20251205065850.3841834-1-amhetre@nvidia.com> References: <20251205065850.3841834-1-amhetre@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NVConfidentiality: public Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS1PEPF0001709B:EE_|DM4PR12MB5890:EE_ X-MS-Office365-Filtering-Correlation-Id: c68969c2-1e99-41cf-2e83-08de33cbc601 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|7416014|376014|36860700013|1800799024|82310400026; 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 05 Dec 2025 06:59:02.5046 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: c68969c2-1e99-41cf-2e83-08de33cbc601 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DS1PEPF0001709B.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR12MB5890 Content-Type: text/plain; charset="utf-8" Add device tree support to the CMDQV driver to enable usage on Tegra264 SoCs. The implementation parses the nvidia,cmdqv phandle from the SMMU device tree node to associate each SMMU with its corresponding CMDQV instance based on compatible string. Remove the dependency from Kconfig as the driver now supports both ACPI and device tree initialization through conditional compilation and ARM_SMMU_V3 depends on ARM64 which implies at least OF. Reviewed-by: Nicolin Chen Signed-off-by: Ashish Mhetre Suggested-by: Robin Murphy --- drivers/iommu/arm/Kconfig | 1 - drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 32 +++++++++++++++++++ .../iommu/arm/arm-smmu-v3/tegra241-cmdqv.c | 27 +++++++++++++++- 3 files changed, 58 insertions(+), 2 deletions(-) diff --git a/drivers/iommu/arm/Kconfig b/drivers/iommu/arm/Kconfig index ef42bbe07dbe..5fac08b89dee 100644 --- a/drivers/iommu/arm/Kconfig +++ b/drivers/iommu/arm/Kconfig @@ -121,7 +121,6 @@ config ARM_SMMU_V3_KUNIT_TEST =20 config TEGRA241_CMDQV bool "NVIDIA Tegra241 CMDQ-V extension support for ARM SMMUv3" - depends on ACPI help Support for NVIDIA CMDQ-Virtualization extension for ARM SMMUv3. The CMDQ-V extension is similar to v3.3 ECMDQ for multi command queues diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/ar= m/arm-smmu-v3/arm-smmu-v3.c index d16d35c78c06..9433cd91c68f 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -4530,6 +4530,35 @@ static int arm_smmu_device_hw_probe(struct arm_smmu_= device *smmu) return 0; } =20 +#ifdef CONFIG_TEGRA241_CMDQV +static void tegra_cmdqv_dt_probe(struct device_node *smmu_node, + struct arm_smmu_device *smmu) +{ + struct platform_device *pdev; + struct device_node *np; + + np =3D of_parse_phandle(smmu_node, "nvidia,cmdqv", 0); + if (!np) + return; + + pdev =3D of_find_device_by_node(np); + of_node_put(np); + if (!pdev) + return; + + smmu->impl_dev =3D &pdev->dev; + smmu->options |=3D ARM_SMMU_OPT_TEGRA241_CMDQV; + dev_info(smmu->dev, "found companion CMDQV device: %s\n", + dev_name(smmu->impl_dev)); + put_device(&pdev->dev); +} +#else +static void tegra_cmdqv_dt_probe(struct device_node *smmu_node, + struct arm_smmu_device *smmu) +{ +} +#endif + #ifdef CONFIG_ACPI #ifdef CONFIG_TEGRA241_CMDQV static void acpi_smmu_dsdt_probe_tegra241_cmdqv(struct acpi_iort_node *nod= e, @@ -4634,6 +4663,9 @@ static int arm_smmu_device_dt_probe(struct platform_d= evice *pdev, if (of_dma_is_coherent(dev->of_node)) smmu->features |=3D ARM_SMMU_FEAT_COHERENCY; =20 + if (of_device_is_compatible(dev->of_node, "nvidia,tegra264-smmu")) + tegra_cmdqv_dt_probe(dev->of_node, smmu); + return ret; } =20 diff --git a/drivers/iommu/arm/arm-smmu-v3/tegra241-cmdqv.c b/drivers/iommu= /arm/arm-smmu-v3/tegra241-cmdqv.c index 378104cd395e..c096c8229c5d 100644 --- a/drivers/iommu/arm/arm-smmu-v3/tegra241-cmdqv.c +++ b/drivers/iommu/arm/arm-smmu-v3/tegra241-cmdqv.c @@ -11,6 +11,8 @@ #include #include #include +#include +#include =20 #include =20 @@ -917,6 +919,26 @@ tegra241_cmdqv_find_acpi_resource(struct device *dev, = int *irq) return res; } =20 +static struct resource * +tegra241_cmdqv_find_dt_resource(struct device *dev, int *irq) +{ + struct platform_device *pdev =3D to_platform_device(dev); + struct resource *res; + + res =3D platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!res) { + dev_err(dev, "no memory resource found for CMDQV\n"); + return NULL; + } + + if (irq) + *irq =3D platform_get_irq_optional(pdev, 0); + if (!irq || *irq <=3D 0) + dev_warn(dev, "no interrupt. errors will not be reported\n"); + + return res; +} + static int tegra241_cmdqv_init_structures(struct arm_smmu_device *smmu) { struct tegra241_cmdqv *cmdqv =3D @@ -1048,11 +1070,14 @@ struct arm_smmu_device *tegra241_cmdqv_probe(struct= arm_smmu_device *smmu) =20 if (!smmu->dev->of_node) res =3D tegra241_cmdqv_find_acpi_resource(smmu->impl_dev, &irq); + else + res =3D tegra241_cmdqv_find_dt_resource(smmu->impl_dev, &irq); if (!res) goto out_fallback; =20 new_smmu =3D __tegra241_cmdqv_probe(smmu, res, irq); - kfree(res); + if (!smmu->dev->of_node) + kfree(res); =20 if (new_smmu) return new_smmu; --=20 2.25.1