From nobody Fri Dec 19 16:39:06 2025 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5F2E1398FB9 for ; Fri, 5 Dec 2025 06:34:09 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.61.82.184 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764916453; cv=none; b=kNWKmKurslWmZH2Wxigtq4hCCFVAlF4vM2bkjN7vGe1BMo9X9ti8kEFi2c60M5UDSMDyIwI2+5iL1QfN2/cVHx+nRDm71rTFOqphAYBnOeL0T5qRyKYzDeEX2OnWD/MUfHIos3PrVr/tEKPYf4eeEoOM7bZCVCqAMNz1yTRCqQw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764916453; c=relaxed/simple; bh=NdHOhxDB5X511h77TiK0y3+SbRf+3iHy43ELTPyc6yU=; h=From:To:CC:Subject:Date:Message-ID:MIME-Version:Content-Type; b=bstqa6o/+Vc1TL3ANGRo/w28LJ0adlN6yemYqxSb90zOS9TWnemRVS7Mor9AdBMRfH6KzdO9e5xOBJxIrTVRNQzimS2AYCzTOrUYv1prfCzDXfvfFEM+ds0ImyzqbDXm9SaC+mmhFS16Gs9zBFqamuaDTuaLBG8EOu71S8cjjS0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mediatek.com; spf=pass smtp.mailfrom=mediatek.com; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b=H3Wv+Obb; arc=none smtp.client-ip=210.61.82.184 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mediatek.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=mediatek.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="H3Wv+Obb" X-UUID: 629872a2d1a411f0b33aeb1e7f16c2b6-20251205 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:Content-Transfer-Encoding:MIME-Version:Message-ID:Date:Subject:CC:To:From; bh=6KEPQoelIaSRZixu2FcCj8GjygNUojPP6SBnzoaIaQY=; b=H3Wv+ObblLDqKZeXQixbULvCLrY4JTwiWjLZ8weIgu9Q3gZJYAQQAo3uweCUusVq2mIBVBLoeUU+5H/HSt5XNnRlFj33v/6OydGCK56YmBvkrx/w+UsmEQ7Xsk6SiOU13hLxPheCVzC9UhkDjoNZWlIlVjSoE3dYKVTpJbAG2pM=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.3.6,REQID:60f474b7-ae25-4e98-b000-4a34b4bdb1a8,IP:0,UR L:0,TC:0,Content:-25,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTION :release,TS:-25 X-CID-META: VersionHash:a9d874c,CLOUDID:fc002f28-e3a2-4f78-a442-8c73c4eb9e9d,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:102|836|888|898,TC:-5,Content:0|15|5 0,EDM:-3,IP:nil,URL:0,File:130,RT:0,Bulk:nil,QS:nil,BEC:nil,COL:0,OSI:0,OS A:0,AV:0,LES:1,SPR:NO,DKR:0,DKP:0,BRR:0,BRE:0,ARC:0 X-CID-BVR: 2,SSN|SDN X-CID-BAS: 2,SSN|SDN,0,_ X-CID-FACTOR: TF_CID_SPAM_SNR X-CID-RHF: D41D8CD98F00B204E9800998ECF8427E X-UUID: 629872a2d1a411f0b33aeb1e7f16c2b6-20251205 Received: from mtkmbs14n2.mediatek.inc [(172.21.101.76)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 888535751; Fri, 05 Dec 2025 14:34:00 +0800 Received: from mtkmbs13n2.mediatek.inc (172.21.101.108) by mtkmbs13n1.mediatek.inc (172.21.101.193) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.26; Fri, 5 Dec 2025 14:33:59 +0800 Received: from mhfsdcap04.gcn.mediatek.inc (10.17.3.154) by mtkmbs13n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1748.26 via Frontend Transport; Fri, 5 Dec 2025 14:33:58 +0800 From: Zexin Wang To: Philipp Zabel , Matthias Brugger , AngeloGioacchino Del Regno CC: , , , , Zexin Wang , Sirius Wang , Jack Hsu Subject: [PATCH] reset-controller: ti: introduce a new reset handler Date: Fri, 5 Dec 2025 14:33:54 +0800 Message-ID: <20251205063356.13515-1-ot_zexin.wang@mediatek.com> X-Mailer: git-send-email 2.46.0 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Introduce ti_syscon_reset() to integrate assert and deassert together. If some modules need do serialized assert and deassert operations to reset itself, reset_control_reset can be called for convenience. Signed-off-by: Zexin Wang --- drivers/reset/reset-ti-syscon.c | 34 +++++++++++++++++++++++++++++++++ 1 file changed, 34 insertions(+) diff --git a/drivers/reset/reset-ti-syscon.c b/drivers/reset/reset-ti-sysco= n.c index 23f86ddb8668..f37685e32b0a 100644 --- a/drivers/reset/reset-ti-syscon.c +++ b/drivers/reset/reset-ti-syscon.c @@ -7,6 +7,7 @@ * Suman Anna */ =20 +#include #include #include #include @@ -42,12 +43,14 @@ struct ti_syscon_reset_control { * @regmap: regmap handle containing the memory-mapped reset registers * @controls: array of reset controls * @nr_controls: number of controls in control array + * @reset_duration_us: time of controller assert reset */ struct ti_syscon_reset_data { struct reset_controller_dev rcdev; struct regmap *regmap; struct ti_syscon_reset_control *controls; unsigned int nr_controls; + unsigned int reset_duration_us; }; =20 #define to_ti_syscon_reset_data(_rcdev) \ @@ -150,9 +153,37 @@ static int ti_syscon_reset_status(struct reset_control= ler_dev *rcdev, !(control->flags & STATUS_SET); } =20 +/** + * ti_syscon_reset() - perform a full reset cycle on a device + * @rcdev: reset controller entity + * @id: ID of the reset to be asserted and deasserted + * + * This function performs a full reset cycle by asserting and then + * deasserting the reset signal for a device. It ensures the device + * is properly reset and ready for operation. + * + * Return: 0 for successful request, else a corresponding error value + */ +static int ti_syscon_reset(struct reset_controller_dev *rcdev, + unsigned long id) +{ + struct ti_syscon_reset_data *data =3D to_ti_syscon_reset_data(rcdev); + int ret; + + ret =3D ti_syscon_reset_assert(rcdev, id); + if (ret) + return ret; + + if (data->reset_duration_us) + usleep_range(data->reset_duration_us, data->reset_duration_us * 2); + + return ti_syscon_reset_deassert(rcdev, id); +} + static const struct reset_control_ops ti_syscon_reset_ops =3D { .assert =3D ti_syscon_reset_assert, .deassert =3D ti_syscon_reset_deassert, + .reset =3D ti_syscon_reset, .status =3D ti_syscon_reset_status, }; =20 @@ -196,6 +227,9 @@ static int ti_syscon_reset_probe(struct platform_device= *pdev) controls[i].flags =3D be32_to_cpup(list++); } =20 + of_property_read_u32(pdev->dev.of_node, "reset-duration-us", + &data->reset_duration_us); + data->rcdev.ops =3D &ti_syscon_reset_ops; data->rcdev.owner =3D THIS_MODULE; data->rcdev.of_node =3D np; --=20 2.45.2