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AJvYcCWTCtAF2VpTEURMonZxhsqzvFCLASffzuxlZWDjmF/VfinQuEmL+2UURj5k1zkXRBWbP/PzycICPYLyNzs=@vger.kernel.org X-Gm-Message-State: AOJu0YwnutItaFoMtstq6pnoVHbJbMcvov0acjdwhDv78sg2IXKVg6Gn M2jljxLwGFAbpBmX2kQxCGq81H6V/B2McE0mTCzqdAqVi8eO+GjiIgRfyhKd9j8sWfsSgCONNAA H1eNg1Pk2DnsvNKpaTy6d0x4Bu2bPrg== X-Google-Smtp-Source: AGHT+IEsCk2LyqVOkWJhdegH8mdf1hOi4A1iW6PlmwDrObjR3XVrHjRiwFEIsDfkYG5erGemrrr/fcN25Cehz6zSF6g= X-Received: from plpn23.prod.google.com ([2002:a17:902:9697:b0:295:1ab8:c43c]) (user=willmcvicker job=prod-delivery.src-stubby-dispatcher) by 2002:a17:902:e544:b0:28e:a70f:e879 with SMTP id d9443c01a7336-29d68339410mr94473405ad.1.1764897033869; Thu, 04 Dec 2025 17:10:33 -0800 (PST) Date: Fri, 5 Dec 2025 01:10:14 +0000 In-Reply-To: <20251205011027.720512-1-willmcvicker@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20251205011027.720512-1-willmcvicker@google.com> X-Mailer: git-send-email 2.52.0.223.gf5cc29aaa4-goog Message-ID: <20251205011027.720512-2-willmcvicker@google.com> Subject: [PATCH v7 1/6] clocksource/drivers/exynos_mct: Don't register as a sched_clock on arm64 From: Will McVicker To: Catalin Marinas , Will Deacon , Daniel Lezcano , Thomas Gleixner , Krzysztof Kozlowski , Alim Akhtar Cc: Will McVicker , Donghoon Yu , Rob Herring , John Stultz , Youngmin Nam , Peter Griffin , Tudor Ambarus , "=?UTF-8?q?Andr=C3=A9=20Draszik?=" , Conor Dooley , Marek Szyprowski , "Russell King (Oracle)" , linux-samsung-soc@vger.kernel.org, kernel-team@android.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Donghoon Yu The MCT register is unfortunately very slow to access, but importantly does not halt in the c2 idle state. So for ARM64, we can improve performance by not registering the MCT for sched_clock, allowing the system to use the faster ARM architected timer for sched_clock instead. The MCT is still registered as a clocksource, and a clockevent in order to be a wakeup source for the arch_timer to exit the "c2" idle state. Since ARM32 SoCs don't have an architected timer, the MCT must continue to be used for sched_clock. Detailed discussion on this topic can be found at [1]. [1] https://lore.kernel.org/linux-samsung-soc/1400188079-21832-1-git-send-e= mail-chirantan@chromium.org/ [Original commit from https://android.googlesource.com/kernel/gs/+/630817f7= 080e92c5e0216095ff52f6eb8dd00727 Signed-off-by: Donghoon Yu Signed-off-by: Youngmin Nam Signed-off-by: Daniel Lezcano Acked-by: John Stultz Tested-by: Youngmin Nam # AOSP -> Linux port Reviewed-by: Youngmin Nam # AOSP -> Linux port Signed-off-by: Will McVicker --- drivers/clocksource/exynos_mct.c | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/drivers/clocksource/exynos_mct.c b/drivers/clocksource/exynos_= mct.c index da09f467a6bb..96361d5dc57d 100644 --- a/drivers/clocksource/exynos_mct.c +++ b/drivers/clocksource/exynos_mct.c @@ -219,12 +219,18 @@ static struct clocksource mct_frc =3D { .resume =3D exynos4_frc_resume, }; =20 +/* + * Since ARM devices do not have an architected timer, they need to contin= ue + * using the MCT as the main clocksource for timekeeping, sched_clock, and= the + * delay timer. For AARCH64 SoCs, the architected timer is the preferred + * clocksource due to it's superior performance. + */ +#if defined(CONFIG_ARM) static u64 notrace exynos4_read_sched_clock(void) { return exynos4_read_count_32(); } =20 -#if defined(CONFIG_ARM) static struct delay_timer exynos4_delay_timer; =20 static cycles_t exynos4_read_current_timer(void) @@ -250,12 +256,13 @@ static int __init exynos4_clocksource_init(bool frc_s= hared) exynos4_delay_timer.read_current_timer =3D &exynos4_read_current_timer; exynos4_delay_timer.freq =3D clk_rate; register_current_timer_delay(&exynos4_delay_timer); + + sched_clock_register(exynos4_read_sched_clock, 32, clk_rate); #endif =20 if (clocksource_register_hz(&mct_frc, clk_rate)) panic("%s: can't register clocksource\n", mct_frc.name); =20 - sched_clock_register(exynos4_read_sched_clock, 32, clk_rate); =20 return 0; } --=20 2.52.0.223.gf5cc29aaa4-goog