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charset="utf-8" From: Donghoon Yu The MCT register is unfortunately very slow to access, but importantly does not halt in the c2 idle state. So for ARM64, we can improve performance by not registering the MCT for sched_clock, allowing the system to use the faster ARM architected timer for sched_clock instead. The MCT is still registered as a clocksource, and a clockevent in order to be a wakeup source for the arch_timer to exit the "c2" idle state. Since ARM32 SoCs don't have an architected timer, the MCT must continue to be used for sched_clock. Detailed discussion on this topic can be found at [1]. [1] https://lore.kernel.org/linux-samsung-soc/1400188079-21832-1-git-send-e= mail-chirantan@chromium.org/ [Original commit from https://android.googlesource.com/kernel/gs/+/630817f7= 080e92c5e0216095ff52f6eb8dd00727 Signed-off-by: Donghoon Yu Signed-off-by: Youngmin Nam Signed-off-by: Daniel Lezcano Acked-by: John Stultz Tested-by: Youngmin Nam # AOSP -> Linux port Reviewed-by: Youngmin Nam # AOSP -> Linux port Signed-off-by: Will McVicker Tested-by: Marek Szyprowski --- drivers/clocksource/exynos_mct.c | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/drivers/clocksource/exynos_mct.c b/drivers/clocksource/exynos_= mct.c index da09f467a6bb..96361d5dc57d 100644 --- a/drivers/clocksource/exynos_mct.c +++ b/drivers/clocksource/exynos_mct.c @@ -219,12 +219,18 @@ static struct clocksource mct_frc =3D { .resume =3D exynos4_frc_resume, }; =20 +/* + * Since ARM devices do not have an architected timer, they need to contin= ue + * using the MCT as the main clocksource for timekeeping, sched_clock, and= the + * delay timer. For AARCH64 SoCs, the architected timer is the preferred + * clocksource due to it's superior performance. + */ +#if defined(CONFIG_ARM) static u64 notrace exynos4_read_sched_clock(void) { return exynos4_read_count_32(); } =20 -#if defined(CONFIG_ARM) static struct delay_timer exynos4_delay_timer; =20 static cycles_t exynos4_read_current_timer(void) @@ -250,12 +256,13 @@ static int __init exynos4_clocksource_init(bool frc_s= hared) exynos4_delay_timer.read_current_timer =3D &exynos4_read_current_timer; exynos4_delay_timer.freq =3D clk_rate; register_current_timer_delay(&exynos4_delay_timer); + + sched_clock_register(exynos4_read_sched_clock, 32, clk_rate); #endif =20 if (clocksource_register_hz(&mct_frc, clk_rate)) panic("%s: can't register clocksource\n", mct_frc.name); =20 - sched_clock_register(exynos4_read_sched_clock, 32, clk_rate); =20 return 0; } --=20 2.52.0.223.gf5cc29aaa4-goog From nobody Wed Dec 17 08:50:08 2025 Received: from mail-pl1-f202.google.com (mail-pl1-f202.google.com [209.85.214.202]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 689E421576E for ; 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charset="utf-8" From: Hosung Kim To allow the CPU to handle it's own clock events, we need to set the IRQF_PERCPU flag. This prevents the local timer interrupts from migrating to other CPUs. This is only supported on ARM64. Signed-off-by: Hosung Kim [Original commit from https://android.googlesource.com/kernel/gs/+/03267fad= 19f093bac979ca78309483e9eb3a8d16] Reviewed-by: Peter Griffin Reviewed-by: Youngmin Nam Tested-by: Youngmin Nam Suggested-by: Marek Szyprowski Link: https://lore.kernel.org/all/20250827102645.1964659-1-m.szyprowski@sam= sung.com/ Signed-off-by: Will McVicker Tested-by: Marek Szyprowski --- drivers/clocksource/exynos_mct.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/clocksource/exynos_mct.c b/drivers/clocksource/exynos_= mct.c index 96361d5dc57d..1429b9d03a58 100644 --- a/drivers/clocksource/exynos_mct.c +++ b/drivers/clocksource/exynos_mct.c @@ -596,7 +596,9 @@ static int __init exynos4_timer_interrupts(struct devic= e_node *np, irq_set_status_flags(mct_irq, IRQ_NOAUTOEN); if (request_irq(mct_irq, exynos4_mct_tick_isr, - IRQF_TIMER | IRQF_NOBALANCING, + IRQF_TIMER | IRQF_NOBALANCING | + (IS_ENABLED(CONFIG_ARM64) ? + IRQF_PERCPU : 0), pcpu_mevt->name, pcpu_mevt)) { pr_err("exynos-mct: cannot register IRQ (cpu%d)\n", cpu); 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AJvYcCXJ6HXB1SrTZ1Nz0fdMmKB6zJBKlXfq4SVpCBxqEpcouDd0AvHaZFsJIuysAQz6/YqzV4KVT/RZKFvF03A=@vger.kernel.org X-Gm-Message-State: AOJu0Yzr3c5djfHZ1UZXdhdQnhY8y3Xq+L/rBBkxW6k8gT9yhXlxOpVW T0Zwm1IbUDGnLNdSZaeOyro8GqtaPnu5MUopMQhhFJ0G0RGp5m0UbrC7vIrJdQliJ9Vz6EIBCCq Hl6TPQd4wJdoKSzDbozQIOB2Jm09LXg== X-Google-Smtp-Source: AGHT+IH9KMxSRQ5wVKmte0Bi3CRERC2XxJgetiRnkGTJBGEVXsPWpng07cULyLreEjs12GMrzr3xnVDBBaYvIjN3EJY= X-Received: from pjbsd5.prod.google.com ([2002:a17:90b:5145:b0:33b:52d6:e13e]) (user=willmcvicker job=prod-delivery.src-stubby-dispatcher) by 2002:a17:90b:5444:b0:343:7714:4cab with SMTP id 98e67ed59e1d1-34947f07f1fmr4183700a91.22.1764897037891; Thu, 04 Dec 2025 17:10:37 -0800 (PST) Date: Fri, 5 Dec 2025 01:10:16 +0000 In-Reply-To: <20251205011027.720512-1-willmcvicker@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20251205011027.720512-1-willmcvicker@google.com> X-Mailer: git-send-email 2.52.0.223.gf5cc29aaa4-goog Message-ID: <20251205011027.720512-4-willmcvicker@google.com> Subject: [PATCH v7 3/6] clocksource/drivers/exynos_mct: Fix uninitialized irq name warning From: Will McVicker To: Catalin Marinas , Will Deacon , Daniel Lezcano , Thomas Gleixner , Krzysztof Kozlowski , Alim Akhtar Cc: Will McVicker , Donghoon Yu , Rob Herring , John Stultz , Youngmin Nam , Peter Griffin , Tudor Ambarus , "=?UTF-8?q?Andr=C3=A9=20Draszik?=" , Conor Dooley , Marek Szyprowski , "Russell King (Oracle)" , linux-samsung-soc@vger.kernel.org, kernel-team@android.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The Exynos MCT driver doesn't set the clocksource name until the CPU hotplug state is setup which happens after the IRQs are requested. This results in an empty IRQ name which leads to the below warning at proc_create() time. When this happens, the userdata partition fails to mount and the device gets stuck in an endless loop printing the error: root '/dev/disk/by-partlabel/userdata' doesn't exist or does not contain = a /dev. To fix this, we just need to initialize the name before requesting the IRQs. Warning from Pixel 6 kernel log: [ T430] name len 0 [ T430] WARNING: CPU: 6 PID: 430 at fs/proc/generic.c:407 __proc_create+0x= 258/0x2b4 [ T430] Modules linked in: dwc3_exynos(E+) [ T430] ufs_exynos(E+) phy_exynos_ufs(E) [ T430] phy_exynos5_usbdrd(E) exynos_usi(E+) exynos_mct(E+) s3c2410_wdt(E) [ T430] arm_dsu_pmu(E) simplefb(E) [ T430] CPU: 6 UID: 0 PID: 430 Comm: (udev-worker) Tainted: ... 6.14.0-next-20250331-4k-00008-g59adf909e40e #1 ... [ T430] Tainted: [W]=3DWARN, [E]=3DUNSIGNED_MODULE [ T430] Hardware name: Raven (DT) [...] [ T430] Call trace: [ T430] __proc_create+0x258/0x2b4 (P) [ T430] proc_mkdir+0x40/0xa0 [ T430] register_handler_proc+0x118/0x140 [ T430] __setup_irq+0x460/0x6d0 [ T430] request_threaded_irq+0xcc/0x1b0 [ T430] mct_init_dt+0x244/0x604 [exynos_mct ...] [ T430] mct_init_spi+0x18/0x34 [exynos_mct ...] [ T430] exynos4_mct_probe+0x30/0x4c [exynos_mct ...] [ T430] platform_probe+0x6c/0xe4 [ T430] really_probe+0xf4/0x38c [...] [ T430] driver_register+0x6c/0x140 [ T430] __platform_driver_register+0x28/0x38 [ T430] exynos4_mct_driver_init+0x24/0xfe8 [exynos_mct ...] [ T430] do_one_initcall+0x84/0x3c0 [ T430] do_init_module+0x58/0x208 [ T430] load_module+0x1de0/0x2500 [ T430] init_module_from_file+0x8c/0xdc Reviewed-by: Peter Griffin Reviewed-by: Youngmin Nam Tested-by: Youngmin Nam Signed-off-by: Will McVicker Tested-by: Marek Szyprowski --- drivers/clocksource/exynos_mct.c | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/drivers/clocksource/exynos_mct.c b/drivers/clocksource/exynos_= mct.c index 1429b9d03a58..fece6bbc190e 100644 --- a/drivers/clocksource/exynos_mct.c +++ b/drivers/clocksource/exynos_mct.c @@ -465,8 +465,6 @@ static int exynos4_mct_starting_cpu(unsigned int cpu) per_cpu_ptr(&percpu_mct_tick, cpu); struct clock_event_device *evt =3D &mevt->evt; =20 - snprintf(mevt->name, sizeof(mevt->name), "mct_tick%d", cpu); - evt->name =3D mevt->name; evt->cpumask =3D cpumask_of(cpu); evt->set_next_event =3D exynos4_tick_set_next_event; @@ -567,6 +565,14 @@ static int __init exynos4_timer_interrupts(struct devi= ce_node *np, for (i =3D MCT_L0_IRQ; i < nr_irqs; i++) mct_irqs[i] =3D irq_of_parse_and_map(np, i); =20 + for_each_possible_cpu(cpu) { + struct mct_clock_event_device *mevt =3D + per_cpu_ptr(&percpu_mct_tick, cpu); + + snprintf(mevt->name, sizeof(mevt->name), "mct_tick%d", + cpu); + } + if (mct_int_type =3D=3D MCT_INT_PPI) { =20 err =3D request_percpu_irq(mct_irqs[MCT_L0_IRQ], --=20 2.52.0.223.gf5cc29aaa4-goog From nobody Wed Dec 17 08:50:08 2025 Received: from mail-pg1-f201.google.com (mail-pg1-f201.google.com [209.85.215.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 65E3C217722 for ; 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Thu, 04 Dec 2025 17:10:40 -0800 (PST) Date: Fri, 5 Dec 2025 01:10:17 +0000 In-Reply-To: <20251205011027.720512-1-willmcvicker@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20251205011027.720512-1-willmcvicker@google.com> X-Mailer: git-send-email 2.52.0.223.gf5cc29aaa4-goog Message-ID: <20251205011027.720512-5-willmcvicker@google.com> Subject: [PATCH v7 4/6] clocksource/drivers/exynos_mct: Refactor driver init From: Will McVicker To: Catalin Marinas , Will Deacon , Daniel Lezcano , Thomas Gleixner , Krzysztof Kozlowski , Alim Akhtar Cc: Will McVicker , Donghoon Yu , Rob Herring , John Stultz , Youngmin Nam , Peter Griffin , Tudor Ambarus , "=?UTF-8?q?Andr=C3=A9=20Draszik?=" , Conor Dooley , Marek Szyprowski , "Russell King (Oracle)" , linux-samsung-soc@vger.kernel.org, kernel-team@android.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" This patch cleans up the driver a bit by - refactoring mct_init_dt() to allow better separation of ARM 32-bit specific code and ARM64 code. Ultimately this allows the driver to access context data outside of mct_init_dt(). - adds driver data to distinguish the interrupt type which allows a single driver init function. This clean up is in preparation for modularizing the MCT driver for only ARM64 SoCs. Signed-off-by: Will McVicker Tested-by: Marek Szyprowski --- drivers/clocksource/exynos_mct.c | 199 +++++++++++++++++++------------ 1 file changed, 125 insertions(+), 74 deletions(-) diff --git a/drivers/clocksource/exynos_mct.c b/drivers/clocksource/exynos_= mct.c index fece6bbc190e..922c2b519a39 100644 --- a/drivers/clocksource/exynos_mct.c +++ b/drivers/clocksource/exynos_mct.c @@ -74,13 +74,22 @@ enum { MCT_INT_PPI }; =20 +/* Needs to be global for sched_clock_register() since we can't pass in da= ta. */ static void __iomem *reg_base; -static unsigned long clk_rate; -static unsigned int mct_int_type; -static int mct_irqs[MCT_NR_IRQS]; + +struct mct_data { + unsigned int int_type; +}; + +struct mct_context { + const struct mct_data *drvdata; + unsigned long clk_rate; + int mct_irqs[MCT_NR_IRQS]; +}; =20 struct mct_clock_event_device { struct clock_event_device evt; + struct mct_context *ctx; unsigned long base; /** * The length of the name must be adjusted if number of @@ -89,6 +98,12 @@ struct mct_clock_event_device { char name[11]; }; =20 +static struct mct_clock_event_device * +to_mct_clock_event_device(struct clock_event_device *evt) +{ + return container_of(evt, struct mct_clock_event_device, evt); +} + static void exynos4_mct_write(unsigned int value, unsigned long offset) { unsigned long stat_addr; @@ -241,7 +256,7 @@ static cycles_t exynos4_read_current_timer(void) } #endif =20 -static int __init exynos4_clocksource_init(bool frc_shared) +static int __init exynos4_clocksource_init(struct mct_context *ctx, bool f= rc_shared) { /* * When the frc is shared, the main processor should have already @@ -252,18 +267,9 @@ static int __init exynos4_clocksource_init(bool frc_sh= ared) else exynos4_mct_frc_start(); =20 -#if defined(CONFIG_ARM) - exynos4_delay_timer.read_current_timer =3D &exynos4_read_current_timer; - exynos4_delay_timer.freq =3D clk_rate; - register_current_timer_delay(&exynos4_delay_timer); - - sched_clock_register(exynos4_read_sched_clock, 32, clk_rate); -#endif - - if (clocksource_register_hz(&mct_frc, clk_rate)) + if (clocksource_register_hz(&mct_frc, ctx->clk_rate)) panic("%s: can't register clocksource\n", mct_frc.name); =20 - return 0; } =20 @@ -297,7 +303,7 @@ static void exynos4_mct_comp0_start(bool periodic, unsi= gned long cycles) exynos4_mct_write(0x1, EXYNOS4_MCT_G_INT_ENB); =20 tcon |=3D MCT_G_TCON_COMP0_ENABLE; - exynos4_mct_write(tcon , EXYNOS4_MCT_G_TCON); + exynos4_mct_write(tcon, EXYNOS4_MCT_G_TCON); } =20 static int exynos4_comp_set_next_event(unsigned long cycles, @@ -325,17 +331,19 @@ static int mct_set_state_periodic(struct clock_event_= device *evt) return 0; } =20 -static struct clock_event_device mct_comp_device =3D { - .name =3D "mct-comp", - .features =3D CLOCK_EVT_FEAT_PERIODIC | - CLOCK_EVT_FEAT_ONESHOT, - .rating =3D 250, - .set_next_event =3D exynos4_comp_set_next_event, - .set_state_periodic =3D mct_set_state_periodic, - .set_state_shutdown =3D mct_set_state_shutdown, - .set_state_oneshot =3D mct_set_state_shutdown, - .set_state_oneshot_stopped =3D mct_set_state_shutdown, - .tick_resume =3D mct_set_state_shutdown, +static struct mct_clock_event_device mct_comp_device =3D { + .evt =3D { + .name =3D "mct-comp", + .features =3D CLOCK_EVT_FEAT_PERIODIC | + CLOCK_EVT_FEAT_ONESHOT, + .rating =3D 250, + .set_next_event =3D exynos4_comp_set_next_event, + .set_state_periodic =3D mct_set_state_periodic, + .set_state_shutdown =3D mct_set_state_shutdown, + .set_state_oneshot =3D mct_set_state_shutdown, + .set_state_oneshot_stopped =3D mct_set_state_shutdown, + .tick_resume =3D mct_set_state_shutdown, + }, }; =20 static irqreturn_t exynos4_mct_comp_isr(int irq, void *dev_id) @@ -349,14 +357,16 @@ static irqreturn_t exynos4_mct_comp_isr(int irq, void= *dev_id) return IRQ_HANDLED; } =20 -static int exynos4_clockevent_init(void) +static int exynos4_clockevent_init(struct mct_context *ctx) { - mct_comp_device.cpumask =3D cpumask_of(0); - clockevents_config_and_register(&mct_comp_device, clk_rate, + struct clock_event_device *evt =3D &mct_comp_device.evt; + + mct_comp_device.ctx =3D ctx; + evt->cpumask =3D cpumask_of(0); + clockevents_config_and_register(evt, ctx->clk_rate, 0xf, 0xffffffff); - if (request_irq(mct_irqs[MCT_G0_IRQ], exynos4_mct_comp_isr, - IRQF_TIMER | IRQF_IRQPOLL, "mct_comp_irq", - &mct_comp_device)) + if (request_irq(ctx->mct_irqs[MCT_G0_IRQ], exynos4_mct_comp_isr, + IRQF_TIMER | IRQF_IRQPOLL, "mct_comp_irq", evt)) pr_err("%s: request_irq() failed\n", "mct_comp_irq"); =20 return 0; @@ -409,18 +419,16 @@ static void exynos4_mct_tick_clear(struct mct_clock_e= vent_device *mevt) static int exynos4_tick_set_next_event(unsigned long cycles, struct clock_event_device *evt) { - struct mct_clock_event_device *mevt; + struct mct_clock_event_device *mevt =3D to_mct_clock_event_device(evt); =20 - mevt =3D container_of(evt, struct mct_clock_event_device, evt); exynos4_mct_tick_start(cycles, mevt); return 0; } =20 static int set_state_shutdown(struct clock_event_device *evt) { - struct mct_clock_event_device *mevt; + struct mct_clock_event_device *mevt =3D to_mct_clock_event_device(evt); =20 - mevt =3D container_of(evt, struct mct_clock_event_device, evt); exynos4_mct_tick_stop(mevt); exynos4_mct_tick_clear(mevt); return 0; @@ -428,10 +436,9 @@ static int set_state_shutdown(struct clock_event_devic= e *evt) =20 static int set_state_periodic(struct clock_event_device *evt) { - struct mct_clock_event_device *mevt; + struct mct_clock_event_device *mevt =3D to_mct_clock_event_device(evt); unsigned long cycles_per_jiffy; =20 - mevt =3D container_of(evt, struct mct_clock_event_device, evt); cycles_per_jiffy =3D (((unsigned long long)NSEC_PER_SEC / HZ * evt->mult) >> evt->shift); exynos4_mct_tick_stop(mevt); @@ -464,6 +471,7 @@ static int exynos4_mct_starting_cpu(unsigned int cpu) struct mct_clock_event_device *mevt =3D per_cpu_ptr(&percpu_mct_tick, cpu); struct clock_event_device *evt =3D &mevt->evt; + struct mct_context *ctx =3D mevt->ctx; =20 evt->name =3D mevt->name; evt->cpumask =3D cpumask_of(cpu); @@ -479,7 +487,7 @@ static int exynos4_mct_starting_cpu(unsigned int cpu) =20 exynos4_mct_write(TICK_BASE_CNT, mevt->base + MCT_L_TCNTB_OFFSET); =20 - if (mct_int_type =3D=3D MCT_INT_SPI) { + if (ctx->drvdata->int_type =3D=3D MCT_INT_SPI) { =20 if (evt->irq =3D=3D -1) return -EIO; @@ -487,9 +495,9 @@ static int exynos4_mct_starting_cpu(unsigned int cpu) irq_force_affinity(evt->irq, cpumask_of(cpu)); enable_irq(evt->irq); } else { - enable_percpu_irq(mct_irqs[MCT_L0_IRQ], 0); + enable_percpu_irq(ctx->mct_irqs[MCT_L0_IRQ], 0); } - clockevents_config_and_register(evt, clk_rate / (TICK_BASE_CNT + 1), + clockevents_config_and_register(evt, ctx->clk_rate / (TICK_BASE_CNT + 1), 0xf, 0x7fffffff); =20 return 0; @@ -500,18 +508,20 @@ static int exynos4_mct_dying_cpu(unsigned int cpu) struct mct_clock_event_device *mevt =3D per_cpu_ptr(&percpu_mct_tick, cpu); struct clock_event_device *evt =3D &mevt->evt; + struct mct_context *ctx =3D mevt->ctx; =20 - if (mct_int_type =3D=3D MCT_INT_SPI) { + if (ctx->drvdata->int_type =3D=3D MCT_INT_SPI) { if (evt->irq !=3D -1) disable_irq_nosync(evt->irq); exynos4_mct_write(0x1, mevt->base + MCT_L_INT_CSTAT_OFFSET); } else { - disable_percpu_irq(mct_irqs[MCT_L0_IRQ]); + disable_percpu_irq(ctx->mct_irqs[MCT_L0_IRQ]); } return 0; } =20 -static int __init exynos4_timer_resources(struct device_node *np) +static int __init exynos4_timer_resources(struct mct_context *ctx, + struct device_node *np) { struct clk *mct_clk, *tick_clk; =20 @@ -522,7 +532,7 @@ static int __init exynos4_timer_resources(struct device= _node *np) tick_clk =3D of_clk_get_by_name(np, "fin_pll"); if (IS_ERR(tick_clk)) panic("%s: unable to determine tick clock rate\n", __func__); - clk_rate =3D clk_get_rate(tick_clk); + ctx->clk_rate =3D clk_get_rate(tick_clk); =20 mct_clk =3D of_clk_get_by_name(np, "mct"); if (IS_ERR(mct_clk)) @@ -534,22 +544,20 @@ static int __init exynos4_timer_resources(struct devi= ce_node *np) =20 /** * exynos4_timer_interrupts - initialize MCT interrupts + * @ctx: device context * @np: device node for MCT - * @int_type: interrupt type, MCT_INT_PPI or MCT_INT_SPI * @local_idx: array mapping CPU numbers to local timer indices * @nr_local: size of @local_idx array */ -static int __init exynos4_timer_interrupts(struct device_node *np, - unsigned int int_type, +static int __init exynos4_timer_interrupts(struct mct_context *ctx, + struct device_node *np, const u32 *local_idx, size_t nr_local) { int nr_irqs, i, err, cpu; =20 - mct_int_type =3D int_type; - /* This driver uses only one global timer interrupt */ - mct_irqs[MCT_G0_IRQ] =3D irq_of_parse_and_map(np, MCT_G0_IRQ); + ctx->mct_irqs[MCT_G0_IRQ] =3D irq_of_parse_and_map(np, MCT_G0_IRQ); =20 /* * Find out the number of local irqs specified. The local @@ -557,29 +565,30 @@ static int __init exynos4_timer_interrupts(struct dev= ice_node *np, * irqs are specified. */ nr_irqs =3D of_irq_count(np); - if (nr_irqs > ARRAY_SIZE(mct_irqs)) { + if (nr_irqs > ARRAY_SIZE(ctx->mct_irqs)) { pr_err("exynos-mct: too many (%d) interrupts configured in DT\n", nr_irqs); - nr_irqs =3D ARRAY_SIZE(mct_irqs); + nr_irqs =3D ARRAY_SIZE(ctx->mct_irqs); } for (i =3D MCT_L0_IRQ; i < nr_irqs; i++) - mct_irqs[i] =3D irq_of_parse_and_map(np, i); + ctx->mct_irqs[i] =3D irq_of_parse_and_map(np, i); =20 for_each_possible_cpu(cpu) { struct mct_clock_event_device *mevt =3D per_cpu_ptr(&percpu_mct_tick, cpu); =20 + mevt->ctx =3D ctx; snprintf(mevt->name, sizeof(mevt->name), "mct_tick%d", cpu); } =20 - if (mct_int_type =3D=3D MCT_INT_PPI) { + if (ctx->drvdata->int_type =3D=3D MCT_INT_PPI) { =20 - err =3D request_percpu_irq(mct_irqs[MCT_L0_IRQ], + err =3D request_percpu_irq(ctx->mct_irqs[MCT_L0_IRQ], exynos4_mct_tick_isr, "MCT", &percpu_mct_tick); WARN(err, "MCT: can't request IRQ %d (%d)\n", - mct_irqs[MCT_L0_IRQ], err); + ctx->mct_irqs[MCT_L0_IRQ], err); } else { for_each_possible_cpu(cpu) { int mct_irq; @@ -595,9 +604,9 @@ static int __init exynos4_timer_interrupts(struct devic= e_node *np, irq_idx =3D MCT_L0_IRQ + local_idx[cpu]; =20 pcpu_mevt->evt.irq =3D -1; - if (irq_idx >=3D ARRAY_SIZE(mct_irqs)) + if (irq_idx >=3D ARRAY_SIZE(ctx->mct_irqs)) break; - mct_irq =3D mct_irqs[irq_idx]; + mct_irq =3D ctx->mct_irqs[irq_idx]; =20 irq_set_status_flags(mct_irq, IRQ_NOAUTOEN); if (request_irq(mct_irq, @@ -637,8 +646,8 @@ static int __init exynos4_timer_interrupts(struct devic= e_node *np, return 0; =20 out_irq: - if (mct_int_type =3D=3D MCT_INT_PPI) { - free_percpu_irq(mct_irqs[MCT_L0_IRQ], &percpu_mct_tick); + if (ctx->drvdata->int_type =3D=3D MCT_INT_PPI) { + free_percpu_irq(ctx->mct_irqs[MCT_L0_IRQ], &percpu_mct_tick); } else { for_each_possible_cpu(cpu) { struct mct_clock_event_device *pcpu_mevt =3D @@ -653,7 +662,7 @@ static int __init exynos4_timer_interrupts(struct devic= e_node *np, return err; } =20 -static int __init mct_init_dt(struct device_node *np, unsigned int int_typ= e) +static int __init mct_init_dt(struct mct_context *ctx, struct device_node = *np) { bool frc_shared =3D of_property_read_bool(np, "samsung,frc-shared"); u32 local_idx[MCT_NR_LOCAL] =3D {0}; @@ -679,15 +688,15 @@ static int __init mct_init_dt(struct device_node *np,= unsigned int int_type) local_idx[i] =3D i; } =20 - ret =3D exynos4_timer_resources(np); + ret =3D exynos4_timer_resources(ctx, np); if (ret) return ret; =20 - ret =3D exynos4_timer_interrupts(np, int_type, local_idx, nr_local); + ret =3D exynos4_timer_interrupts(ctx, np, local_idx, nr_local); if (ret) return ret; =20 - ret =3D exynos4_clocksource_init(frc_shared); + ret =3D exynos4_clocksource_init(ctx, frc_shared); if (ret) return ret; =20 @@ -698,18 +707,60 @@ static int __init mct_init_dt(struct device_node *np,= unsigned int int_type) if (frc_shared) return 0; =20 - return exynos4_clockevent_init(); + ret =3D exynos4_clockevent_init(ctx); + if (ret) + return ret; + + return 0; } =20 +static const struct mct_data exynos4210_mct_data =3D { .int_type =3D MCT_I= NT_SPI, }; +static const struct mct_data exynos4412_mct_data =3D { .int_type =3D MCT_I= NT_PPI, }; =20 -static int __init mct_init_spi(struct device_node *np) -{ - return mct_init_dt(np, MCT_INT_SPI); -} +static const struct of_device_id exynos4_mct_match_table[] =3D { + { .compatible =3D "samsung,exynos4210-mct", .data =3D &exynos4210_mct_dat= a, }, + { .compatible =3D "samsung,exynos4412-mct", .data =3D &exynos4412_mct_dat= a, }, + {} +}; =20 -static int __init mct_init_ppi(struct device_node *np) +/* Note, legacy ARM 32-bit systems depend on the MCT as the only clocksour= ce + * which requires this driver to be initialized very early. We need to kee= p this + * special condition until we can transparently support modular and early = init + * timers. + */ +static int __init mct_of_declare_init(struct device_node *np) { - return mct_init_dt(np, MCT_INT_PPI); + struct mct_context *ctx; + const struct of_device_id *match; + int ret; + + match =3D of_match_node(exynos4_mct_match_table, np); + if (!match || !match->data) + return -ENODEV; + + ctx =3D kzalloc(sizeof(*ctx), GFP_KERNEL); + if (!ctx) + return -ENOMEM; + + ctx->drvdata =3D match->data; + + ret =3D mct_init_dt(ctx, np); + if (ret) + goto out_ctx; + +#if defined(CONFIG_ARM) + sched_clock_register(exynos4_read_sched_clock, 32, ctx->clk_rate); + + exynos4_delay_timer.read_current_timer =3D &exynos4_read_current_timer; + exynos4_delay_timer.freq =3D ctx->clk_rate; + register_current_timer_delay(&exynos4_delay_timer); +#endif + + return 0; + +out_ctx: + kfree(ctx); + return ret; } -TIMER_OF_DECLARE(exynos4210, "samsung,exynos4210-mct", mct_init_spi); -TIMER_OF_DECLARE(exynos4412, "samsung,exynos4412-mct", mct_init_ppi); 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charset="utf-8" On Arm64 platforms the Exynos MCT driver can be built as a module. On boot (and even after boot) the arch_timer is used as the clocksource and tick timer. Once the MCT driver is loaded, it can be used as the wakeup source for the arch_timer. Note, this commit was derived from https://android.googlesource.com/kernel/gs/+/8a52a8288ec7d88ff78f0b37480dbb= 0e9c65bbfd. Signed-off-by: Daniel Lezcano Reviewed-by: Youngmin Nam # AOSP -> Linux port Tested-by: Youngmin Nam # AOSP -> Linux port Signed-off-by: Will McVicker Tested-by: Marek Szyprowski --- drivers/clocksource/Kconfig | 3 +- drivers/clocksource/exynos_mct.c | 51 ++++++++++++++++++++++++++++---- 2 files changed, 47 insertions(+), 7 deletions(-) diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig index ffcd23668763..9450cfaf982f 100644 --- a/drivers/clocksource/Kconfig +++ b/drivers/clocksource/Kconfig @@ -451,7 +451,8 @@ config ATMEL_TCB_CLKSRC Support for Timer Counter Blocks on Atmel SoCs. =20 config CLKSRC_EXYNOS_MCT - bool "Exynos multi core timer driver" if COMPILE_TEST + tristate "Exynos multi core timer driver" if ARM64 + default y if ARCH_EXYNOS || COMPILE_TEST depends on ARM || ARM64 depends on ARCH_ARTPEC || ARCH_EXYNOS || COMPILE_TEST help diff --git a/drivers/clocksource/exynos_mct.c b/drivers/clocksource/exynos_= mct.c index 922c2b519a39..d9a888607726 100644 --- a/drivers/clocksource/exynos_mct.c +++ b/drivers/clocksource/exynos_mct.c @@ -15,9 +15,11 @@ #include #include #include +#include #include #include #include +#include #include #include =20 @@ -232,6 +234,7 @@ static struct clocksource mct_frc =3D { .mask =3D CLOCKSOURCE_MASK(32), .flags =3D CLOCK_SOURCE_IS_CONTINUOUS, .resume =3D exynos4_frc_resume, + .owner =3D THIS_MODULE, }; =20 /* @@ -256,7 +259,7 @@ static cycles_t exynos4_read_current_timer(void) } #endif =20 -static int __init exynos4_clocksource_init(struct mct_context *ctx, bool f= rc_shared) +static int __init_or_module exynos4_clocksource_init(struct mct_context *c= tx, bool frc_shared) { /* * When the frc is shared, the main processor should have already @@ -343,6 +346,7 @@ static struct mct_clock_event_device mct_comp_device = =3D { .set_state_oneshot =3D mct_set_state_shutdown, .set_state_oneshot_stopped =3D mct_set_state_shutdown, .tick_resume =3D mct_set_state_shutdown, + .owner =3D THIS_MODULE, }, }; =20 @@ -484,6 +488,7 @@ static int exynos4_mct_starting_cpu(unsigned int cpu) evt->features =3D CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_PERCPU; evt->rating =3D MCT_CLKEVENTS_RATING; + evt->owner =3D THIS_MODULE; =20 exynos4_mct_write(TICK_BASE_CNT, mevt->base + MCT_L_TCNTB_OFFSET); =20 @@ -520,7 +525,7 @@ static int exynos4_mct_dying_cpu(unsigned int cpu) return 0; } =20 -static int __init exynos4_timer_resources(struct mct_context *ctx, +static int __init_or_module exynos4_timer_resources(struct mct_context *ct= x, struct device_node *np) { struct clk *mct_clk, *tick_clk; @@ -549,7 +554,7 @@ static int __init exynos4_timer_resources(struct mct_co= ntext *ctx, * @local_idx: array mapping CPU numbers to local timer indices * @nr_local: size of @local_idx array */ -static int __init exynos4_timer_interrupts(struct mct_context *ctx, +static int __init_or_module exynos4_timer_interrupts(struct mct_context *c= tx, struct device_node *np, const u32 *local_idx, size_t nr_local) @@ -662,7 +667,7 @@ static int __init exynos4_timer_interrupts(struct mct_c= ontext *ctx, return err; } =20 -static int __init mct_init_dt(struct mct_context *ctx, struct device_node = *np) +static int __init_or_module mct_init_dt(struct mct_context *ctx, struct de= vice_node *np) { bool frc_shared =3D of_property_read_bool(np, "samsung,frc-shared"); u32 local_idx[MCT_NR_LOCAL] =3D {0}; @@ -722,7 +727,9 @@ static const struct of_device_id exynos4_mct_match_tabl= e[] =3D { { .compatible =3D "samsung,exynos4412-mct", .data =3D &exynos4412_mct_dat= a, }, {} }; +MODULE_DEVICE_TABLE(of, exynos4_mct_match_table); =20 +#if defined(CONFIG_ARM) /* Note, legacy ARM 32-bit systems depend on the MCT as the only clocksour= ce * which requires this driver to be initialized very early. We need to kee= p this * special condition until we can transparently support modular and early = init @@ -748,13 +755,11 @@ static int __init mct_of_declare_init(struct device_n= ode *np) if (ret) goto out_ctx; =20 -#if defined(CONFIG_ARM) sched_clock_register(exynos4_read_sched_clock, 32, ctx->clk_rate); =20 exynos4_delay_timer.read_current_timer =3D &exynos4_read_current_timer; exynos4_delay_timer.freq =3D ctx->clk_rate; register_current_timer_delay(&exynos4_delay_timer); -#endif =20 return 0; =20 @@ -764,3 +769,37 @@ static int __init mct_of_declare_init(struct device_no= de *np) } TIMER_OF_DECLARE(exynos4210, "samsung,exynos4210-mct", mct_of_declare_init= ); TIMER_OF_DECLARE(exynos4412, "samsung,exynos4412-mct", mct_of_declare_init= ); +#else +static int exynos4_mct_probe(struct platform_device *pdev) +{ + struct mct_context *ctx; + struct device *dev =3D &pdev->dev; + + ctx =3D devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL); + if (!ctx) + return -ENOMEM; + + ctx->drvdata =3D of_device_get_match_data(dev); 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Thu, 04 Dec 2025 17:10:44 -0800 (PST) Date: Fri, 5 Dec 2025 01:10:19 +0000 In-Reply-To: <20251205011027.720512-1-willmcvicker@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20251205011027.720512-1-willmcvicker@google.com> X-Mailer: git-send-email 2.52.0.223.gf5cc29aaa4-goog Message-ID: <20251205011027.720512-7-willmcvicker@google.com> Subject: [PATCH v7 6/6] arm64: exynos: Drop select CLKSRC_EXYNOS_MCT From: Will McVicker To: Catalin Marinas , Will Deacon , Daniel Lezcano , Thomas Gleixner , Krzysztof Kozlowski , Alim Akhtar Cc: Will McVicker , Donghoon Yu , Rob Herring , John Stultz , Youngmin Nam , Peter Griffin , Tudor Ambarus , "=?UTF-8?q?Andr=C3=A9=20Draszik?=" , Conor Dooley , Marek Szyprowski , "Russell King (Oracle)" , linux-samsung-soc@vger.kernel.org, kernel-team@android.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Since the Exynos MCT driver can be built as a module for some Arm64 SoCs like gs101, drop force-selecting it as a built-in driver by ARCH_EXYNOS and instead depend on `default y if ARCH_EXYNOS` to select it automatically. This allows platforms like Android to build the driver as a module if desired. Reviewed-by: Youngmin Nam Tested-by: Youngmin Nam Signed-off-by: Will McVicker Tested-by: Marek Szyprowski --- arch/arm64/Kconfig.platforms | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms index 13173795c43d..fc6026c368ca 100644 --- a/arch/arm64/Kconfig.platforms +++ b/arch/arm64/Kconfig.platforms @@ -128,7 +128,6 @@ config ARCH_CIX config ARCH_EXYNOS bool "Samsung Exynos SoC family" select COMMON_CLK_SAMSUNG - select CLKSRC_EXYNOS_MCT select EXYNOS_PM_DOMAINS if PM_GENERIC_DOMAINS select EXYNOS_PMU select PINCTRL --=20 2.52.0.223.gf5cc29aaa4-goog