From nobody Tue Dec 16 15:10:06 2025 Received: from smtpout-03.galae.net (smtpout-03.galae.net [185.246.85.4]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 306B231AAB8; Fri, 5 Dec 2025 19:39:52 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.246.85.4 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764963595; cv=none; b=rfSyCCENq11xIujBDXa15ZjrMgcXgYWtgtFBC4s1d+BySIBZx7Ag1BP7oAe0DupBlhgu3QYWdLYMtVIx/Fk7G/TbtKSmiHM7kC4UDXuV7x3oMNT4VHVi+bcA4H0TMNpobg6LfSJyhmvpIYTsNQqAdqfFts3KZ5DAzZBBeX01tTk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764963595; c=relaxed/simple; bh=8MfZrxm+61/f0kdvvZFpnJWPO1aniiNrAmuo+gmtrlM=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=F16XXhkJJgI+lUqZXqRT+Zil2xeyN7jmAGh8VAsdu8YH91QK19gkY6jjyTt8wQ1zi35fLOkAZoX0hhjuMGjGvhAwaz5sYngYz/7LevY3rQUsUtNCnuRDqCyGq33nd2njSLmmdo7i2NPlV2BtRqeqeR3YKLyLPfUBgGEa8mZHBy8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com; spf=pass smtp.mailfrom=bootlin.com; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b=nSdCXRxc; arc=none smtp.client-ip=185.246.85.4 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="nSdCXRxc" Received: from smtpout-01.galae.net (smtpout-01.galae.net [212.83.139.233]) by smtpout-03.galae.net (Postfix) with ESMTPS id 76F314E41A72; Fri, 5 Dec 2025 19:39:51 +0000 (UTC) Received: from mail.galae.net (mail.galae.net [212.83.136.155]) by smtpout-01.galae.net (Postfix) with ESMTPS id 478CA606AC; Fri, 5 Dec 2025 19:39:51 +0000 (UTC) Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id 2C20C102F1956; Fri, 5 Dec 2025 20:39:48 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=dkim; t=1764963590; h=from:subject:date:message-id:to:cc:mime-version:content-type: content-transfer-encoding:in-reply-to:references; bh=V1ljS8mutIdNmKv1uTSb1HOPJkaHUuTFfvh6FqXD2eU=; b=nSdCXRxcvN2Tl6j80JiBHD5VXqmAb7ozAe3pOWLL0TCcmgz74lHnCUVCUSrEU0h4mGed34 JNJ9VkXDTUIHl3A12525JxJqlmuFa26k2arTrtbB8a9xN5IvUj/6XHs3tbByK28V3fw+EB To0Wo+B7Wnzw11pFwQorDZXUR2VwwYRP+88vRe552E/aCI8AutOTrY4XhYJAgfcbKyeEq6 53hZk46QueC2gXbjkX/ouxdtBvNbiAHqdNCcBUnUsCCN41z88bw5FV9eS3pz1Ap1R0NFvZ Cl4KHTzx3XaLEtD2XmviJoHz+l3JEVspmc9a8Lpy9Ln+a5+OsbO4MBZGhtbpxw== From: Miquel Raynal Date: Fri, 05 Dec 2025 20:38:56 +0100 Subject: [PATCH RFC 5/8] spi: spi-mem: Create a secondary read operation Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251205-winbond-v6-18-rc1-cont-read-v1-5-01bc48631c73@bootlin.com> References: <20251205-winbond-v6-18-rc1-cont-read-v1-0-01bc48631c73@bootlin.com> In-Reply-To: <20251205-winbond-v6-18-rc1-cont-read-v1-0-01bc48631c73@bootlin.com> To: Mark Brown , Richard Weinberger , Vignesh Raghavendra , Michael Walle Cc: Tudor Ambarus , Pratyush Yadav , Thomas Petazzoni , Steam Lin , Santhosh Kumar K , linux-spi@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mtd@lists.infradead.org, Miquel Raynal X-Mailer: b4 0.14.3 X-Last-TLS-Session-Version: TLSv1.3 In some situations, direct mappings may need to use different operation templates. For instance, when enabling continuous reads, Winbond SPI NANDs no longer expect address cycles because they would be ignoring them otherwise. Hence, right after the command opcode, they start counting dummy cycles, followed by the data cycles as usual. This breaks the assumptions of "reads from cache" always being done identically once the best variant has been picked up, across the lifetime of the system. In order to support this feature, we must give direct mapping more than a single operation template to use, in order to switch to using secondary operations upon request by the upper layer. Create the concept of optional secondary operation template, which may or may not be fulfilled by the SPI NAND and SPI NOR cores. If the underlying SPI controller does not leverage any kind of direct mapping acceleration, the feature has no impact and can be freely used. Otherwise, the controller driver needs to opt-in for using this feature, if supported. The condition checked to know whether a secondary operation has been provided or not is to look for a non zero opcode to limit the creation of extra variables. In practice, the opcode 0x00 exist, but is not related to any cache related operation. Signed-off-by: Miquel Raynal Acked-by: Mark Brown --- The choice of defining two variables named primary and secondary instead of using an array of templates is on purpose, to simplify the reading. I find less obvious the use of an array here but this is personal taste. --- drivers/spi/spi-mem.c | 17 +++++++++++++++++ include/linux/spi/spi-mem.h | 5 +++++ 2 files changed, 22 insertions(+) diff --git a/drivers/spi/spi-mem.c b/drivers/spi/spi-mem.c index 50f16943dc73..b6debc796cf8 100644 --- a/drivers/spi/spi-mem.c +++ b/drivers/spi/spi-mem.c @@ -708,6 +708,23 @@ spi_mem_dirmap_create(struct spi_mem *mem, if (info->primary_op_tmpl.data.dir =3D=3D SPI_MEM_NO_DATA) return ERR_PTR(-EINVAL); =20 + /* Apply similar constraints to the secondary template */ + if (info->secondary_op_tmpl.cmd.opcode) { + if (!info->secondary_op_tmpl.addr.nbytes || + info->secondary_op_tmpl.addr.nbytes > 8) + return ERR_PTR(-EINVAL); + + if (info->secondary_op_tmpl.data.dir =3D=3D SPI_MEM_NO_DATA) + return ERR_PTR(-EINVAL); + + if (!spi_mem_supports_op(mem, &info->secondary_op_tmpl)) + return ERR_PTR(-EOPNOTSUPP); + + if (ctlr->mem_ops && ctlr->mem_ops->dirmap_create && + !spi_mem_controller_is_capable(ctlr, secondary_op_tmpl)) + return ERR_PTR(-EOPNOTSUPP); + } + desc =3D kzalloc(sizeof(*desc), GFP_KERNEL); if (!desc) return ERR_PTR(-ENOMEM); diff --git a/include/linux/spi/spi-mem.h b/include/linux/spi/spi-mem.h index 3092caefa0b6..099de23e7084 100644 --- a/include/linux/spi/spi-mem.h +++ b/include/linux/spi/spi-mem.h @@ -207,6 +207,8 @@ struct spi_mem_op { * struct spi_mem_dirmap_info - Direct mapping information * @op_tmpl: operation template that should be used by the direct mapping = when * the memory device is accessed + * @secondary_op_tmpl: secondary template, may be used as an alternative t= o the + * primary template (decided by the upper layer) * @offset: absolute offset this direct mapping is pointing to * @length: length in byte of this direct mapping * @@ -219,6 +221,7 @@ struct spi_mem_op { struct spi_mem_dirmap_info { struct spi_mem_op *op_tmpl; struct spi_mem_op primary_op_tmpl; + struct spi_mem_op secondary_op_tmpl; u64 offset; u64 length; }; @@ -362,12 +365,14 @@ struct spi_controller_mem_ops { * @swap16: Supports swapping bytes on a 16 bit boundary when configured in * Octal DTR * @per_op_freq: Supports per operation frequency switching + * @secondary_op_tmpl: Supports leveraging a secondary memory operation te= mplate */ struct spi_controller_mem_caps { bool dtr; bool ecc; bool swap16; bool per_op_freq; + bool secondary_op_tmpl; }; =20 #define spi_mem_controller_is_capable(ctlr, cap) \ --=20 2.51.1