From nobody Thu Dec 11 19:15:12 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9069D35E543; Fri, 5 Dec 2025 18:41:52 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764960112; cv=none; b=E3EDZntwerTQtCJZQvNSL+UnoSE3+XnGaYnVt2ejyRyPW/6rnVCq85XHCbOfIM/WQcH6Wr39HU/4YQnqVnnnoV7mCB6PoYu7Q1PyPN+Q7YRkXtMFcUAcKbZemDPeXzwPbGCfbaRzyr2q/9sjZlROQg8CDR9qxoz5Xlc3ZDWed6Q= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764960112; c=relaxed/simple; bh=pSevc+phD1fBDgaqvt0l/IWjr9lXWT3WiB8a6qBRwR4=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=rBOKuBcq4VYrZi9IlPzqcfAB0pHym7DKW3Xc4BmG662vY7LU7cY8bL6mpxpVH5v8uTDdWp5Xi+L7ATsDX66K50REYvQjkCQkAsjPmGUYnDaYaoFDxxqP4JbXUSxG/muWkXEd1s+izflJRxdQv6zeUtaLuKuRtvPwJ/YW8Juqy/8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=uVT2rsHn; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="uVT2rsHn" Received: by smtp.kernel.org (Postfix) with ESMTPS id 60C2BC2BCC7; Fri, 5 Dec 2025 18:41:52 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1764960112; bh=pSevc+phD1fBDgaqvt0l/IWjr9lXWT3WiB8a6qBRwR4=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=uVT2rsHn+o/6JF2AVQy5t6bSSyTFJ+/DcCEuFiZrQzzn2mkTukNAZLx74sBgUbQuT CqVjhB16DUpaghtMsbpNH6lQT+badUkIKU+9uowmBKpbv4E634CjoN9T9lmfYvzBRl ctyAhKNAO9AmzPH3JElpl/AVJ6IQosMDGnAHm9pnTW2rIIgVwZSzUHH4FzzZ/0xghM JBaPhjprBJLmz41L5TWwW0njqA6CI6NKRY2a1ry23stZiftSCBSr1VGjs2fbS3bsbf 5ijTYc1QpOA0PT6hGWApcYTbZtg7oCiInQx/2rTXgOYfKjwa1k7OtT6dXIlWdd3VBm 7D4lQSib8QDvg== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 521AED339B7; Fri, 5 Dec 2025 18:41:52 +0000 (UTC) From: Deepak Gupta via B4 Relay Date: Fri, 05 Dec 2025 10:42:03 -0800 Subject: [PATCH v25 25/28] riscv: create a config for shadow stack and landing pad instr support Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251205-v5_user_cfi_series-v25-25-1a07c0127361@rivosinc.com> References: <20251205-v5_user_cfi_series-v25-0-1a07c0127361@rivosinc.com> In-Reply-To: <20251205-v5_user_cfi_series-v25-0-1a07c0127361@rivosinc.com> To: Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , x86@kernel.org, "H. Peter Anvin" , Andrew Morton , "Liam R. Howlett" , Vlastimil Babka , Lorenzo Stoakes , Paul Walmsley , Palmer Dabbelt , Albert Ou , Conor Dooley , Rob Herring , Krzysztof Kozlowski , Arnd Bergmann , Christian Brauner , Peter Zijlstra , Oleg Nesterov , Eric Biederman , Kees Cook , Jonathan Corbet , Shuah Khan , Jann Horn , Conor Dooley , Miguel Ojeda , Alex Gaynor , Boqun Feng , Gary Guo , =?utf-8?q?Bj=C3=B6rn_Roy_Baron?= , Andreas Hindborg , Alice Ryhl , Trevor Gross , Benno Lossin Cc: linux-kernel@vger.kernel.org, linux-fsdevel@vger.kernel.org, linux-mm@kvack.org, linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-arch@vger.kernel.org, linux-doc@vger.kernel.org, linux-kselftest@vger.kernel.org, alistair.francis@wdc.com, richard.henderson@linaro.org, jim.shu@sifive.com, andybnac@gmail.com, kito.cheng@sifive.com, charlie@rivosinc.com, atishp@rivosinc.com, evan@rivosinc.com, cleger@rivosinc.com, alexghiti@rivosinc.com, samitolvanen@google.com, broonie@kernel.org, rick.p.edgecombe@intel.com, rust-for-linux@vger.kernel.org, Zong Li , Andreas Korb , Valentin Haudiquet , Deepak Gupta X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1764960107; l=2507; i=debug@rivosinc.com; s=20251023; h=from:subject:message-id; bh=ShEpf/mdXmXiYjxpPm2TYnh4BcOrM6EZbWr5d0sAVrg=; b=Im+5jnxuIPQo6DUl06oEYlBQjitdutc40AsyN4qPupKlVzp5lwfX0S6c/IstZH66/KbG6xM/T cGI2w5Fx9Q4BiCo7T8juXcnlGLUMnbMH6S493wuwcI0FyrqAgx5IGfl X-Developer-Key: i=debug@rivosinc.com; a=ed25519; pk=O37GQv1thBhZToXyQKdecPDhtWVbEDRQ0RIndijvpjk= X-Endpoint-Received: by B4 Relay for debug@rivosinc.com/20251023 with auth_id=553 X-Original-From: Deepak Gupta Reply-To: debug@rivosinc.com From: Deepak Gupta This patch creates a config for shadow stack support and landing pad instr support. Shadow stack support and landing instr support can be enabled by selecting `CONFIG_RISCV_USER_CFI`. Selecting `CONFIG_RISCV_USER_CFI` wires up path to enumerate CPU support and if cpu support exists, kernel will support cpu assisted user mode cfi. If CONFIG_RISCV_USER_CFI is selected, select `ARCH_USES_HIGH_VMA_FLAGS`, `ARCH_HAS_USER_SHADOW_STACK` and DYNAMIC_SIGFRAME for riscv. Reviewed-by: Zong Li Tested-by: Andreas Korb Tested-by: Valentin Haudiquet Signed-off-by: Deepak Gupta --- arch/riscv/Kconfig | 22 ++++++++++++++++++++++ arch/riscv/configs/hardening.config | 4 ++++ 2 files changed, 26 insertions(+) diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index 0c6038dc5dfd..be3f036e18d0 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -1146,6 +1146,28 @@ config RANDOMIZE_BASE =20 If unsure, say N. =20 +config RISCV_USER_CFI + def_bool y + bool "riscv userspace control flow integrity" + depends on 64BIT && \ + $(cc-option,-mabi=3Dlp64 -march=3Drv64ima_zicfiss_zicfilp -fcf-protectio= n=3Dfull) + depends on RISCV_ALTERNATIVE + select RISCV_SBI + select ARCH_HAS_USER_SHADOW_STACK + select ARCH_USES_HIGH_VMA_FLAGS + select DYNAMIC_SIGFRAME + help + Provides CPU-assisted control flow integrity to userspace tasks. + Control flow integrity is provided by implementing shadow stack for + backward edge and indirect branch tracking for forward edge in program. + Shadow stack protection is a hardware feature that detects function + return address corruption. This helps mitigate ROP attacks. + Indirect branch tracking enforces that all indirect branches must land + on a landing pad instruction else CPU will fault. This mitigates against + JOP / COP attacks. Applications must be enabled to use it, and old user- + space does not get protection "for free". + default y. + endmenu # "Kernel features" =20 menu "Boot options" diff --git a/arch/riscv/configs/hardening.config b/arch/riscv/configs/harde= ning.config new file mode 100644 index 000000000000..089f4cee82f4 --- /dev/null +++ b/arch/riscv/configs/hardening.config @@ -0,0 +1,4 @@ +# RISCV specific kernel hardening options + +# Enable control flow integrity support for usermode. +CONFIG_RISCV_USER_CFI=3Dy --=20 2.43.0