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Each variant of the family differs in resolution. The device contains two outputs (gp0, gp1). The outputs can be configured for range of options, such as threshold and data ready. The device uses a 2-wire I3C interface. Signed-off-by: Jorge Marques --- .../devicetree/bindings/iio/adc/adi,ad4062.yaml | 124 +++++++++++++++++= ++++ MAINTAINERS | 6 + 2 files changed, 130 insertions(+) diff --git a/Documentation/devicetree/bindings/iio/adc/adi,ad4062.yaml b/Do= cumentation/devicetree/bindings/iio/adc/adi,ad4062.yaml new file mode 100644 index 0000000000000..a7a2ad761d1f0 --- /dev/null +++ b/Documentation/devicetree/bindings/iio/adc/adi,ad4062.yaml @@ -0,0 +1,124 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +# Copyright 2024 Analog Devices Inc. +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/iio/adc/adi,ad4062.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Analog Devices AD4062 ADC family device driver + +maintainers: + - Jorge Marques + +description: | + Analog Devices AD4062 Single Channel Precision SAR ADC family + + https://www.analog.com/media/en/technical-documentation/data-sheets/ad40= 60.pdf + https://www.analog.com/media/en/technical-documentation/data-sheets/ad40= 62.pdf + +properties: + compatible: + enum: + - adi,ad4060 + - adi,ad4062 + + reg: + maxItems: 1 + + interrupts: + description: + The interrupt pins are digital outputs that can be configured at run= time + as multiple interrupt signals. Each can be configured as GP_INTR, RD= Y, + DEV_EN, logic low, logic high and DEV_RDY (GP1 only). RDY is the + active-low data ready signal, indicates when new ADC data are ready = to + read. DEV_EN synchronizes the enable and power-down states of signal + chain devices with the ADC sampling instant. DEV_RDY is an active-hi= gh + signal that indicates when the device is ready to accept serial inte= rface + communications. In GP_INTR mode, the interrupt outputs one of the + threshold detection interrupt signals (MIN_INTR, MAX_INTR or either). + minItems: 1 + items: + - description: + GP0 pin, cannot be configured as DEV_RDY. + - description: + GP1 pin, can be configured to any setting. + + interrupt-names: + minItems: 1 + items: + - const: gp0 + - const: gp1 + + gpio-controller: + description: + Marks the device node as a GPIO controller. GPs not listed as interr= upts + are exposed as a GPO. + + '#gpio-cells': + const: 2 + description: + The first cell is the GPIO number and the second cell specifies + GPIO flags, as defined in . + + vdd-supply: + description: Analog power supply. + + vio-supply: + description: Digital interface logic power supply. + + ref-supply: + description: + Reference voltage to set the ADC full-scale range. If not present, + vdd-supply is used as the reference voltage. + +required: + - compatible + - reg + - vdd-supply + - vio-supply + +allOf: + - $ref: /schemas/i3c/i3c.yaml# + +unevaluatedProperties: false + +examples: + - | + #include + #include + + i3c { + #address-cells =3D <3>; + #size-cells =3D <0>; + + adc@0,2ee007c0000 { + reg =3D <0x0 0x2ee 0x7c0000>; + vdd-supply =3D <&vdd>; + vio-supply =3D <&vio>; + ref-supply =3D <&ref>; + + interrupt-parent =3D <&gpio>; + interrupts =3D <0 0 IRQ_TYPE_EDGE_RISING>, + <0 1 IRQ_TYPE_EDGE_FALLING>; + interrupt-names =3D "gp0", "gp1"; + }; + }; + + - | + #include + #include + + i3c { + #address-cells =3D <3>; + #size-cells =3D <0>; + + adc@0,2ee007c0000 { + reg =3D <0x0 0x2ee 0x7c0000>; + vdd-supply =3D <&vdd>; + vio-supply =3D <&vio>; + ref-supply =3D <&ref>; + + gpio-controller; + #gpio-cells =3D <2>; + }; + }; diff --git a/MAINTAINERS b/MAINTAINERS index 31d98efb1ad15..e22ba5ec8c849 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1432,6 +1432,12 @@ F: Documentation/devicetree/bindings/iio/adc/adi,ad4= 030.yaml F: Documentation/iio/ad4030.rst F: drivers/iio/adc/ad4030.c =20 +ANALOG DEVICES INC AD4062 DRIVER +M: Jorge Marques +S: Supported +W: https://ez.analog.com/linux-software-drivers +F: Documentation/devicetree/bindings/iio/adc/adi,ad4062.yaml + ANALOG DEVICES INC AD4080 DRIVER M: Antoniu Miclaus L: linux-iio@vger.kernel.org --=20 2.51.1 From nobody Thu Dec 18 09:27:40 2025 Received: from mx0b-00128a01.pphosted.com (mx0a-00128a01.pphosted.com [148.163.135.77]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 61E2D34DCE4; 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Fri, 5 Dec 2025 10:12:23 -0500 From: Jorge Marques Date: Fri, 5 Dec 2025 16:12:03 +0100 Subject: [PATCH v3 2/9] docs: iio: New docs for ad4062 driver Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20251205-staging-ad4062-v3-2-8761355f9c66@analog.com> References: <20251205-staging-ad4062-v3-0-8761355f9c66@analog.com> In-Reply-To: <20251205-staging-ad4062-v3-0-8761355f9c66@analog.com> To: Lars-Peter Clausen , Michael Hennerich , Jonathan Cameron , "David Lechner" , =?utf-8?q?Nuno_S=C3=A1?= , Andy Shevchenko , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Jonathan Corbet , Linus Walleij , Bartosz Golaszewski CC: , , , , , Jorge Marques X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1764947528; l=4325; i=jorge.marques@analog.com; s=20250303; h=from:subject:message-id; bh=Z8LmT3qY041U83j0q+I/X13ABeV5uquFKXkkjyjU46A=; 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Signed-off-by: Jorge Marques --- Documentation/iio/ad4062.rst | 94 ++++++++++++++++++++++++++++++++++++++++= ++++ Documentation/iio/index.rst | 1 + MAINTAINERS | 1 + 3 files changed, 96 insertions(+) diff --git a/Documentation/iio/ad4062.rst b/Documentation/iio/ad4062.rst new file mode 100644 index 0000000000000..e6bcca2bef24b --- /dev/null +++ b/Documentation/iio/ad4062.rst @@ -0,0 +1,94 @@ +.. SPDX-License-Identifier: GPL-2.0-only + +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D +AD4062 driver +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D + +ADC driver for Analog Devices Inc. AD4060/AD4062 devices. The module name = is +``ad4062``. + +Supported devices +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D + +The following chips are supported by this driver: + +* `AD4060 `_ +* `AD4062 `_ + +Wiring modes +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D + +The ADC is interfaced through an I3C bus, and contains two programmable GP= IOs. + +The ADC convert-start happens on the SDA rising edge of the I3C stop (P) b= it +at the end of the read command. + +The two programmable GPIOS are optional and have a role assigned if presen= t in +the devicetree ``interrupt-names`` property: + +- GP1: Is assigned the role of Data Ready signal. + +Device attributes +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D + +The ADC contains only one channel with following attributes: + +.. list-table:: Channel attributes + :header-rows: 1 + + * - Attribute + - Description + * - ``in_voltage_calibscale`` + - Sets the gain scaling factor that the hardware applies to the sampl= e, + to compensate for system gain error. + * - ``in_voltage_oversampling_ratio`` + - Sets device's burst averaging mode to over sample using the + internal sample rate. Value 1 disable the burst averaging mode. + * - ``in_voltage_oversampling_ratio_available`` + - List of available oversampling values. + * - ``in_voltage_raw`` + - Returns the raw ADC voltage value. + * - ``in_voltage_scale`` + - Returns the channel scale in reference to the reference voltage + ``ref-supply`` or ``vdd-supply`` if the former not present. + +Also contain the following device attributes: + +.. list-table:: Device attributes + :header-rows: 1 + + * - Attribute + - Description + * - ``sampling_frequency`` + - Sets the duration of a single scan, used in the burst averaging mod= e. + The duration is described by ``(n_avg - 1) / fosc + tconv``, where + ``n_avg`` is the oversampling ratio, ``fosc`` is the internal sample + rate and ``tconv`` is the ADC conversion time. + * - ``sampling_frequency_available`` + - Lists the available sampling frequencies, computed on the current + oversampling ratio. If the ratio is 1, the frequency is ``1/tconv``. + +Interrupts +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D + +The interrupts are mapped through the ``interrupt-names`` and ``interrupts= `` +properties. + +The ``interrupt-names`` ``gp1`` entry sets the role of Data Ready signal. +If it is not present, the driver fallback to enabling the same role as an +I3C IBI. + +Low-power mode +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D + +The device enters low-power mode on idle to save power. Enabling an event = puts +the device out of the low-power since the ADC autonomously samples to asse= rt +the event condition. + +Unimplemented features +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D + +- Monitor mode +- Trigger mode +- Averaging mode +- General purpose output diff --git a/Documentation/iio/index.rst b/Documentation/iio/index.rst index 315ae37d6fd4b..ba3e609c6a13c 100644 --- a/Documentation/iio/index.rst +++ b/Documentation/iio/index.rst @@ -22,6 +22,7 @@ Industrial I/O Kernel Drivers ad3552r ad4000 ad4030 + ad4062 ad4695 ad7191 ad7380 diff --git a/MAINTAINERS b/MAINTAINERS index e22ba5ec8c849..8fc28b789d639 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1437,6 +1437,7 @@ M: Jorge Marques S: Supported W: https://ez.analog.com/linux-software-drivers F: Documentation/devicetree/bindings/iio/adc/adi,ad4062.yaml +F: Documentation/iio/ad4062.rst =20 ANALOG DEVICES INC AD4080 DRIVER M: Antoniu Miclaus --=20 2.51.1 From nobody Thu Dec 18 09:27:40 2025 Received: from mx0b-00128a01.pphosted.com (mx0a-00128a01.pphosted.com [148.163.135.77]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1DDFC2EE5FC; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20251205-staging-ad4062-v3-3-8761355f9c66@analog.com> References: <20251205-staging-ad4062-v3-0-8761355f9c66@analog.com> In-Reply-To: <20251205-staging-ad4062-v3-0-8761355f9c66@analog.com> To: Lars-Peter Clausen , Michael Hennerich , Jonathan Cameron , David Lechner , =?utf-8?q?Nuno_S=C3=A1?= , Andy Shevchenko , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Jonathan Corbet , Linus Walleij , Bartosz Golaszewski CC: , , , , , Jorge Marques X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1764947528; l=27321; i=jorge.marques@analog.com; s=20250303; h=from:subject:message-id; bh=wphneAhLTHV8VZE4rvIsuUuuw0G7QgYv1zhqGiqYgQE=; b=Sjjx2Q55EcpgzI2Giswpd0xSDGnoevKin0wmz5qbXD5kzlGieEf6kc8FQVtDCTRhdAqHiJJrF cXJTr3YWFM/CcLwQeW1kGd9YlXpLpmr/aNOajlHEdv04KC70dxjUKKz X-Developer-Key: i=jorge.marques@analog.com; a=ed25519; pk=NUR1IZZMH0Da3QbJ2tBSznSPVfRpuoWdhBzKGSpAdbg= X-ADIRuleOP-NewSCL: Rule Triggered X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMjA1MDEwOSBTYWx0ZWRfX7gnRR1QYfwoy 9ELSO/Bd6aD2ES7M3WGcReKesG7dEhIoEzOJGLpq7gi3NVPTAZhXcTyB6OGoFMP7Oio0KkC1oRr +NKJlF1E6FnOqzIzIXvaSXfA81atSeDwq/lHfZuKBwoBrsgfRoWH1hcg23cP4moYy6Avmwy54zv wLz5EgIZvl6Q/JF3/UW3Tils2EmWf5zgfZASbsuU4BYm5vQyFRW4S88q7sxup/IzOVEHhvG2GQT r/PPdROX+bVCA2wOgOGD+quiWuhseEr15NhKlyl+J/Y9g8u6mLzSj+iAfF7Dbc2uxg9vrOPgD8Y CG9Xgf9Nb7/SIaL9g/5x5Se/m5+XzcXtgsKoauYjR71ZDq4w8Tx4PsA8D3m/JyXUQr+utMGmMDA SqC8d7fS8QJFc6j63E2vabflkIR1vg== X-Authority-Analysis: v=2.4 cv=Q+nfIo2a c=1 sm=1 tr=0 ts=6932f665 cx=c_pps a=3WNzaoukacrqR9RwcOSAdA==:117 a=3WNzaoukacrqR9RwcOSAdA==:17 a=IkcTkHD0fZMA:10 a=wP3pNCr1ah4A:10 a=VkNPw1HP01LnGYTKEx00:22 a=gAnH3GRIAAAA:8 a=NSoWa4u4GR6dBB1-BnIA:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 X-Proofpoint-ORIG-GUID: gWDqhtW0oaZE4rx2ezGMqXLByKwenIen X-Proofpoint-GUID: gWDqhtW0oaZE4rx2ezGMqXLByKwenIen X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2025-12-05_05,2025-12-04_04,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 bulkscore=0 clxscore=1015 spamscore=0 lowpriorityscore=0 priorityscore=1501 impostorscore=0 adultscore=0 malwarescore=0 suspectscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2510240001 definitions=main-2512050109 The AD4060/AD4062 are versatile, 16-bit/12-bit, successive approximation register (SAR) analog-to-digital converter (ADC) with low-power and threshold monitoring modes. Signed-off-by: Jorge Marques --- MAINTAINERS | 1 + drivers/iio/adc/Kconfig | 11 + drivers/iio/adc/Makefile | 1 + drivers/iio/adc/ad4062.c | 879 +++++++++++++++++++++++++++++++++++++++++++= ++++ 4 files changed, 892 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 8fc28b789d639..003f51cfb0d07 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1438,6 +1438,7 @@ S: Supported W: https://ez.analog.com/linux-software-drivers F: Documentation/devicetree/bindings/iio/adc/adi,ad4062.yaml F: Documentation/iio/ad4062.rst +F: drivers/iio/adc/ad4062.c =20 ANALOG DEVICES INC AD4080 DRIVER M: Antoniu Miclaus diff --git a/drivers/iio/adc/Kconfig b/drivers/iio/adc/Kconfig index 58da8255525e4..e506dbe83f488 100644 --- a/drivers/iio/adc/Kconfig +++ b/drivers/iio/adc/Kconfig @@ -70,6 +70,17 @@ config AD4030 To compile this driver as a module, choose M here: the module will be called ad4030. =20 +config AD4062 + tristate "Analog Devices AD4062 Driver" + depends on I3C + select REGMAP_I3C + help + Say yes here to build support for Analog Devices AD4062 I3C analog + to digital converters (ADC). + + To compile this driver as a module, choose M here: the module will be + called ad4062. + config AD4080 tristate "Analog Devices AD4080 high speed ADC" depends on SPI diff --git a/drivers/iio/adc/Makefile b/drivers/iio/adc/Makefile index 7cc8f9a12f763..a897252eeed40 100644 --- a/drivers/iio/adc/Makefile +++ b/drivers/iio/adc/Makefile @@ -11,6 +11,7 @@ obj-$(CONFIG_AB8500_GPADC) +=3D ab8500-gpadc.o obj-$(CONFIG_AD_SIGMA_DELTA) +=3D ad_sigma_delta.o obj-$(CONFIG_AD4000) +=3D ad4000.o obj-$(CONFIG_AD4030) +=3D ad4030.o +obj-$(CONFIG_AD4062) +=3D ad4062.o obj-$(CONFIG_AD4080) +=3D ad4080.o obj-$(CONFIG_AD4130) +=3D ad4130.o obj-$(CONFIG_AD4170_4) +=3D ad4170-4.o diff --git a/drivers/iio/adc/ad4062.c b/drivers/iio/adc/ad4062.c new file mode 100644 index 0000000000000..54f7f69e40879 --- /dev/null +++ b/drivers/iio/adc/ad4062.c @@ -0,0 +1,879 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Analog Devices AD4062 I3C ADC driver + * + * Copyright 2025 Analog Devices Inc. + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define AD4062_REG_INTERFACE_CONFIG_A 0x00 +#define AD4062_REG_DEVICE_CONFIG 0x02 +#define AD4062_REG_DEVICE_CONFIG_POWER_MODE_MSK GENMASK(1, 0) +#define AD4062_REG_DEVICE_CONFIG_LOW_POWER_MODE 3 +#define AD4062_REG_PROD_ID_1 0x05 +#define AD4062_REG_DEVICE_GRADE 0x06 +#define AD4062_REG_SCRATCH_PAD 0x0A +#define AD4062_REG_VENDOR_H 0x0D +#define AD4062_REG_STREAM_MODE 0x0E +#define AD4062_REG_INTERFACE_STATUS 0x11 +#define AD4062_REG_MODE_SET 0x20 +#define AD4062_REG_MODE_SET_ENTER_ADC BIT(0) +#define AD4062_REG_ADC_MODES 0x21 +#define AD4062_REG_ADC_MODES_MODE_MSK GENMASK(1, 0) +#define AD4062_REG_ADC_CONFIG 0x22 +#define AD4062_REG_ADC_CONFIG_REF_EN_MSK BIT(5) +#define AD4062_REG_ADC_CONFIG_SCALE_EN_MSK BIT(4) +#define AD4062_REG_AVG_CONFIG 0x23 +#define AD4062_REG_GP_CONF 0x24 +#define AD4062_REG_GP_CONF_MODE_MSK_1 GENMASK(6, 4) +#define AD4062_REG_INTR_CONF 0x25 +#define AD4062_REG_INTR_CONF_EN_MSK_1 GENMASK(5, 4) +#define AD4062_REG_TIMER_CONFIG 0x27 +#define AD4062_REG_TIMER_CONFIG_FS_MASK GENMASK(7, 4) +#define AD4062_REG_MON_VAL 0x2F +#define AD4062_REG_ADC_IBI_EN 0x31 +#define AD4062_REG_ADC_IBI_EN_CONV_TRIGGER BIT(2) +#define AD4062_REG_FUSE_CRC 0x40 +#define AD4062_REG_DEVICE_STATUS 0x41 +#define AD4062_REG_DEVICE_STATUS_DEVICE_RESET BIT(6) +#define AD4062_REG_IBI_STATUS 0x48 +#define AD4062_REG_CONV_READ_LSB 0x50 +#define AD4062_REG_CONV_TRIGGER 0x59 +#define AD4062_REG_CONV_AUTO 0x61 +#define AD4062_MAX_REG AD4062_REG_CONV_AUTO + +#define AD4062_MON_VAL_MIDDLE_POINT 0x8000 + +#define AD4062_I3C_VENDOR 0x0177 +#define AD4062_SOFT_RESET 0x81 + +#define AD4060_MAX_AVG 0x7 +#define AD4062_MAX_AVG 0xB + +#define AD4062_GP_DRDY 0x2 + +#define AD4062_INTR_EN_NEITHER 0x0 + +#define AD4062_TCONV_NS 270 + +enum ad4062_operation_mode { + AD4062_SAMPLE_MODE =3D 0x0, + AD4062_BURST_AVERAGING_MODE =3D 0x1, + AD4062_MONITOR_MODE =3D 0x3, +}; + +struct ad4062_chip_info { + const struct iio_chan_spec channels[1]; + const char *name; + u16 prod_id; + u8 max_avg; +}; + +enum { + AD4062_SCAN_TYPE_SAMPLE, + AD4062_SCAN_TYPE_BURST_AVG, +}; + +static const struct iio_scan_type ad4062_scan_type_12_s[] =3D { + [AD4062_SCAN_TYPE_SAMPLE] =3D { + .sign =3D 's', + .realbits =3D 16, + .storagebits =3D 32, + .endianness =3D IIO_BE, + }, + [AD4062_SCAN_TYPE_BURST_AVG] =3D { + .sign =3D 's', + .realbits =3D 16, + .storagebits =3D 32, + .endianness =3D IIO_BE, + }, +}; + +static const struct iio_scan_type ad4062_scan_type_16_s[] =3D { + [AD4062_SCAN_TYPE_SAMPLE] =3D { + .sign =3D 's', + .realbits =3D 16, + .storagebits =3D 32, + .endianness =3D IIO_BE, + }, + [AD4062_SCAN_TYPE_BURST_AVG] =3D { + .sign =3D 's', + .realbits =3D 24, + .storagebits =3D 32, + .endianness =3D IIO_BE, + }, +}; + +static const unsigned int ad4062_conversion_freqs[] =3D { + 2000000, 1000000, 300000, 100000, /* 0 - 3 */ + 33300, 10000, 3000, 500, /* 4 - 7 */ + 333, 250, 200, 166, /* 8 - 11 */ + 140, 124, 111, /* 12 - 15 */ +}; + +struct ad4062_state { + const struct ad4062_chip_info *chip; + const struct ad4062_bus_ops *ops; + enum ad4062_operation_mode mode; + struct completion completion; + struct iio_trigger *trigger; + struct iio_dev *indio_dev; + struct i3c_device *i3cdev; + struct regmap *regmap; + int vref_uV; + unsigned int samp_freqs[ARRAY_SIZE(ad4062_conversion_freqs)]; + union { + __be32 be32; + __be16 be16; + u8 bytes[4]; + } buf __aligned(IIO_DMA_MINALIGN); + u16 sampling_frequency; + u8 oversamp_ratio; + u8 reg_addr_conv; +}; + +static const struct regmap_range ad4062_regmap_rd_ranges[] =3D { + regmap_reg_range(AD4062_REG_INTERFACE_CONFIG_A, AD4062_REG_DEVICE_GRADE), + regmap_reg_range(AD4062_REG_SCRATCH_PAD, AD4062_REG_INTERFACE_STATUS), + regmap_reg_range(AD4062_REG_MODE_SET, AD4062_REG_ADC_IBI_EN), + regmap_reg_range(AD4062_REG_FUSE_CRC, AD4062_REG_IBI_STATUS), + regmap_reg_range(AD4062_REG_CONV_READ_LSB, AD4062_REG_CONV_AUTO), +}; + +static const struct regmap_access_table ad4062_regmap_rd_table =3D { + .yes_ranges =3D ad4062_regmap_rd_ranges, + .n_yes_ranges =3D ARRAY_SIZE(ad4062_regmap_rd_ranges), +}; + +static const struct regmap_range ad4062_regmap_wr_ranges[] =3D { + regmap_reg_range(AD4062_REG_INTERFACE_CONFIG_A, AD4062_REG_DEVICE_CONFIG), + regmap_reg_range(AD4062_REG_SCRATCH_PAD, AD4062_REG_SCRATCH_PAD), + regmap_reg_range(AD4062_REG_STREAM_MODE, AD4062_REG_INTERFACE_STATUS), + regmap_reg_range(AD4062_REG_MODE_SET, AD4062_REG_ADC_IBI_EN), + regmap_reg_range(AD4062_REG_FUSE_CRC, AD4062_REG_DEVICE_STATUS), +}; + +static const struct regmap_access_table ad4062_regmap_wr_table =3D { + .yes_ranges =3D ad4062_regmap_wr_ranges, + .n_yes_ranges =3D ARRAY_SIZE(ad4062_regmap_wr_ranges), +}; + +static int ad4062_conversion_frequency_set(struct ad4062_state *st, u8 val) +{ + return regmap_write(st->regmap, AD4062_REG_TIMER_CONFIG, + FIELD_PREP(AD4062_REG_TIMER_CONFIG_FS_MASK, val)); +} + +#define AD4062_CHAN(bits) { \ + .type =3D IIO_VOLTAGE, \ + .info_mask_shared_by_type =3D BIT(IIO_CHAN_INFO_RAW) | \ + BIT(IIO_CHAN_INFO_SCALE) | \ + BIT(IIO_CHAN_INFO_CALIBSCALE) | \ + BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \ + .info_mask_shared_by_all =3D BIT(IIO_CHAN_INFO_SAMP_FREQ), \ + .info_mask_shared_by_type_available =3D BIT(IIO_CHAN_INFO_OVERSAMPLING_RA= TIO), \ + .info_mask_shared_by_all_available =3D BIT(IIO_CHAN_INFO_SAMP_FREQ), \ + .indexed =3D 1, \ + .channel =3D 0, \ + .has_ext_scan_type =3D 1, \ + .ext_scan_type =3D ad4062_scan_type_##bits##_s, \ + .num_ext_scan_type =3D ARRAY_SIZE(ad4062_scan_type_##bits##_s), \ +} + +static const struct ad4062_chip_info ad4060_chip_info =3D { + .name =3D "ad4060", + .channels =3D { AD4062_CHAN(12) }, + .prod_id =3D 0x7A, + .max_avg =3D AD4060_MAX_AVG, +}; + +static const struct ad4062_chip_info ad4062_chip_info =3D { + .name =3D "ad4062", + .channels =3D { AD4062_CHAN(16) }, + .prod_id =3D 0x7C, + .max_avg =3D AD4062_MAX_AVG, +}; + +static int ad4062_set_oversampling_ratio(struct ad4062_state *st, unsigned= int val) +{ + const u32 _max =3D GENMASK(st->chip->max_avg, 0) + 1; + const u32 _min =3D 1; + int ret; + + if (!in_range(val, _min, _max)) + return -EINVAL; + + /* 1 disables oversampling */ + val =3D ilog2(val); + if (val =3D=3D 0) { + st->mode =3D AD4062_SAMPLE_MODE; + } else { + st->mode =3D AD4062_BURST_AVERAGING_MODE; + ret =3D regmap_write(st->regmap, AD4062_REG_AVG_CONFIG, val - 1); + if (ret) + return ret; + } + st->oversamp_ratio =3D val; + + return 0; +} + +static int ad4062_get_oversampling_ratio(struct ad4062_state *st, + unsigned int *val) +{ + int ret, buf; + + if (st->mode =3D=3D AD4062_SAMPLE_MODE) { + *val =3D 1; + return 0; + } + + ret =3D regmap_read(st->regmap, AD4062_REG_AVG_CONFIG, &buf); + if (ret) + return ret; + + *val =3D BIT(buf + 1); + return 0; +} + +static int ad4062_calc_sampling_frequency(unsigned int fosc, unsigned int = oversamp_ratio) +{ + /* From datasheet p.31: (n_avg - 1)/fosc + tconv */ + u32 n_avg =3D BIT(oversamp_ratio) - 1; + u32 period_ns =3D NSEC_PER_SEC / fosc; + + /* Result is less than 1 Hz */ + if (n_avg >=3D fosc) + return 1; + + return NSEC_PER_SEC / (n_avg * period_ns + AD4062_TCONV_NS); +} + +static int ad4062_populate_sampling_frequency(struct ad4062_state *st) +{ + for (u8 i =3D 0; i < ARRAY_SIZE(ad4062_conversion_freqs); i++) + st->samp_freqs[i] =3D + ad4062_calc_sampling_frequency(ad4062_conversion_freqs[i], + st->oversamp_ratio); + return 0; +} + +static int ad4062_get_sampling_frequency(struct ad4062_state *st, int *val) +{ + int freq =3D ad4062_conversion_freqs[st->sampling_frequency]; + + *val =3D ad4062_calc_sampling_frequency(freq, st->oversamp_ratio); + return 0; +} + +static int ad4062_set_sampling_frequency(struct ad4062_state *st, int val) +{ + int ret; + + ret =3D ad4062_populate_sampling_frequency(st); + if (ret) + return ret; + + st->sampling_frequency =3D find_closest_descending(val, st->samp_freqs, + ARRAY_SIZE(ad4062_conversion_freqs)); + return 0; +} + +static int ad4062_check_ids(struct ad4062_state *st) +{ + struct device *dev =3D &st->i3cdev->dev; + int ret; + u16 val; + + ret =3D regmap_bulk_read(st->regmap, AD4062_REG_PROD_ID_1, + &st->buf.be16, sizeof(st->buf.be16)); + if (ret) + return ret; + + val =3D get_unaligned_be16(st->buf.bytes); + if (val !=3D st->chip->prod_id) + dev_warn(dev, "Production ID x%x does not match known values", val); + + ret =3D regmap_bulk_read(st->regmap, AD4062_REG_VENDOR_H, + &st->buf.be16, sizeof(st->buf.be16)); + if (ret) + return ret; + + val =3D get_unaligned_be16(st->buf.bytes); + if (val !=3D AD4062_I3C_VENDOR) { + dev_err(dev, "Vendor ID x%x does not match expected value\n", val); + return -ENODEV; + } + + return 0; +} + +static int ad4062_set_operation_mode(struct ad4062_state *st, + enum ad4062_operation_mode mode) +{ + int ret; + + if (mode =3D=3D AD4062_BURST_AVERAGING_MODE) { + ret =3D ad4062_conversion_frequency_set(st, st->sampling_frequency); + if (ret) + return ret; + } + + ret =3D regmap_update_bits(st->regmap, AD4062_REG_ADC_MODES, + AD4062_REG_ADC_MODES_MODE_MSK, mode); + if (ret) + return ret; + + return regmap_write(st->regmap, AD4062_REG_MODE_SET, + AD4062_REG_MODE_SET_ENTER_ADC); +} + +static int ad4062_soft_reset(struct ad4062_state *st) +{ + u8 val =3D AD4062_SOFT_RESET; + int ret; + + ret =3D regmap_write(st->regmap, AD4062_REG_INTERFACE_CONFIG_A, val); + if (ret) + return ret; + + /* Wait AD4062 treset time, datasheet p8 */ + ndelay(60); + + return 0; +} + +static int ad4062_setup(struct iio_dev *indio_dev, struct iio_chan_spec co= nst *chan, + const bool *ref_sel) +{ + struct ad4062_state *st =3D iio_priv(indio_dev); + const struct iio_scan_type *scan_type; + int ret; + u8 val; + + scan_type =3D iio_get_current_scan_type(indio_dev, chan); + if (IS_ERR(scan_type)) + return PTR_ERR(scan_type); + + val =3D FIELD_PREP(AD4062_REG_GP_CONF_MODE_MSK_1, AD4062_GP_DRDY); + ret =3D regmap_update_bits(st->regmap, AD4062_REG_GP_CONF, + AD4062_REG_GP_CONF_MODE_MSK_1, val); + if (ret) + return ret; + + ret =3D regmap_update_bits(st->regmap, AD4062_REG_ADC_CONFIG, + AD4062_REG_ADC_CONFIG_REF_EN_MSK, + FIELD_PREP(AD4062_REG_ADC_CONFIG_REF_EN_MSK, + *ref_sel)); + if (ret) + return ret; + + ret =3D regmap_write(st->regmap, AD4062_REG_DEVICE_STATUS, + AD4062_REG_DEVICE_STATUS_DEVICE_RESET); + if (ret) + return ret; + + val =3D FIELD_PREP(AD4062_REG_INTR_CONF_EN_MSK_1, AD4062_INTR_EN_NEITHER); + ret =3D regmap_update_bits(st->regmap, AD4062_REG_INTR_CONF, + AD4062_REG_INTR_CONF_EN_MSK_1, val); + if (ret) + return ret; + + put_unaligned_be16(AD4062_MON_VAL_MIDDLE_POINT, st->buf.bytes); + return regmap_bulk_write(st->regmap, AD4062_REG_MON_VAL, + &st->buf.be16, sizeof(st->buf.be16)); +} + +static irqreturn_t ad4062_irq_handler_drdy(int irq, void *private) +{ + struct iio_dev *indio_dev =3D private; + struct ad4062_state *st =3D iio_priv(indio_dev); + + complete(&st->completion); + + return IRQ_HANDLED; +} + +static void ad4062_ibi_handler(struct i3c_device *i3cdev, + const struct i3c_ibi_payload *payload) +{ + struct ad4062_state *st =3D i3cdev_get_drvdata(i3cdev); + + complete(&st->completion); +} + +static void ad4062_remove_ibi(void *data) +{ + struct i3c_device *i3cdev =3D data; + + i3c_device_disable_ibi(i3cdev); + i3c_device_free_ibi(i3cdev); +} + +static int ad4062_request_ibi(struct i3c_device *i3cdev) +{ + const struct i3c_ibi_setup ibireq =3D { + .max_payload_len =3D 1, + .num_slots =3D 1, + .handler =3D ad4062_ibi_handler, + }; + int ret; + + ret =3D i3c_device_request_ibi(i3cdev, &ibireq); + if (ret) + return ret; + + ret =3D i3c_device_enable_ibi(i3cdev); + if (ret) + goto err_enable_ibi; + + return devm_add_action_or_reset(&i3cdev->dev, ad4062_remove_ibi, i3cdev); + +err_enable_ibi: + i3c_device_free_ibi(i3cdev); + return ret; +} + +static int ad4062_request_irq(struct iio_dev *indio_dev) +{ + struct ad4062_state *st =3D iio_priv(indio_dev); + struct device *dev =3D &st->i3cdev->dev; + int ret; + + ret =3D fwnode_irq_get_byname(dev_fwnode(&st->i3cdev->dev), "gp1"); + if (ret =3D=3D -EPROBE_DEFER) { + return ret; + } else if (ret < 0) { + return regmap_update_bits(st->regmap, AD4062_REG_ADC_IBI_EN, + AD4062_REG_ADC_IBI_EN_CONV_TRIGGER, + AD4062_REG_ADC_IBI_EN_CONV_TRIGGER); + } + return devm_request_threaded_irq(dev, ret, + ad4062_irq_handler_drdy, + NULL, IRQF_ONESHOT, indio_dev->name, + indio_dev); +} + +static const int ad4062_oversampling_avail[] =3D { + 1, 2, 4, 8, 16, 32, 64, 128, /* 0 - 7 */ + 256, 512, 1024, 2048, 4096, /* 8 - 12 */ +}; + +static int ad4062_read_avail(struct iio_dev *indio_dev, + struct iio_chan_spec const *chan, const int **vals, + int *type, int *len, long mask) +{ + struct ad4062_state *st =3D iio_priv(indio_dev); + int ret; + + switch (mask) { + case IIO_CHAN_INFO_OVERSAMPLING_RATIO: + *vals =3D ad4062_oversampling_avail; + *len =3D ARRAY_SIZE(ad4062_oversampling_avail); + *type =3D IIO_VAL_INT; + + return IIO_AVAIL_LIST; + case IIO_CHAN_INFO_SAMP_FREQ: + ret =3D ad4062_populate_sampling_frequency(st); + if (ret) + return ret; + *vals =3D st->samp_freqs; + *len =3D st->oversamp_ratio ? ARRAY_SIZE(ad4062_conversion_freqs) : 1; + *type =3D IIO_VAL_INT; + + return IIO_AVAIL_LIST; + default: + return -EINVAL; + } +} + +static int ad4062_get_chan_scale(struct iio_dev *indio_dev, int *val, int = *val2) +{ + struct ad4062_state *st =3D iio_priv(indio_dev); + const struct iio_scan_type *scan_type; + + scan_type =3D iio_get_current_scan_type(indio_dev, st->chip->channels); + if (IS_ERR(scan_type)) + return PTR_ERR(scan_type); + + *val =3D (st->vref_uV * 2) / (MICRO / MILLI); + + *val2 =3D scan_type->realbits - 1; /* signed */ + + return IIO_VAL_FRACTIONAL_LOG2; +} + +static int ad4062_get_chan_calibscale(struct ad4062_state *st, int *val, i= nt *val2) +{ + int ret; + + ret =3D regmap_bulk_read(st->regmap, AD4062_REG_MON_VAL, + &st->buf.be16, sizeof(st->buf.be16)); + if (ret) + return ret; + + /* From datasheet: code out =3D code in =C3=97 mon_val/0x8000 */ + *val =3D get_unaligned_be16(st->buf.bytes) * 2; + *val2 =3D 16; + + return IIO_VAL_FRACTIONAL_LOG2; +} + +static int ad4062_set_chan_calibscale(struct ad4062_state *st, int gain_in= t, + int gain_frac) +{ + /* Divide numerator and denumerator by known great common divider */ + const u32 mon_val =3D AD4062_MON_VAL_MIDDLE_POINT / 64; + const u32 micro =3D MICRO / 64; + const u32 gain_fp =3D gain_int * MICRO + gain_frac; + const u32 reg_val =3D DIV_ROUND_CLOSEST(gain_fp * mon_val, micro); + int ret; + + /* Checks if the gain is in range and the value fits the field */ + if (gain_int < 0 || gain_int > 1 || reg_val > BIT(16) - 1) + return -EINVAL; + + put_unaligned_be16(reg_val, st->buf.bytes); + ret =3D regmap_bulk_write(st->regmap, AD4062_REG_MON_VAL, + &st->buf.be16, sizeof(st->buf.be16)); + if (ret) + return ret; + + /* Enable scale if gain is not equal to one */ + return regmap_update_bits(st->regmap, AD4062_REG_ADC_CONFIG, + AD4062_REG_ADC_CONFIG_SCALE_EN_MSK, + FIELD_PREP(AD4062_REG_ADC_CONFIG_SCALE_EN_MSK, + !(gain_int =3D=3D 1 && gain_frac =3D=3D 0))); +} + +static int ad4062_read_chan_raw(struct ad4062_state *st, int *val) +{ + int ret; + struct i3c_device *i3cdev =3D st->i3cdev; + struct i3c_priv_xfer t0 =3D { + .data.out =3D &st->reg_addr_conv, + .len =3D sizeof(st->reg_addr_conv), + .rnw =3D false, + }; + struct i3c_priv_xfer t1 =3D { + .data.in =3D &st->buf.be32, + .len =3D sizeof(st->buf.be32), + .rnw =3D true, + }; + + ACQUIRE(pm_runtime_active_try_enabled, pm)(&st->i3cdev->dev); + ret =3D ACQUIRE_ERR(pm_runtime_active_try_enabled, &pm); + if (ret) + return ret; + + ret =3D ad4062_set_operation_mode(st, st->mode); + if (ret) + return ret; + + reinit_completion(&st->completion); + /* Change address pointer to trigger conversion */ + ret =3D i3c_device_do_priv_xfers(i3cdev, &t0, 1); + if (ret) + return ret; + /* + * Single sample read should be used only for oversampling and + * sampling frequency pairs that take less than 1 sec. + */ + ret =3D wait_for_completion_timeout(&st->completion, + msecs_to_jiffies(1000)); + if (!ret) + return -ETIMEDOUT; + + ret =3D i3c_device_do_priv_xfers(i3cdev, &t1, 1); + if (ret) + return ret; + *val =3D get_unaligned_be32(st->buf.bytes); + return 0; +} + +static int ad4062_read_raw_dispatch(struct ad4062_state *st, + int *val, int *val2, long info) +{ + switch (info) { + case IIO_CHAN_INFO_RAW: + return ad4062_read_chan_raw(st, val); + + case IIO_CHAN_INFO_CALIBSCALE: + return ad4062_get_chan_calibscale(st, val, val2); + + case IIO_CHAN_INFO_OVERSAMPLING_RATIO: + return ad4062_get_oversampling_ratio(st, val); + + case IIO_CHAN_INFO_SAMP_FREQ: + return ad4062_get_sampling_frequency(st, val); + + default: + return -EINVAL; + } +} + +static int ad4062_read_raw(struct iio_dev *indio_dev, + struct iio_chan_spec const *chan, + int *val, int *val2, long info) +{ + struct ad4062_state *st =3D iio_priv(indio_dev); + int ret; + + if (info =3D=3D IIO_CHAN_INFO_SCALE) + return ad4062_get_chan_scale(indio_dev, val, val2); + + if (!iio_device_claim_direct(indio_dev)) + return -EBUSY; + + ret =3D ad4062_read_raw_dispatch(st, val, val2, info); + + iio_device_release_direct(indio_dev); + return ret ?: IIO_VAL_INT; +} + +static int ad4062_write_raw_dispatch(struct ad4062_state *st, int val, int= val2, + long info) +{ + switch (info) { + case IIO_CHAN_INFO_OVERSAMPLING_RATIO: + return ad4062_set_oversampling_ratio(st, val); + + case IIO_CHAN_INFO_CALIBSCALE: + return ad4062_set_chan_calibscale(st, val, val2); + + case IIO_CHAN_INFO_SAMP_FREQ: + return ad4062_set_sampling_frequency(st, val); + + default: + return -EINVAL; + } +}; + +static int ad4062_write_raw(struct iio_dev *indio_dev, + struct iio_chan_spec const *chan, int val, + int val2, long info) +{ + struct ad4062_state *st =3D iio_priv(indio_dev); + int ret; + + if (!iio_device_claim_direct(indio_dev)) + return -EBUSY; + + ret =3D ad4062_write_raw_dispatch(st, val, val2, info); + + iio_device_release_direct(indio_dev); + return ret; +} + +static int ad4062_debugfs_reg_access(struct iio_dev *indio_dev, unsigned i= nt reg, + unsigned int writeval, unsigned int *readval) +{ + struct ad4062_state *st =3D iio_priv(indio_dev); + + if (readval) + return regmap_read(st->regmap, reg, readval); + else + return regmap_write(st->regmap, reg, writeval); +} + +static int ad4062_get_current_scan_type(const struct iio_dev *indio_dev, + const struct iio_chan_spec *chan) +{ + struct ad4062_state *st =3D iio_priv(indio_dev); + + return st->mode =3D=3D AD4062_BURST_AVERAGING_MODE ? + AD4062_SCAN_TYPE_BURST_AVG : + AD4062_SCAN_TYPE_SAMPLE; +} + +static const struct iio_info ad4062_info =3D { + .read_raw =3D ad4062_read_raw, + .write_raw =3D ad4062_write_raw, + .read_avail =3D ad4062_read_avail, + .get_current_scan_type =3D &ad4062_get_current_scan_type, + .debugfs_reg_access =3D &ad4062_debugfs_reg_access, +}; + +static const struct regmap_config ad4062_regmap_config =3D { + .name =3D "ad4062", + .reg_bits =3D 8, + .val_bits =3D 8, + .max_register =3D AD4062_MAX_REG, + .rd_table =3D &ad4062_regmap_rd_table, + .wr_table =3D &ad4062_regmap_wr_table, + .can_sleep =3D true, +}; + +static int ad4062_regulators_get(struct ad4062_state *st, bool *ref_sel) +{ + struct device *dev =3D &st->i3cdev->dev; + int ret; + + ret =3D devm_regulator_get_enable(dev, "vio"); + if (ret) + return dev_err_probe(dev, ret, + "Failed to enable vio voltage\n"); + + st->vref_uV =3D devm_regulator_get_enable_read_voltage(dev, "ref"); + *ref_sel =3D st->vref_uV =3D=3D -ENODEV; + if (st->vref_uV < 0 && !*ref_sel) { + return dev_err_probe(dev, st->vref_uV, + "Failed to enable and read ref voltage\n"); + } + + if (*ref_sel) { + st->vref_uV =3D devm_regulator_get_enable_read_voltage(dev, "vdd"); + if (st->vref_uV < 0) + return dev_err_probe(dev, st->vref_uV, + "Failed to enable and read vdd voltage\n"); + } else { + ret =3D devm_regulator_get_enable(dev, "vdd"); + if (ret) + return dev_err_probe(dev, ret, + "Failed to enable vdd regulator\n"); + } + + return 0; +} + +static const struct i3c_device_id ad4062_id_table[] =3D { + I3C_DEVICE(AD4062_I3C_VENDOR, ad4060_chip_info.prod_id, &ad4060_chip_info= ), + I3C_DEVICE(AD4062_I3C_VENDOR, ad4062_chip_info.prod_id, &ad4062_chip_info= ), + { } +}; +MODULE_DEVICE_TABLE(i3c, ad4062_id_table); + +static int ad4062_probe(struct i3c_device *i3cdev) +{ + const struct i3c_device_id *id =3D i3c_device_match_id(i3cdev, ad4062_id_= table); + const struct ad4062_chip_info *chip =3D id->data; + struct device *dev =3D &i3cdev->dev; + struct iio_dev *indio_dev; + struct ad4062_state *st; + bool ref_sel; + int ret; + + indio_dev =3D devm_iio_device_alloc(dev, sizeof(*st)); + if (!indio_dev) + return -ENOMEM; + + st =3D iio_priv(indio_dev); + st->i3cdev =3D i3cdev; + i3cdev_set_drvdata(i3cdev, st); + init_completion(&st->completion); + + ret =3D ad4062_regulators_get(st, &ref_sel); + if (ret) + return ret; + + st->regmap =3D devm_regmap_init_i3c(i3cdev, &ad4062_regmap_config); + if (IS_ERR(st->regmap)) + return dev_err_probe(dev, PTR_ERR(st->regmap), + "Failed to initialize regmap\n"); + + st->mode =3D AD4062_SAMPLE_MODE; + st->chip =3D chip; + st->sampling_frequency =3D 0; + st->oversamp_ratio =3D 0; + st->indio_dev =3D indio_dev; + st->reg_addr_conv =3D AD4062_REG_CONV_TRIGGER; + + indio_dev->modes =3D INDIO_DIRECT_MODE; + indio_dev->num_channels =3D 1; + indio_dev->info =3D &ad4062_info; + indio_dev->name =3D chip->name; + indio_dev->channels =3D chip->channels; + + ret =3D ad4062_soft_reset(st); + if (ret) + return dev_err_probe(dev, ret, "AD4062 failed to soft reset\n"); + + ret =3D ad4062_check_ids(st); + if (ret) + return ret; + + ret =3D ad4062_setup(indio_dev, indio_dev->channels, &ref_sel); + if (ret) + return ret; + + ret =3D ad4062_request_irq(indio_dev); + if (ret) + return ret; + + pm_runtime_set_active(dev); + ret =3D devm_pm_runtime_enable(dev); + if (ret) + return dev_err_probe(dev, ret, "Failed to enable pm_runtime\n"); + + pm_runtime_set_autosuspend_delay(dev, 1000); + pm_runtime_use_autosuspend(dev); + + ret =3D ad4062_request_ibi(i3cdev); + if (ret) + return dev_err_probe(dev, ret, "Failed to request i3c ibi\n"); + + return devm_iio_device_register(dev, indio_dev); +} + +static int ad4062_runtime_suspend(struct device *dev) +{ + struct ad4062_state *st =3D dev_get_drvdata(dev); + + return regmap_write(st->regmap, AD4062_REG_DEVICE_CONFIG, + FIELD_PREP(AD4062_REG_DEVICE_CONFIG_POWER_MODE_MSK, + AD4062_REG_DEVICE_CONFIG_LOW_POWER_MODE)); +} + +static int ad4062_runtime_resume(struct device *dev) +{ + struct ad4062_state *st =3D dev_get_drvdata(dev); + int ret; + + ret =3D regmap_clear_bits(st->regmap, AD4062_REG_DEVICE_CONFIG, + AD4062_REG_DEVICE_CONFIG_POWER_MODE_MSK); + if (ret) + return ret; + + /* Wait device functional blocks to power up */ + fsleep(2 * USEC_PER_MSEC); + return 0; +} + +static DEFINE_RUNTIME_DEV_PM_OPS(ad4062_pm_ops, + ad4062_runtime_suspend, ad4062_runtime_resume, NULL); + +static struct i3c_driver ad4062_driver =3D { + .driver =3D { + .name =3D "ad4062", + .pm =3D pm_ptr(&ad4062_pm_ops), + }, + .probe =3D ad4062_probe, + .id_table =3D ad4062_id_table, +}; +module_i3c_driver(ad4062_driver); + +MODULE_AUTHOR("Jorge Marques "); +MODULE_DESCRIPTION("Analog Devices AD4062"); +MODULE_LICENSE("GPL"); --=20 2.51.1 From nobody Thu Dec 18 09:27:40 2025 Received: from mx0b-00128a01.pphosted.com (mx0a-00128a01.pphosted.com [148.163.135.77]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C12B03164D4; Fri, 5 Dec 2025 15:13:02 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.163.135.77 ARC-Seal: i=1; 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Signed-off-by: Jorge Marques --- Documentation/iio/ad4062.rst | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/Documentation/iio/ad4062.rst b/Documentation/iio/ad4062.rst index e6bcca2bef24b..9dda4eb782a02 100644 --- a/Documentation/iio/ad4062.rst +++ b/Documentation/iio/ad4062.rst @@ -85,6 +85,19 @@ The device enters low-power mode on idle to save power. = Enabling an event puts the device out of the low-power since the ADC autonomously samples to asse= rt the event condition. =20 +IIO trigger support +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D + +An IIO trigger ``ad4062-devX`` is registered by the driver to be used by t= he +same device, to capture samples to a software buffer. It is required to at= tach +the trigger to the device by setting the ``current_trigger`` before enabli= ng +and reading the buffer. + +The acquisition is sequential and bounded by the protocol timings, software +latency and internal timings, the sample rate is not configurable. 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Fri, 5 Dec 2025 10:12:39 -0500 Received: from ASHBMBX9.ad.analog.com (10.64.17.10) by ASHBMBX9.ad.analog.com (10.64.17.10) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.37; Fri, 5 Dec 2025 10:12:39 -0500 Received: from zeus.spd.analog.com (10.66.68.11) by ashbmbx9.ad.analog.com (10.64.17.10) with Microsoft SMTP Server id 15.2.1748.37 via Frontend Transport; Fri, 5 Dec 2025 10:12:39 -0500 Received: from HYB-DlYm71t3hSl.ad.analog.com ([10.66.6.192]) by zeus.spd.analog.com (8.15.1/8.15.1) with ESMTP id 5B5FC8SF029946; Fri, 5 Dec 2025 10:12:32 -0500 From: Jorge Marques Date: Fri, 5 Dec 2025 16:12:06 +0100 Subject: [PATCH v3 5/9] iio: adc: ad4062: Add IIO Trigger support Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20251205-staging-ad4062-v3-5-8761355f9c66@analog.com> References: <20251205-staging-ad4062-v3-0-8761355f9c66@analog.com> In-Reply-To: <20251205-staging-ad4062-v3-0-8761355f9c66@analog.com> To: Lars-Peter Clausen , Michael Hennerich , Jonathan Cameron , David Lechner , =?utf-8?q?Nuno_S=C3=A1?= , Andy Shevchenko , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Jonathan Corbet , Linus Walleij , Bartosz Golaszewski CC: , , , , , Jorge Marques X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; 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Optionally, gp1 is assigned as Data Ready signal, if not present, fallback to an I3C IBI with the same role. The software trigger is allocated by the device, but must be attached by the user before enabling the buffer. The purpose is to not impede removing the driver due to the increased reference count when iio_trigger_set_immutable() or iio_trigger_get() is used. Signed-off-by: Jorge Marques --- drivers/iio/adc/Kconfig | 2 + drivers/iio/adc/ad4062.c | 188 +++++++++++++++++++++++++++++++++++++++++++= ---- 2 files changed, 175 insertions(+), 15 deletions(-) diff --git a/drivers/iio/adc/Kconfig b/drivers/iio/adc/Kconfig index e506dbe83f488..ddb7820f0bdcc 100644 --- a/drivers/iio/adc/Kconfig +++ b/drivers/iio/adc/Kconfig @@ -74,6 +74,8 @@ config AD4062 tristate "Analog Devices AD4062 Driver" depends on I3C select REGMAP_I3C + select IIO_BUFFER + select IIO_TRIGGERED_BUFFER help Say yes here to build support for Analog Devices AD4062 I3C analog to digital converters (ADC). diff --git a/drivers/iio/adc/ad4062.c b/drivers/iio/adc/ad4062.c index 54f7f69e40879..080dc80fd1621 100644 --- a/drivers/iio/adc/ad4062.c +++ b/drivers/iio/adc/ad4062.c @@ -9,11 +9,16 @@ #include #include #include +#include #include #include #include +#include #include #include +#include +#include +#include #include #include #include @@ -60,6 +65,7 @@ #define AD4062_REG_DEVICE_STATUS_DEVICE_RESET BIT(6) #define AD4062_REG_IBI_STATUS 0x48 #define AD4062_REG_CONV_READ_LSB 0x50 +#define AD4062_REG_CONV_READ 0x53 #define AD4062_REG_CONV_TRIGGER 0x59 #define AD4062_REG_CONV_AUTO 0x61 #define AD4062_MAX_REG AD4062_REG_CONV_AUTO @@ -137,6 +143,7 @@ struct ad4062_state { const struct ad4062_chip_info *chip; const struct ad4062_bus_ops *ops; enum ad4062_operation_mode mode; + struct work_struct trig_conv; struct completion completion; struct iio_trigger *trigger; struct iio_dev *indio_dev; @@ -144,6 +151,7 @@ struct ad4062_state { struct regmap *regmap; int vref_uV; unsigned int samp_freqs[ARRAY_SIZE(ad4062_conversion_freqs)]; + bool gpo_irq[2]; union { __be32 be32; __be16 be16; @@ -411,7 +419,10 @@ static irqreturn_t ad4062_irq_handler_drdy(int irq, vo= id *private) struct iio_dev *indio_dev =3D private; struct ad4062_state *st =3D iio_priv(indio_dev); =20 - complete(&st->completion); + if (iio_buffer_enabled(indio_dev) && iio_trigger_using_own(indio_dev)) + iio_trigger_poll(st->trigger); + else + complete(&st->completion); =20 return IRQ_HANDLED; } @@ -421,7 +432,57 @@ static void ad4062_ibi_handler(struct i3c_device *i3cd= ev, { struct ad4062_state *st =3D i3cdev_get_drvdata(i3cdev); =20 - complete(&st->completion); + if (iio_buffer_enabled(st->indio_dev)) + iio_trigger_poll_nested(st->trigger); + else + complete(&st->completion); +} + +static void ad4062_trigger_work(struct work_struct *work) +{ + struct ad4062_state *st =3D + container_of(work, struct ad4062_state, trig_conv); + int ret; + + /* + * Read current conversion, if at reg CONV_READ, stop bit triggers + * next sample and does not need writing the address. + */ + struct i3c_priv_xfer t[2] =3D { + { + .data.in =3D &st->buf.be32, + .len =3D sizeof(st->buf.be32), + .rnw =3D true, + }, + { + .data.out =3D &st->reg_addr_conv, + .len =3D sizeof(st->reg_addr_conv), + .rnw =3D false, + }, + }; + + ret =3D i3c_device_do_priv_xfers(st->i3cdev, &t[0], 1); + if (ret) + return; + + iio_push_to_buffers_with_timestamp(st->indio_dev, &st->buf.be32, + iio_get_time_ns(st->indio_dev)); + if (st->gpo_irq[1]) + return; + + i3c_device_do_priv_xfers(st->i3cdev, &t[1], 1); +} + +static irqreturn_t ad4062_poll_handler(int irq, void *p) +{ + struct iio_poll_func *pf =3D p; + struct iio_dev *indio_dev =3D pf->indio_dev; + struct ad4062_state *st =3D iio_priv(indio_dev); + + iio_trigger_notify_done(indio_dev->trig); + schedule_work(&st->trig_conv); + + return IRQ_HANDLED; } =20 static void ad4062_remove_ibi(void *data) @@ -466,16 +527,48 @@ static int ad4062_request_irq(struct iio_dev *indio_d= ev) if (ret =3D=3D -EPROBE_DEFER) { return ret; } else if (ret < 0) { + st->gpo_irq[1] =3D false; + st->reg_addr_conv =3D AD4062_REG_CONV_TRIGGER; return regmap_update_bits(st->regmap, AD4062_REG_ADC_IBI_EN, AD4062_REG_ADC_IBI_EN_CONV_TRIGGER, AD4062_REG_ADC_IBI_EN_CONV_TRIGGER); } + st->gpo_irq[1] =3D true; + st->reg_addr_conv =3D AD4062_REG_CONV_READ; return devm_request_threaded_irq(dev, ret, ad4062_irq_handler_drdy, NULL, IRQF_ONESHOT, indio_dev->name, indio_dev); } =20 +static const struct iio_trigger_ops ad4062_trigger_ops =3D { + .validate_device =3D &iio_trigger_validate_own_device, +}; + +static int ad4062_request_trigger(struct iio_dev *indio_dev) +{ + struct ad4062_state *st =3D iio_priv(indio_dev); + struct device *dev =3D &st->i3cdev->dev; + int ret; + + st->trigger =3D devm_iio_trigger_alloc(dev, "%s-dev%d", + indio_dev->name, + iio_device_id(indio_dev)); + if (!st->trigger) + return -ENOMEM; + + st->trigger->ops =3D &ad4062_trigger_ops; + iio_trigger_set_drvdata(st->trigger, indio_dev); + + ret =3D devm_iio_trigger_register(dev, st->trigger); + if (ret) + return ret; + + indio_dev->trig =3D iio_trigger_get(st->trigger); + + return 0; +} + static const int ad4062_oversampling_avail[] =3D { 1, 2, 4, 8, 16, 32, 64, 128, /* 0 - 7 */ 256, 512, 1024, 2048, 4096, /* 8 - 12 */ @@ -572,15 +665,17 @@ static int ad4062_read_chan_raw(struct ad4062_state *= st, int *val) { int ret; struct i3c_device *i3cdev =3D st->i3cdev; - struct i3c_priv_xfer t0 =3D { - .data.out =3D &st->reg_addr_conv, - .len =3D sizeof(st->reg_addr_conv), - .rnw =3D false, - }; - struct i3c_priv_xfer t1 =3D { - .data.in =3D &st->buf.be32, - .len =3D sizeof(st->buf.be32), - .rnw =3D true, + struct i3c_priv_xfer t[] =3D { + { + .data.out =3D &st->reg_addr_conv, + .len =3D sizeof(st->reg_addr_conv), + .rnw =3D false, + }, + { + .data.in =3D &st->buf.be32, + .len =3D sizeof(st->buf.be32), + .rnw =3D true, + } }; =20 ACQUIRE(pm_runtime_active_try_enabled, pm)(&st->i3cdev->dev); @@ -593,8 +688,8 @@ static int ad4062_read_chan_raw(struct ad4062_state *st= , int *val) return ret; =20 reinit_completion(&st->completion); - /* Change address pointer to trigger conversion */ - ret =3D i3c_device_do_priv_xfers(i3cdev, &t0, 1); + /* Change address pointer (and read if CONV_READ) to trigger conversion. = */ + ret =3D i3c_device_do_priv_xfers(i3cdev, t, st->gpo_irq[1] ? 2 : 1); if (ret) return ret; /* @@ -606,7 +701,7 @@ static int ad4062_read_chan_raw(struct ad4062_state *st= , int *val) if (!ret) return -ETIMEDOUT; =20 - ret =3D i3c_device_do_priv_xfers(i3cdev, &t1, 1); + ret =3D i3c_device_do_priv_xfers(i3cdev, &t[1], 1); if (ret) return ret; *val =3D get_unaligned_be32(st->buf.bytes); @@ -687,6 +782,55 @@ static int ad4062_write_raw(struct iio_dev *indio_dev, return ret; } =20 +static int ad4062_triggered_buffer_postenable(struct iio_dev *indio_dev) +{ + struct ad4062_state *st =3D iio_priv(indio_dev); + int ret; + + ACQUIRE(pm_runtime_active_try_enabled, pm)(&st->i3cdev->dev); + ret =3D ACQUIRE_ERR(pm_runtime_active_try_enabled, &pm); + if (ret) + return ret; + + ret =3D ad4062_set_operation_mode(st, st->mode); + if (ret) + return ret; + + /* CONV_READ requires read to trigger first sample. */ + struct i3c_priv_xfer t[2] =3D { + { + .data.out =3D &st->reg_addr_conv, + .len =3D sizeof(st->reg_addr_conv), + .rnw =3D false, + }, + { + .data.in =3D &st->buf.be32, + .len =3D sizeof(st->buf.be32), + .rnw =3D true, + } + }; + + ret =3D i3c_device_do_priv_xfers(st->i3cdev, t, st->gpo_irq[1] ? 2 : 1); + if (ret) + return ret; + + pm_runtime_get_noresume(&st->i3cdev->dev); + return 0; +} + +static int ad4062_triggered_buffer_predisable(struct iio_dev *indio_dev) +{ + struct ad4062_state *st =3D iio_priv(indio_dev); + + pm_runtime_put_autosuspend(&st->i3cdev->dev); + return 0; +} + +static const struct iio_buffer_setup_ops ad4062_triggered_buffer_setup_ops= =3D { + .postenable =3D &ad4062_triggered_buffer_postenable, + .predisable =3D &ad4062_triggered_buffer_predisable, +}; + static int ad4062_debugfs_reg_access(struct iio_dev *indio_dev, unsigned i= nt reg, unsigned int writeval, unsigned int *readval) { @@ -798,7 +942,6 @@ static int ad4062_probe(struct i3c_device *i3cdev) st->sampling_frequency =3D 0; st->oversamp_ratio =3D 0; st->indio_dev =3D indio_dev; - st->reg_addr_conv =3D AD4062_REG_CONV_TRIGGER; =20 indio_dev->modes =3D INDIO_DIRECT_MODE; indio_dev->num_channels =3D 1; @@ -822,6 +965,17 @@ static int ad4062_probe(struct i3c_device *i3cdev) if (ret) return ret; =20 + ret =3D ad4062_request_trigger(indio_dev); + if (ret) + return ret; + + ret =3D devm_iio_triggered_buffer_setup(&i3cdev->dev, indio_dev, + iio_pollfunc_store_time, + ad4062_poll_handler, + &ad4062_triggered_buffer_setup_ops); + if (ret) + return ret; + pm_runtime_set_active(dev); ret =3D devm_pm_runtime_enable(dev); if (ret) @@ -834,6 +988,10 @@ static int ad4062_probe(struct i3c_device *i3cdev) if (ret) return dev_err_probe(dev, ret, "Failed to request i3c ibi\n"); =20 + ret =3D devm_work_autocancel(dev, &st->trig_conv, ad4062_trigger_work); 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Signed-off-by: Jorge Marques --- Documentation/iio/ad4062.rst | 42 +++++++++++++++++++++++++++++++++++++++-= -- 1 file changed, 39 insertions(+), 3 deletions(-) diff --git a/Documentation/iio/ad4062.rst b/Documentation/iio/ad4062.rst index 9dda4eb782a02..5afec4d8c2ddb 100644 --- a/Documentation/iio/ad4062.rst +++ b/Documentation/iio/ad4062.rst @@ -26,6 +26,7 @@ at the end of the read command. The two programmable GPIOS are optional and have a role assigned if presen= t in the devicetree ``interrupt-names`` property: =20 +- GP0: Is assigned the role of Threshold Either signal. - GP1: Is assigned the role of Data Ready signal. =20 Device attributes @@ -74,8 +75,10 @@ Interrupts The interrupts are mapped through the ``interrupt-names`` and ``interrupts= `` properties. =20 -The ``interrupt-names`` ``gp1`` entry sets the role of Data Ready signal. -If it is not present, the driver fallback to enabling the same role as an +The ``interrupt-names`` ``gp0`` entry sets the role of Threshold signal, a= nd +entry ``gp1`` the role of Data Ready signal. + +If each is not present, the driver fallback to enabling the same role as an I3C IBI. =20 Low-power mode @@ -98,10 +101,43 @@ latency and internal timings, the sample rate is not c= onfigurable. The burst averaging mode does impact the effective sample rate, since it increases t= he internal timing to output a single sample. =20 +Threshold events +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D + +The ADC supports a monitoring mode to raise threshold events. The driver +supports a single interrupt for both rising and falling readings. + +The feature is enabled/disabled by setting ``thresh_either_en``. During mo= nitor +mode, the device continuously operates in autonomous mode. Any register ac= cess +puts the device back in configuration mode, due to this, any access disabl= es +monitor mode. + +The following event attributes are available: + +.. list-table:: Event attributes + :header-rows: 1 + + * - Attribute + - Description + * - ``sampling_frequency`` + - Frequency used in the monitoring mode, sets the device internal sam= ple + rate when the mode is activated. + * - ``sampling_frequency_available`` + - List of available sample rates. + * - ``thresh_either_en`` + - Enable monitoring mode. + * - ``thresh_falling_hysteresis`` + - Set the hysteresis value for the minimum threshold. + * - ``thresh_falling_value`` + - Set the minimum threshold value. + * - ``thresh_rising_hysteresis`` + - Set the hysteresis value for the maximum threshold. + * - ``thresh_rising_value`` + - Set the maximum threshold value. + Unimplemented features =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D =20 -- Monitor mode - Trigger mode - Averaging mode - General purpose output --=20 2.51.1 From nobody Thu Dec 18 09:27:40 2025 Received: from mx0a-00128a01.pphosted.com (mx0a-00128a01.pphosted.com [148.163.135.77]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 510CF34F470; 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Fri, 5 Dec 2025 10:12:37 -0500 From: Jorge Marques Date: Fri, 5 Dec 2025 16:12:08 +0100 Subject: [PATCH v3 7/9] iio: adc: ad4062: Add IIO Events support Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20251205-staging-ad4062-v3-7-8761355f9c66@analog.com> References: <20251205-staging-ad4062-v3-0-8761355f9c66@analog.com> In-Reply-To: <20251205-staging-ad4062-v3-0-8761355f9c66@analog.com> To: Lars-Peter Clausen , Michael Hennerich , Jonathan Cameron , "David Lechner" , =?utf-8?q?Nuno_S=C3=A1?= , Andy Shevchenko , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Jonathan Corbet , Linus Walleij , Bartosz Golaszewski CC: , , , , , Jorge Marques X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1764947528; l=15664; i=jorge.marques@analog.com; s=20250303; h=from:subject:message-id; bh=VqhcHJ+8/Pojy4IeBtkQj+MRFHp3xzlpGLBpLMOTnaw=; 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Optionally, gp0 is assigned as Threshold Either signal, if not present, fallback to an I3C IBI with the same role. Signed-off-by: Jorge Marques --- drivers/iio/adc/ad4062.c | 376 +++++++++++++++++++++++++++++++++++++++++++= +++- 1 file changed, 372 insertions(+), 4 deletions(-) diff --git a/drivers/iio/adc/ad4062.c b/drivers/iio/adc/ad4062.c index 080dc80fd1621..e432aa60a224e 100644 --- a/drivers/iio/adc/ad4062.c +++ b/drivers/iio/adc/ad4062.c @@ -14,6 +14,7 @@ #include #include #include +#include #include #include #include @@ -52,14 +53,22 @@ #define AD4062_REG_ADC_CONFIG_SCALE_EN_MSK BIT(4) #define AD4062_REG_AVG_CONFIG 0x23 #define AD4062_REG_GP_CONF 0x24 +#define AD4062_REG_GP_CONF_MODE_MSK_0 GENMASK(2, 0) #define AD4062_REG_GP_CONF_MODE_MSK_1 GENMASK(6, 4) #define AD4062_REG_INTR_CONF 0x25 +#define AD4062_REG_INTR_CONF_EN_MSK_0 GENMASK(1, 0) #define AD4062_REG_INTR_CONF_EN_MSK_1 GENMASK(5, 4) #define AD4062_REG_TIMER_CONFIG 0x27 #define AD4062_REG_TIMER_CONFIG_FS_MASK GENMASK(7, 4) +#define AD4062_REG_MAX_LIMIT 0x29 +#define AD4062_REG_MIN_LIMIT 0x2B +#define AD4062_REG_MAX_HYST 0x2C +#define AD4062_REG_MIN_HYST 0x2D #define AD4062_REG_MON_VAL 0x2F #define AD4062_REG_ADC_IBI_EN 0x31 #define AD4062_REG_ADC_IBI_EN_CONV_TRIGGER BIT(2) +#define AD4062_REG_ADC_IBI_EN_MAX BIT(1) +#define AD4062_REG_ADC_IBI_EN_MIN BIT(0) #define AD4062_REG_FUSE_CRC 0x40 #define AD4062_REG_DEVICE_STATUS 0x41 #define AD4062_REG_DEVICE_STATUS_DEVICE_RESET BIT(6) @@ -78,9 +87,13 @@ #define AD4060_MAX_AVG 0x7 #define AD4062_MAX_AVG 0xB =20 +#define AD4062_GP_INTR 0x1 #define AD4062_GP_DRDY 0x2 =20 +#define AD4062_LIMIT_BITS 11 + #define AD4062_INTR_EN_NEITHER 0x0 +#define AD4062_INTR_EN_EITHER 0x3 =20 #define AD4062_TCONV_NS 270 =20 @@ -149,6 +162,7 @@ struct ad4062_state { struct iio_dev *indio_dev; struct i3c_device *i3cdev; struct regmap *regmap; + bool wait_event; int vref_uV; unsigned int samp_freqs[ARRAY_SIZE(ad4062_conversion_freqs)]; bool gpo_irq[2]; @@ -158,6 +172,7 @@ struct ad4062_state { u8 bytes[4]; } buf __aligned(IIO_DMA_MINALIGN); u16 sampling_frequency; + u16 events_frequency; u8 oversamp_ratio; u8 reg_addr_conv; }; @@ -188,6 +203,26 @@ static const struct regmap_access_table ad4062_regmap_= wr_table =3D { .n_yes_ranges =3D ARRAY_SIZE(ad4062_regmap_wr_ranges), }; =20 +static const struct iio_event_spec ad4062_events[] =3D { + { + .type =3D IIO_EV_TYPE_THRESH, + .dir =3D IIO_EV_DIR_EITHER, + .mask_shared_by_all =3D BIT(IIO_EV_INFO_ENABLE), + }, + { + .type =3D IIO_EV_TYPE_THRESH, + .dir =3D IIO_EV_DIR_RISING, + .mask_shared_by_all =3D BIT(IIO_EV_INFO_VALUE) | + BIT(IIO_EV_INFO_HYSTERESIS), + }, + { + .type =3D IIO_EV_TYPE_THRESH, + .dir =3D IIO_EV_DIR_FALLING, + .mask_shared_by_all =3D BIT(IIO_EV_INFO_VALUE) | + BIT(IIO_EV_INFO_HYSTERESIS), + }, +}; + static int ad4062_conversion_frequency_set(struct ad4062_state *st, u8 val) { return regmap_write(st->regmap, AD4062_REG_TIMER_CONFIG, @@ -205,6 +240,8 @@ static int ad4062_conversion_frequency_set(struct ad406= 2_state *st, u8 val) .info_mask_shared_by_all_available =3D BIT(IIO_CHAN_INFO_SAMP_FREQ), \ .indexed =3D 1, \ .channel =3D 0, \ + .event_spec =3D ad4062_events, \ + .num_event_specs =3D ARRAY_SIZE(ad4062_events), \ .has_ext_scan_type =3D 1, \ .ext_scan_type =3D ad4062_scan_type_##bits##_s, \ .num_ext_scan_type =3D ARRAY_SIZE(ad4062_scan_type_##bits##_s), \ @@ -224,6 +261,68 @@ static const struct ad4062_chip_info ad4062_chip_info = =3D { .max_avg =3D AD4062_MAX_AVG, }; =20 +static ssize_t sampling_frequency_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct ad4062_state *st =3D iio_priv(dev_to_iio_dev(dev)); + + return sysfs_emit(buf, "%d\n", ad4062_conversion_freqs[st->events_frequen= cy]); +} + +static ssize_t sampling_frequency_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t len) +{ + struct iio_dev *indio_dev =3D dev_to_iio_dev(dev); + struct ad4062_state *st =3D iio_priv(indio_dev); + int val, ret; + + if (!iio_device_claim_direct(indio_dev)) + return -EBUSY; + if (st->wait_event) { + ret =3D -EBUSY; + goto out_release; + } + + ret =3D kstrtoint(buf, 10, &val); + if (ret < 0) + goto out_release; + + st->events_frequency =3D find_closest_descending(val, ad4062_conversion_f= reqs, + ARRAY_SIZE(ad4062_conversion_freqs)); + ret =3D 0; + +out_release: + iio_device_release_direct(indio_dev); + return ret ?: len; +} + +static IIO_DEVICE_ATTR_RW(sampling_frequency, 0); + +static ssize_t sampling_frequency_available_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + int ret =3D 0; + + for (u8 i =3D 0; i < ARRAY_SIZE(ad4062_conversion_freqs); i++) + ret +=3D sysfs_emit_at(buf, ret, "%d%s", ad4062_conversion_freqs[i], + i !=3D (ARRAY_SIZE(ad4062_conversion_freqs) - 1) ? " " : "\n"); + return ret; +} + +static IIO_DEVICE_ATTR_RO(sampling_frequency_available, 0); + +static struct attribute *ad4062_event_attributes[] =3D { + &iio_dev_attr_sampling_frequency.dev_attr.attr, + &iio_dev_attr_sampling_frequency_available.dev_attr.attr, + NULL +}; + +static const struct attribute_group ad4062_event_attribute_group =3D { + .attrs =3D ad4062_event_attributes, +}; + static int ad4062_set_oversampling_ratio(struct ad4062_state *st, unsigned= int val) { const u32 _max =3D GENMASK(st->chip->max_avg, 0) + 1; @@ -385,9 +484,12 @@ static int ad4062_setup(struct iio_dev *indio_dev, str= uct iio_chan_spec const *c if (IS_ERR(scan_type)) return PTR_ERR(scan_type); =20 - val =3D FIELD_PREP(AD4062_REG_GP_CONF_MODE_MSK_1, AD4062_GP_DRDY); + val =3D FIELD_PREP(AD4062_REG_GP_CONF_MODE_MSK_0, AD4062_GP_INTR) | + FIELD_PREP(AD4062_REG_GP_CONF_MODE_MSK_1, AD4062_GP_DRDY); + ret =3D regmap_update_bits(st->regmap, AD4062_REG_GP_CONF, - AD4062_REG_GP_CONF_MODE_MSK_1, val); + AD4062_REG_GP_CONF_MODE_MSK_1 | AD4062_REG_GP_CONF_MODE_MSK_0, + val); if (ret) return ret; =20 @@ -403,9 +505,11 @@ static int ad4062_setup(struct iio_dev *indio_dev, str= uct iio_chan_spec const *c if (ret) return ret; =20 - val =3D FIELD_PREP(AD4062_REG_INTR_CONF_EN_MSK_1, AD4062_INTR_EN_NEITHER); + val =3D FIELD_PREP(AD4062_REG_INTR_CONF_EN_MSK_0, AD4062_INTR_EN_EITHER) | + FIELD_PREP(AD4062_REG_INTR_CONF_EN_MSK_1, AD4062_INTR_EN_NEITHER); ret =3D regmap_update_bits(st->regmap, AD4062_REG_INTR_CONF, - AD4062_REG_INTR_CONF_EN_MSK_1, val); + AD4062_REG_INTR_CONF_EN_MSK_0 | AD4062_REG_INTR_CONF_EN_MSK_1, + val); if (ret) return ret; =20 @@ -414,6 +518,19 @@ static int ad4062_setup(struct iio_dev *indio_dev, str= uct iio_chan_spec const *c &st->buf.be16, sizeof(st->buf.be16)); } =20 +static irqreturn_t ad4062_irq_handler_thresh(int irq, void *private) +{ + struct iio_dev *indio_dev =3D private; + + iio_push_event(indio_dev, + IIO_UNMOD_EVENT_CODE(IIO_VOLTAGE, 0, + IIO_EV_TYPE_THRESH, + IIO_EV_DIR_EITHER), + iio_get_time_ns(indio_dev)); + + return IRQ_HANDLED; +} + static irqreturn_t ad4062_irq_handler_drdy(int irq, void *private) { struct iio_dev *indio_dev =3D private; @@ -432,6 +549,14 @@ static void ad4062_ibi_handler(struct i3c_device *i3cd= ev, { struct ad4062_state *st =3D i3cdev_get_drvdata(i3cdev); =20 + if (st->wait_event) { + iio_push_event(st->indio_dev, + IIO_UNMOD_EVENT_CODE(IIO_VOLTAGE, 0, + IIO_EV_TYPE_THRESH, + IIO_EV_DIR_EITHER), + iio_get_time_ns(st->indio_dev)); + return; + } if (iio_buffer_enabled(st->indio_dev)) iio_trigger_poll_nested(st->trigger); else @@ -523,6 +648,24 @@ static int ad4062_request_irq(struct iio_dev *indio_de= v) struct device *dev =3D &st->i3cdev->dev; int ret; =20 + ret =3D fwnode_irq_get_byname(dev_fwnode(&st->i3cdev->dev), "gp0"); + if (ret =3D=3D -EPROBE_DEFER) { + return ret; + } else if (ret < 0) { + ret =3D regmap_update_bits(st->regmap, AD4062_REG_ADC_IBI_EN, + AD4062_REG_ADC_IBI_EN_MAX | AD4062_REG_ADC_IBI_EN_MIN, + AD4062_REG_ADC_IBI_EN_MAX | AD4062_REG_ADC_IBI_EN_MIN); + if (ret) + return ret; + } else { + ret =3D devm_request_threaded_irq(dev, ret, NULL, + ad4062_irq_handler_thresh, + IRQF_ONESHOT, indio_dev->name, + indio_dev); + if (ret) + return ret; + } + ret =3D fwnode_irq_get_byname(dev_fwnode(&st->i3cdev->dev), "gp1"); if (ret =3D=3D -EPROBE_DEFER) { return ret; @@ -741,9 +884,14 @@ static int ad4062_read_raw(struct iio_dev *indio_dev, =20 if (!iio_device_claim_direct(indio_dev)) return -EBUSY; + if (st->wait_event) { + ret =3D -EBUSY; + goto out_release; + } =20 ret =3D ad4062_read_raw_dispatch(st, val, val2, info); =20 +out_release: iio_device_release_direct(indio_dev); return ret ?: IIO_VAL_INT; } @@ -775,9 +923,219 @@ static int ad4062_write_raw(struct iio_dev *indio_dev, =20 if (!iio_device_claim_direct(indio_dev)) return -EBUSY; + if (st->wait_event) { + ret =3D -EBUSY; + goto out_release; + } =20 ret =3D ad4062_write_raw_dispatch(st, val, val2, info); =20 +out_release: + iio_device_release_direct(indio_dev); + return ret; +} + +static int ad4062_monitor_mode_enable(struct ad4062_state *st) +{ + int ret; + + ACQUIRE(pm_runtime_active_try_enabled, pm)(&st->i3cdev->dev); + ret =3D ACQUIRE_ERR(pm_runtime_active_try_enabled, &pm); + if (ret) + return ret; + + ret =3D ad4062_conversion_frequency_set(st, st->events_frequency); + if (ret) + return ret; + + ret =3D ad4062_set_operation_mode(st, AD4062_MONITOR_MODE); + if (ret) + return ret; + + pm_runtime_get_noresume(&st->i3cdev->dev); + return 0; +} + +static int ad4062_monitor_mode_disable(struct ad4062_state *st) +{ + pm_runtime_put_autosuspend(&st->i3cdev->dev); + return 0; +} + +static int ad4062_read_event_config(struct iio_dev *indio_dev, + const struct iio_chan_spec *chan, + enum iio_event_type type, + enum iio_event_direction dir) +{ + struct ad4062_state *st =3D iio_priv(indio_dev); + + return st->wait_event; +} + +static int ad4062_write_event_config(struct iio_dev *indio_dev, + const struct iio_chan_spec *chan, + enum iio_event_type type, + enum iio_event_direction dir, + bool state) +{ + struct ad4062_state *st =3D iio_priv(indio_dev); + int ret; + + if (!iio_device_claim_direct(indio_dev)) + return -EBUSY; + if (st->wait_event =3D=3D state) + ret =3D 0; + else if (state) + ret =3D ad4062_monitor_mode_enable(st); + else + ret =3D ad4062_monitor_mode_disable(st); + if (ret) + goto out_release; + + st->wait_event =3D state; + +out_release: + iio_device_release_direct(indio_dev); + return ret; +} + +static int __ad4062_read_event_info_value(struct ad4062_state *st, + enum iio_event_direction dir, int *val) +{ + int ret; + u8 reg; + + if (dir =3D=3D IIO_EV_DIR_RISING) + reg =3D AD4062_REG_MAX_LIMIT; + else + reg =3D AD4062_REG_MIN_LIMIT; + + ret =3D regmap_bulk_read(st->regmap, reg, &st->buf.be16, + sizeof(st->buf.be16)); + if (ret) + return ret; + + *val =3D sign_extend32(get_unaligned_be16(st->buf.bytes), + AD4062_LIMIT_BITS - 1); + + return 0; +} + +static int __ad4062_read_event_info_hysteresis(struct ad4062_state *st, + enum iio_event_direction dir, int *val) +{ + u8 reg; + + if (dir =3D=3D IIO_EV_DIR_RISING) + reg =3D AD4062_REG_MAX_HYST; + else + reg =3D AD4062_REG_MIN_HYST; + return regmap_read(st->regmap, reg, val); +} + +static int ad4062_read_event_value(struct iio_dev *indio_dev, + const struct iio_chan_spec *chan, + enum iio_event_type type, + enum iio_event_direction dir, + enum iio_event_info info, int *val, + int *val2) +{ + struct ad4062_state *st =3D iio_priv(indio_dev); + int ret; + + if (!iio_device_claim_direct(indio_dev)) + return -EBUSY; + if (st->wait_event) { + ret =3D -EBUSY; + goto out_release; + } + + switch (info) { + case IIO_EV_INFO_VALUE: + ret =3D __ad4062_read_event_info_value(st, dir, val); + break; + case IIO_EV_INFO_HYSTERESIS: + ret =3D __ad4062_read_event_info_hysteresis(st, dir, val); + break; + default: + ret =3D -EINVAL; + break; + } + +out_release: + iio_device_release_direct(indio_dev); + return ret ?: IIO_VAL_INT; +} + +static int __ad4062_write_event_info_value(struct ad4062_state *st, + enum iio_event_direction dir, int val) +{ + u8 reg; + + if (val !=3D sign_extend32(val, AD4062_LIMIT_BITS - 1)) + return -EINVAL; + if (dir =3D=3D IIO_EV_DIR_RISING) + reg =3D AD4062_REG_MAX_LIMIT; + else + reg =3D AD4062_REG_MIN_LIMIT; + put_unaligned_be16(val, st->buf.bytes); + + return regmap_bulk_write(st->regmap, reg, &st->buf.be16, + sizeof(st->buf.be16)); +} + +static int __ad4062_write_event_info_hysteresis(struct ad4062_state *st, + enum iio_event_direction dir, int val) +{ + u8 reg; + + if (val > BIT(7) - 1) + return -EINVAL; + if (dir =3D=3D IIO_EV_DIR_RISING) + reg =3D AD4062_REG_MAX_HYST; + else + reg =3D AD4062_REG_MIN_HYST; + + return regmap_write(st->regmap, reg, val); +} + +static int ad4062_write_event_value(struct iio_dev *indio_dev, + const struct iio_chan_spec *chan, + enum iio_event_type type, + enum iio_event_direction dir, + enum iio_event_info info, int val, + int val2) +{ + struct ad4062_state *st =3D iio_priv(indio_dev); + int ret; + + if (!iio_device_claim_direct(indio_dev)) + return -EBUSY; + if (st->wait_event) { + ret =3D -EBUSY; + goto out_release; + } + + switch (type) { + case IIO_EV_TYPE_THRESH: + switch (info) { + case IIO_EV_INFO_VALUE: + ret =3D __ad4062_write_event_info_value(st, dir, val); + break; + case IIO_EV_INFO_HYSTERESIS: + ret =3D __ad4062_write_event_info_hysteresis(st, dir, val); + break; + default: + ret =3D -EINVAL; + break; + } + break; + default: + ret =3D -EINVAL; + break; + } + +out_release: iio_device_release_direct(indio_dev); return ret; } @@ -792,6 +1150,9 @@ static int ad4062_triggered_buffer_postenable(struct i= io_dev *indio_dev) if (ret) return ret; =20 + if (st->wait_event) + return -EBUSY; + ret =3D ad4062_set_operation_mode(st, st->mode); if (ret) return ret; @@ -856,6 +1217,11 @@ static const struct iio_info ad4062_info =3D { .read_raw =3D ad4062_read_raw, .write_raw =3D ad4062_write_raw, .read_avail =3D ad4062_read_avail, + .read_event_config =3D &ad4062_read_event_config, + .write_event_config =3D &ad4062_write_event_config, + .read_event_value =3D &ad4062_read_event_value, + .write_event_value =3D &ad4062_write_event_value, + .event_attrs =3D &ad4062_event_attribute_group, .get_current_scan_type =3D &ad4062_get_current_scan_type, .debugfs_reg_access =3D &ad4062_debugfs_reg_access, }; @@ -938,8 +1304,10 @@ static int ad4062_probe(struct i3c_device *i3cdev) "Failed to initialize regmap\n"); =20 st->mode =3D AD4062_SAMPLE_MODE; + st->wait_event =3D false; st->chip =3D chip; st->sampling_frequency =3D 0; + st->events_frequency =3D 0; st->oversamp_ratio =3D 0; st->indio_dev =3D indio_dev; =20 --=20 2.51.1 From nobody Thu Dec 18 09:27:40 2025 Received: from mx0a-00128a01.pphosted.com (mx0a-00128a01.pphosted.com [148.163.135.77]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3D1FC329C40; Fri, 5 Dec 2025 15:13:10 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.163.135.77 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764947597; cv=none; b=uRW8HrQAr7gZ9vNLx0R3BWpklr21KPycGzPn6R37TG/NaK9AuH4ggGdwyV5g0lXB9UKBE8HrB2vn2+8hp8Cg1Q9Nth/ZxGBiz5UOtIXq3xzYoe6gIgPw4JQmPy+9KJs8TmyOxSwAuFfG3UqJTV2RufpnqPc1I+sOdUnSOfaoMgU= ARC-Message-Signature: i=1; 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Signed-off-by: Jorge Marques Reviewed-by: Linus Walleij --- Documentation/iio/ad4062.rst | 13 ++++++++++++- 1 file changed, 12 insertions(+), 1 deletion(-) diff --git a/Documentation/iio/ad4062.rst b/Documentation/iio/ad4062.rst index 5afec4d8c2ddb..78665755ebebc 100644 --- a/Documentation/iio/ad4062.rst +++ b/Documentation/iio/ad4062.rst @@ -29,6 +29,9 @@ the devicetree ``interrupt-names`` property: - GP0: Is assigned the role of Threshold Either signal. - GP1: Is assigned the role of Data Ready signal. =20 +If the property ``gpio-controller`` is present in the devicetree, then the= GPO +not present in the ``interrupt-names`` is exposed as a GPO. + Device attributes =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D =20 @@ -135,9 +138,17 @@ The following event attributes are available: * - ``thresh_rising_value`` - Set the maximum threshold value. =20 +GPO controller support +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D + +The device supports using GP0 and GP1 as GPOs. If the devicetree contains = the +node ``gpio-controller```, the device is marked as a GPIO controller and t= he +GPs not listed in ``interrupt-names`` are exposed as a GPO. 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20251205-staging-ad4062-v3-9-8761355f9c66@analog.com> References: <20251205-staging-ad4062-v3-0-8761355f9c66@analog.com> In-Reply-To: <20251205-staging-ad4062-v3-0-8761355f9c66@analog.com> To: Lars-Peter Clausen , Michael Hennerich , Jonathan Cameron , "David Lechner" , =?utf-8?q?Nuno_S=C3=A1?= , Andy Shevchenko , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Jonathan Corbet , Linus Walleij , Bartosz Golaszewski CC: , , , , , Jorge Marques X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1764947528; l=5635; i=jorge.marques@analog.com; s=20250303; h=from:subject:message-id; bh=uq609zIRAOVsAf4uucshpjyCAMyR9HyUFzZbfYrcEe0=; b=EMgSPj6+FkEhY8ozHtLL8QCCDWIiDiJ+ZLQQNK6psLbPjKfBfcCF3vhhMacHzNqrcvLbhpu5B j4a9vCJkBCMBgOBJlrx2bPR4FjAvt8Ew5wy7djjF7tKqsDUEkpBrV3S X-Developer-Key: i=jorge.marques@analog.com; a=ed25519; pk=NUR1IZZMH0Da3QbJ2tBSznSPVfRpuoWdhBzKGSpAdbg= X-ADIRuleOP-NewSCL: Rule Triggered X-Authority-Analysis: v=2.4 cv=G4cR0tk5 c=1 sm=1 tr=0 ts=6932f674 cx=c_pps a=3WNzaoukacrqR9RwcOSAdA==:117 a=3WNzaoukacrqR9RwcOSAdA==:17 a=IkcTkHD0fZMA:10 a=wP3pNCr1ah4A:10 a=VkNPw1HP01LnGYTKEx00:22 a=gAnH3GRIAAAA:8 a=xMyuZJbwAj7bCYiyej4A:9 a=QEXdDO2ut3YA:10 X-Proofpoint-GUID: iyXUigWsP5l9yKJZiyOEghs_Dm0xCzOe X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMjA1MDExMCBTYWx0ZWRfXxPSX+6dzbUCR EHKTFjcIQHappZv2EtWoE+R1IfxOvEH1kmUJ2WvVzBtBNY7JPag+Hbh+jgUBlcM6ZkGsnOXnc5U sC3WQYON55GEM6vObZ7uqTSHm0d5H2neuN7KhgsM0dEIWZfDjj2CjwqmFWILCf0bttkO0yxr+iV BEIb3eFaEEtsOVilVtB1MkXBN3TklXYo/J+6L4vTnlTeXRGcHLm9xmbzbu2YQUv6liz5rR8jn3q J/DyArDogOCou99k4oc2xXZjSMOYMnIUXwXbZGXiqSegB7P3Q1joKRk2RGqhAfKf053p1m3dwv6 AiA1Q2Y3ekfw15cwh9F/nDR7ZGe5ofOyBHQukIfKZDFfXetc6DNpXrogCU6kSiKdcW2Ee+hXLmX 8k8kI3x/ZkSAHXVgKLZe04OtG4Mlng== X-Proofpoint-ORIG-GUID: iyXUigWsP5l9yKJZiyOEghs_Dm0xCzOe X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2025-12-05_05,2025-12-04_04,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 lowpriorityscore=0 priorityscore=1501 suspectscore=0 spamscore=0 clxscore=1015 phishscore=0 malwarescore=0 adultscore=0 bulkscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2510240001 definitions=main-2512050110 When gp0 or gp1 is not taken as an interrupt, expose them as GPO if gpio-contoller is set in the devicetree. gpio-regmap is not used because the GPO static low is 'b101 and static high is 0b110; low state requires setting bit 0, not fitting the abstraction of low=3D0 and high=3Dmask. Signed-off-by: Jorge Marques Reviewed-by: Linus Walleij --- drivers/iio/adc/ad4062.c | 125 +++++++++++++++++++++++++++++++++++++++++++= ++++ 1 file changed, 125 insertions(+) diff --git a/drivers/iio/adc/ad4062.c b/drivers/iio/adc/ad4062.c index e432aa60a224e..e52894ed757f7 100644 --- a/drivers/iio/adc/ad4062.c +++ b/drivers/iio/adc/ad4062.c @@ -11,6 +11,7 @@ #include #include #include +#include #include #include #include @@ -87,8 +88,11 @@ #define AD4060_MAX_AVG 0x7 #define AD4062_MAX_AVG 0xB =20 +#define AD4062_GP_DISABLED 0x0 #define AD4062_GP_INTR 0x1 #define AD4062_GP_DRDY 0x2 +#define AD4062_GP_STATIC_LOW 0x5 +#define AD4062_GP_STATIC_HIGH 0x6 =20 #define AD4062_LIMIT_BITS 11 =20 @@ -652,12 +656,14 @@ static int ad4062_request_irq(struct iio_dev *indio_d= ev) if (ret =3D=3D -EPROBE_DEFER) { return ret; } else if (ret < 0) { + st->gpo_irq[0] =3D false; ret =3D regmap_update_bits(st->regmap, AD4062_REG_ADC_IBI_EN, AD4062_REG_ADC_IBI_EN_MAX | AD4062_REG_ADC_IBI_EN_MIN, AD4062_REG_ADC_IBI_EN_MAX | AD4062_REG_ADC_IBI_EN_MIN); if (ret) return ret; } else { + st->gpo_irq[0] =3D true; ret =3D devm_request_threaded_irq(dev, ret, NULL, ad4062_irq_handler_thresh, IRQF_ONESHOT, indio_dev->name, @@ -1268,6 +1274,121 @@ static int ad4062_regulators_get(struct ad4062_stat= e *st, bool *ref_sel) return 0; } =20 +static int ad4062_gpio_get_direction(struct gpio_chip *gc, unsigned int of= fset) +{ + return GPIO_LINE_DIRECTION_OUT; +} + +static int ad4062_gpio_set(struct gpio_chip *gc, unsigned int offset, int = value) +{ + struct ad4062_state *st =3D gpiochip_get_data(gc); + unsigned int reg_val =3D value ? AD4062_GP_STATIC_HIGH : AD4062_GP_STATIC= _LOW; + + if (offset) + return regmap_update_bits(st->regmap, AD4062_REG_GP_CONF, + AD4062_REG_GP_CONF_MODE_MSK_1, + FIELD_PREP(AD4062_REG_GP_CONF_MODE_MSK_1, reg_val)); + else + return regmap_update_bits(st->regmap, AD4062_REG_GP_CONF, + AD4062_REG_GP_CONF_MODE_MSK_0, + FIELD_PREP(AD4062_REG_GP_CONF_MODE_MSK_0, reg_val)); +} + +static int ad4062_gpio_get(struct gpio_chip *gc, unsigned int offset) +{ + struct ad4062_state *st =3D gpiochip_get_data(gc); + unsigned int reg_val; + int ret; + + ret =3D regmap_read(st->regmap, AD4062_REG_GP_CONF, ®_val); + if (ret) + return ret; + + if (offset) + reg_val =3D FIELD_GET(AD4062_REG_GP_CONF_MODE_MSK_1, reg_val); + else + reg_val =3D FIELD_GET(AD4062_REG_GP_CONF_MODE_MSK_0, reg_val); + + return reg_val =3D=3D AD4062_GP_STATIC_HIGH; +} + +static void ad4062_gpio_disable(void *data) +{ + struct ad4062_state *st =3D data; + u8 val =3D FIELD_PREP(AD4062_REG_GP_CONF_MODE_MSK_0, AD4062_GP_DISABLED) | + FIELD_PREP(AD4062_REG_GP_CONF_MODE_MSK_1, AD4062_GP_DISABLED); + + regmap_update_bits(st->regmap, AD4062_REG_GP_CONF, + AD4062_REG_GP_CONF_MODE_MSK_1 | AD4062_REG_GP_CONF_MODE_MSK_0, + val); +} + +static int ad4062_gpio_init_valid_mask(struct gpio_chip *gc, + unsigned long *valid_mask, + unsigned int ngpios) +{ + struct ad4062_state *st =3D gpiochip_get_data(gc); + + bitmap_zero(valid_mask, ngpios); + + for (unsigned int i =3D 0; i < ARRAY_SIZE(st->gpo_irq); i++) + __assign_bit(i, valid_mask, !st->gpo_irq[i]); + + return 0; +} + +static int ad4062_gpio_init(struct ad4062_state *st) +{ + struct device *dev =3D &st->i3cdev->dev; + struct gpio_chip *gc; + u8 val, mask; + int ret; + + if (!device_property_read_bool(dev, "gpio-controller")) + return 0; + + gc =3D devm_kzalloc(dev, sizeof(*gc), GFP_KERNEL); + if (!gc) + return -ENOMEM; + + val =3D 0; + mask =3D 0; + if (!st->gpo_irq[0]) { + mask |=3D AD4062_REG_GP_CONF_MODE_MSK_0; + val |=3D FIELD_PREP(AD4062_REG_GP_CONF_MODE_MSK_0, AD4062_GP_STATIC_LOW); + } + if (!st->gpo_irq[1]) { + mask |=3D AD4062_REG_GP_CONF_MODE_MSK_1; + val |=3D FIELD_PREP(AD4062_REG_GP_CONF_MODE_MSK_1, AD4062_GP_STATIC_LOW); + } + + ret =3D regmap_update_bits(st->regmap, AD4062_REG_GP_CONF, + mask, val); + if (ret) + return ret; + + ret =3D devm_add_action_or_reset(dev, ad4062_gpio_disable, st); + if (ret) + return ret; + + gc->parent =3D dev; + gc->label =3D st->chip->name; + gc->owner =3D THIS_MODULE; + gc->base =3D -1; + gc->ngpio =3D 2; + gc->init_valid_mask =3D ad4062_gpio_init_valid_mask; + gc->get_direction =3D ad4062_gpio_get_direction; + gc->set =3D ad4062_gpio_set; + gc->get =3D ad4062_gpio_get; + gc->can_sleep =3D true; + + ret =3D devm_gpiochip_add_data(dev, gc, st); + if (ret) + return dev_err_probe(dev, ret, "Unable to register GPIO chip\n"); + + return 0; +} + static const struct i3c_device_id ad4062_id_table[] =3D { I3C_DEVICE(AD4062_I3C_VENDOR, ad4060_chip_info.prod_id, &ad4060_chip_info= ), I3C_DEVICE(AD4062_I3C_VENDOR, ad4062_chip_info.prod_id, &ad4062_chip_info= ), @@ -1356,6 +1477,10 @@ static int ad4062_probe(struct i3c_device *i3cdev) if (ret) return dev_err_probe(dev, ret, "Failed to request i3c ibi\n"); =20 + ret =3D ad4062_gpio_init(st); + if (ret) + return ret; + ret =3D devm_work_autocancel(dev, &st->trig_conv, ad4062_trigger_work); if (ret) return ret; --=20 2.51.1