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a=ed25519-sha256; t=1764906855; l=5759; i=royluo@google.com; s=20251120; h=from:subject:message-id; bh=ptdeaHvryRd3du/x5tpdu2A1Uhs07EexzpJqndowuTI=; b=q5ohSaGg7OpLG4b4ODFHBEYmeqz1yVI6mZnXTBU2XgYOPQGfz5Ten0zXX12PwvMmv7x03fc6H 5JSFNmnffTnDAlpSA0UoomGjan0EmjhV5SDd8ay7fdQnshlMwukAKSC X-Mailer: b4 0.14.2 Message-ID: <20251205-phyb4-v8-1-c59ea80a4458@google.com> Subject: [PATCH v8 1/2] dt-bindings: phy: google: Add Google Tensor G5 USB PHY From: Roy Luo To: Vinod Koul , Kishon Vijay Abraham I , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Peter Griffin , "=?utf-8?q?Andr=C3=A9_Draszik?=" , Tudor Ambarus , Philipp Zabel Cc: Badhri Jagan Sridharan , Doug Anderson , linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, Joy Chakraborty , Naveen Kumar , Roy Luo Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Document the device tree bindings for the USB PHY interfaces integrated with the DWC3 controller on Google Tensor SoCs, starting with G5 generation (Laguna). The USB PHY on Tensor G5 includes two integrated Synopsys PHY IPs: the eUSB 2.0 PHY IP and the USB 3.2/DisplayPort combo PHY IP. Due to a complete architectural overhaul in the Google Tensor G5, the existing Samsung/Exynos USB PHY binding for older generations of Google silicons such as gs101 are no longer compatible, necessitating this new device tree binding. Signed-off-by: Roy Luo Reviewed-by: Krzysztof Kozlowski --- .../bindings/phy/google,lga-usb-phy.yaml | 133 +++++++++++++++++= ++++ MAINTAINERS | 1 + 2 files changed, 134 insertions(+) diff --git a/Documentation/devicetree/bindings/phy/google,lga-usb-phy.yaml = b/Documentation/devicetree/bindings/phy/google,lga-usb-phy.yaml new file mode 100644 index 0000000000000000000000000000000000000000..427e2e3425f645f40c0813e29d6= efe4f62b20609 --- /dev/null +++ b/Documentation/devicetree/bindings/phy/google,lga-usb-phy.yaml @@ -0,0 +1,133 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +# Copyright (C) 2025, Google LLC +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/phy/google,lga-usb-phy.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Google Tensor Series G5 (Laguna) USB PHY + +maintainers: + - Roy Luo + +description: + Describes the USB PHY interfaces integrated with the DWC3 USB controller= on + Google Tensor SoCs, starting with the G5 generation (laguna). + Two specific PHY IPs from Synopsys are integrated, including eUSB 2.0 PH= Y IP + and USB3.2/DisplayPort combo PHY IP. + +properties: + compatible: + const: google,lga-usb-phy + + reg: + items: + - description: USB3.2/DisplayPort combo PHY core registers. + - description: USB3.2/DisplayPort combo PHY Type-C Assist registers. + - description: eUSB 2.0 PHY core registers. + - description: Top-level wrapper registers for the integrated PHYs. + + reg-names: + items: + - const: usb3_core + - const: usb3_tca + - const: usb2_core + - const: usbdp_top + + "#phy-cells": + description: | + The phandle's argument in the PHY specifier selects one of the three + following PHY interfaces. + - 0 for USB high-speed. + - 1 for USB super-speed. + - 2 for DisplayPort. + const: 1 + + clocks: + items: + - description: USB2 PHY clock. + - description: USB2 PHY APB clock. + - description: USB3.2/DisplayPort combo PHY clock. + - description: USB3.2/DisplayPort combo PHY firmware clock. + + clock-names: + items: + - const: usb2 + - const: usb2_apb + - const: usb3 + - const: usb3_fw + + resets: + items: + - description: USB2 PHY reset. + - description: USB2 PHY APB reset. + - description: USB3.2/DisplayPort combo PHY reset. + + reset-names: + items: + - const: usb2 + - const: usb2_apb + - const: usb3 + + power-domains: + maxItems: 1 + + orientation-switch: + type: boolean + description: + Indicates the PHY as a handler of USB Type-C orientation changes + + google,usb-cfg-csr: + description: + A phandle to a syscon node used to access the USB configuration + registers. These registers are the top-level wrapper of the USB + subsystem and provide control and status for the integrated USB + controller and USB PHY. + $ref: /schemas/types.yaml#/definitions/phandle-array + items: + - items: + - description: phandle to the syscon node. + - description: USB2 PHY configuration register offset. + +required: + - compatible + - reg + - reg-names + - "#phy-cells" + - clocks + - clock-names + - resets + - reset-names + - power-domains + - orientation-switch + - google,usb-cfg-csr + +additionalProperties: false + +examples: + - | + soc { + #address-cells =3D <2>; + #size-cells =3D <2>; + + usb-phy@c410000 { + compatible =3D "google,lga-usb-phy"; + reg =3D <0 0x0c410000 0 0x20000>, + <0 0x0c430000 0 0x1000>, + <0 0x0c440000 0 0x10000>, + <0 0x0c637000 0 0xa0>; + reg-names =3D "usb3_core", "usb3_tca", "usb2_core", "usbdp_top= "; + #phy-cells =3D <1>; + clocks =3D <&hsion_usb2_phy_clk>, <&hsion_u2phy_apb_clk>, + <&hsion_usb3_phy_clk>, <&hsion_usb3_phy_fw_clk>; + clock-names =3D "usb2", "usb2_apb", "usb3", "usb3_fw"; + resets =3D <&hsion_resets_usb2_phy>, + <&hsion_resets_u2phy_apb>, + <&hsion_resets_usb3_phy>; + reset-names =3D "usb2", "usb2_apb", "usb3"; + power-domains =3D <&hsio_n_usb_pd>; + orientation-switch; + google,usb-cfg-csr =3D <&usb_cfg_csr 0x14>; + }; + }; +... diff --git a/MAINTAINERS b/MAINTAINERS index 772af0072fff0921000c6fe27c018666c1579e48..27e6f9e20f5e83b861c6a04dede= db93b8561715c 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -10661,6 +10661,7 @@ S: Maintained P: Documentation/process/maintainer-soc-clean-dts.rst C: irc://irc.oftc.net/pixel6-kernel-dev F: Documentation/devicetree/bindings/clock/google,gs101-clock.yaml +F: Documentation/devicetree/bindings/phy/google,lga-usb-phy.yaml F: Documentation/devicetree/bindings/soc/google/google,gs101-pmu-intr-gen.= yaml F: arch/arm64/boot/dts/exynos/google/ F: drivers/clk/samsung/clk-gs101.c --=20 2.52.0.223.gf5cc29aaa4-goog From nobody Sat Feb 7 20:22:19 2026 Received: from mail-pg1-f201.google.com (mail-pg1-f201.google.com [209.85.215.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 843512C027B for ; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Support the USB PHY found on Google Tensor G5 (Laguna). This particular USB PHY supports both high-speed and super-speed operations, and is integrated with the SNPS DWC3 controller that's also on the SoC. This initial patch specifically adds functionality for high-speed. Co-developed-by: Joy Chakraborty Signed-off-by: Joy Chakraborty Co-developed-by: Naveen Kumar Signed-off-by: Naveen Kumar Signed-off-by: Roy Luo --- MAINTAINERS | 1 + drivers/phy/Kconfig | 11 ++ drivers/phy/Makefile | 1 + drivers/phy/phy-google-usb.c | 295 +++++++++++++++++++++++++++++++++++++++= ++++ 4 files changed, 308 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 27e6f9e20f5e83b861c6a04dededb93b8561715c..50ffe42c7c373914aa96314430f= 35843efc1dc07 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -10665,6 +10665,7 @@ F: Documentation/devicetree/bindings/phy/google,lga= -usb-phy.yaml F: Documentation/devicetree/bindings/soc/google/google,gs101-pmu-intr-gen.= yaml F: arch/arm64/boot/dts/exynos/google/ F: drivers/clk/samsung/clk-gs101.c +F: drivers/phy/phy-google-usb.c F: drivers/phy/samsung/phy-gs101-ufs.c F: include/dt-bindings/clock/google,gs101.h K: [gG]oogle.?[tT]ensor diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig index 678dd0452f0aa0597773433f04d2a9ba77474d2a..c6fbf83de656349f5c9be27a187= 48b9bd327f683 100644 --- a/drivers/phy/Kconfig +++ b/drivers/phy/Kconfig @@ -101,6 +101,17 @@ config PHY_NXP_PTN3222 schemes. It supports all three USB 2.0 data rates: Low Speed, Full Speed and High Speed. =20 +config PHY_GOOGLE_USB + tristate "Google Tensor SoC USB PHY driver" + depends on ARCH_GOOGLE || COMPILE_TEST + select GENERIC_PHY + help + Enable support for the USB PHY on Google Tensor SoCs, starting with + the G5 generation (Laguna). This driver provides the PHY interfaces + to interact with the SNPS eUSB2 and USB 3.2/DisplayPort Combo PHY, + both of which are integrated with the DWC3 USB DRD controller. + This driver currently supports USB high-speed. + source "drivers/phy/allwinner/Kconfig" source "drivers/phy/amlogic/Kconfig" source "drivers/phy/broadcom/Kconfig" diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile index bfb27fb5a494283d7fd05dd670ebd1b12df8b1a1..aeaaaf988554a24bb572d8b34b5= 4638a6a3aed73 100644 --- a/drivers/phy/Makefile +++ b/drivers/phy/Makefile @@ -13,6 +13,7 @@ obj-$(CONFIG_PHY_SNPS_EUSB2) +=3D phy-snps-eusb2.o obj-$(CONFIG_USB_LGM_PHY) +=3D phy-lgm-usb.o obj-$(CONFIG_PHY_AIROHA_PCIE) +=3D phy-airoha-pcie.o obj-$(CONFIG_PHY_NXP_PTN3222) +=3D phy-nxp-ptn3222.o +obj-$(CONFIG_PHY_GOOGLE_USB) +=3D phy-google-usb.o obj-y +=3D allwinner/ \ amlogic/ \ broadcom/ \ diff --git a/drivers/phy/phy-google-usb.c b/drivers/phy/phy-google-usb.c new file mode 100644 index 0000000000000000000000000000000000000000..97e345fdab9b3679e7a76f6957a= e3814ef3420e8 --- /dev/null +++ b/drivers/phy/phy-google-usb.c @@ -0,0 +1,295 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * phy-google-usb.c - Google USB PHY driver + * + * Copyright (C) 2025, Google LLC + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define USBCS_USB2PHY_CFG19_OFFSET 0x0 +#define USBCS_USB2PHY_CFG19_PHY_CFG_PLL_FB_DIV GENMASK(19, 8) + +#define USBCS_USB2PHY_CFG21_OFFSET 0x8 +#define USBCS_USB2PHY_CFG21_PHY_ENABLE BIT(12) +#define USBCS_USB2PHY_CFG21_REF_FREQ_SEL GENMASK(15, 13) +#define USBCS_USB2PHY_CFG21_PHY_TX_DIG_BYPASS_SEL BIT(19) + +#define USBCS_PHY_CFG1_OFFSET 0x28 +#define USBCS_PHY_CFG1_SYS_VBUSVALID BIT(17) + +enum google_usb_phy_id { + GOOGLE_USB2_PHY, + GOOGLE_USB_PHY_NUM, +}; + +struct google_usb_phy_instance { + int index; + struct phy *phy; + int num_clks; + struct clk_bulk_data *clks; + int num_rsts; + struct reset_control_bulk_data *rsts; +}; + +struct google_usb_phy { + struct device *dev; + struct regmap *usb_cfg_regmap; + unsigned int usb2_cfg_offset; + void __iomem *usbdp_top_base; + struct google_usb_phy_instance insts[GOOGLE_USB_PHY_NUM]; + /* + * Protect phy registers from concurrent access, specifically via + * google_usb_set_orientation callback. + */ + struct mutex phy_mutex; + struct typec_switch_dev *sw; + enum typec_orientation orientation; +}; + +static inline struct google_usb_phy *to_google_usb_phy(struct google_usb_p= hy_instance *inst) +{ + return container_of(inst, struct google_usb_phy, insts[inst->index]); +} + +static void set_vbus_valid(struct google_usb_phy *gphy) +{ + u32 reg; + + if (gphy->orientation =3D=3D TYPEC_ORIENTATION_NONE) { + reg =3D readl(gphy->usbdp_top_base + USBCS_PHY_CFG1_OFFSET); + reg &=3D ~USBCS_PHY_CFG1_SYS_VBUSVALID; + writel(reg, gphy->usbdp_top_base + USBCS_PHY_CFG1_OFFSET); + } else { + reg =3D readl(gphy->usbdp_top_base + USBCS_PHY_CFG1_OFFSET); + reg |=3D USBCS_PHY_CFG1_SYS_VBUSVALID; + writel(reg, gphy->usbdp_top_base + USBCS_PHY_CFG1_OFFSET); + } +} + +static int google_usb_set_orientation(struct typec_switch_dev *sw, + enum typec_orientation orientation) +{ + struct google_usb_phy *gphy =3D typec_switch_get_drvdata(sw); + + dev_dbg(gphy->dev, "set orientation %d\n", orientation); + + gphy->orientation =3D orientation; + + if (pm_runtime_suspended(gphy->dev)) + return 0; + + guard(mutex)(&gphy->phy_mutex); + + set_vbus_valid(gphy); + + return 0; +} + +static int google_usb2_phy_init(struct phy *_phy) +{ + struct google_usb_phy_instance *inst =3D phy_get_drvdata(_phy); + struct google_usb_phy *gphy =3D to_google_usb_phy(inst); + u32 reg; + int ret =3D 0; + + dev_dbg(gphy->dev, "initializing usb2 phy\n"); + + guard(mutex)(&gphy->phy_mutex); + + regmap_read(gphy->usb_cfg_regmap, gphy->usb2_cfg_offset + USBCS_USB2PHY_C= FG21_OFFSET, ®); + reg &=3D ~USBCS_USB2PHY_CFG21_PHY_TX_DIG_BYPASS_SEL; + reg &=3D ~USBCS_USB2PHY_CFG21_REF_FREQ_SEL; + reg |=3D FIELD_PREP(USBCS_USB2PHY_CFG21_REF_FREQ_SEL, 0); + regmap_write(gphy->usb_cfg_regmap, gphy->usb2_cfg_offset + USBCS_USB2PHY_= CFG21_OFFSET, reg); + + regmap_read(gphy->usb_cfg_regmap, gphy->usb2_cfg_offset + USBCS_USB2PHY_C= FG19_OFFSET, ®); + reg &=3D ~USBCS_USB2PHY_CFG19_PHY_CFG_PLL_FB_DIV; + reg |=3D FIELD_PREP(USBCS_USB2PHY_CFG19_PHY_CFG_PLL_FB_DIV, 368); + regmap_write(gphy->usb_cfg_regmap, gphy->usb2_cfg_offset + USBCS_USB2PHY_= CFG19_OFFSET, reg); + + set_vbus_valid(gphy); + + ret =3D clk_bulk_prepare_enable(inst->num_clks, inst->clks); + if (ret) + return ret; + + ret =3D reset_control_bulk_deassert(inst->num_rsts, inst->rsts); + if (ret) { + clk_bulk_disable_unprepare(inst->num_clks, inst->clks); + return ret; + } + + regmap_read(gphy->usb_cfg_regmap, gphy->usb2_cfg_offset + USBCS_USB2PHY_C= FG21_OFFSET, ®); + reg |=3D USBCS_USB2PHY_CFG21_PHY_ENABLE; + regmap_write(gphy->usb_cfg_regmap, gphy->usb2_cfg_offset + USBCS_USB2PHY_= CFG21_OFFSET, reg); + + return ret; +} + +static int google_usb2_phy_exit(struct phy *_phy) +{ + struct google_usb_phy_instance *inst =3D phy_get_drvdata(_phy); + struct google_usb_phy *gphy =3D to_google_usb_phy(inst); + u32 reg; + + dev_dbg(gphy->dev, "exiting usb2 phy\n"); + + guard(mutex)(&gphy->phy_mutex); + + regmap_read(gphy->usb_cfg_regmap, gphy->usb2_cfg_offset + USBCS_USB2PHY_C= FG21_OFFSET, ®); + reg &=3D ~USBCS_USB2PHY_CFG21_PHY_ENABLE; + regmap_write(gphy->usb_cfg_regmap, gphy->usb2_cfg_offset + USBCS_USB2PHY_= CFG21_OFFSET, reg); + + reset_control_bulk_assert(inst->num_rsts, inst->rsts); + clk_bulk_disable_unprepare(inst->num_clks, inst->clks); + + return 0; +} + +static const struct phy_ops google_usb2_phy_ops =3D { + .init =3D google_usb2_phy_init, + .exit =3D google_usb2_phy_exit, +}; + +static struct phy *google_usb_phy_xlate(struct device *dev, + const struct of_phandle_args *args) +{ + struct google_usb_phy *gphy =3D dev_get_drvdata(dev); + + if (args->args[0] >=3D GOOGLE_USB_PHY_NUM) { + dev_err(dev, "invalid PHY index requested from DT\n"); + return ERR_PTR(-ENODEV); + } + return gphy->insts[args->args[0]].phy; +} + +static int google_usb_phy_probe(struct platform_device *pdev) +{ + struct typec_switch_desc sw_desc =3D { }; + struct google_usb_phy_instance *inst; + struct phy_provider *phy_provider; + struct device *dev =3D &pdev->dev; + struct google_usb_phy *gphy; + struct phy *phy; + u32 args[1]; + int ret; + + gphy =3D devm_kzalloc(dev, sizeof(*gphy), GFP_KERNEL); + if (!gphy) + return -ENOMEM; + + dev_set_drvdata(dev, gphy); + gphy->dev =3D dev; + + ret =3D devm_mutex_init(dev, &gphy->phy_mutex); + if (ret) + return ret; + + gphy->usb_cfg_regmap =3D + syscon_regmap_lookup_by_phandle_args(dev->of_node, + "google,usb-cfg-csr", + ARRAY_SIZE(args), args); + if (IS_ERR(gphy->usb_cfg_regmap)) { + return dev_err_probe(dev, PTR_ERR(gphy->usb_cfg_regmap), + "invalid usb cfg csr\n"); + } + + gphy->usb2_cfg_offset =3D args[0]; + + gphy->usbdp_top_base =3D devm_platform_ioremap_resource_byname(pdev, + "usbdp_top"); + if (IS_ERR(gphy->usbdp_top_base)) + return dev_err_probe(dev, PTR_ERR(gphy->usbdp_top_base), + "invalid usbdp top\n"); + + inst =3D &gphy->insts[GOOGLE_USB2_PHY]; + inst->index =3D GOOGLE_USB2_PHY; + phy =3D devm_phy_create(dev, NULL, &google_usb2_phy_ops); + if (IS_ERR(phy)) + return dev_err_probe(dev, PTR_ERR(phy), + "failed to create usb2 phy instance\n"); + inst->phy =3D phy; + phy_set_drvdata(phy, inst); + + inst->num_clks =3D 2; + inst->clks =3D devm_kcalloc(dev, inst->num_clks, sizeof(*inst->clks), GFP= _KERNEL); + if (!inst->clks) + return -ENOMEM; + inst->clks[0].id =3D "usb2"; + inst->clks[1].id =3D "usb2_apb"; + ret =3D devm_clk_bulk_get(dev, inst->num_clks, inst->clks); + if (ret) + return dev_err_probe(dev, ret, "failed to get u2 phy clks\n"); + + inst->num_rsts =3D 2; + inst->rsts =3D devm_kcalloc(dev, inst->num_rsts, sizeof(*inst->rsts), GFP= _KERNEL); + if (!inst->rsts) + return -ENOMEM; + inst->rsts[0].id =3D "usb2"; + inst->rsts[1].id =3D "usb2_apb"; + ret =3D devm_reset_control_bulk_get_exclusive(dev, inst->num_rsts, inst->= rsts); + if (ret) + return dev_err_probe(dev, ret, "failed to get u2 phy resets\n"); + + phy_provider =3D devm_of_phy_provider_register(dev, google_usb_phy_xlate); + if (IS_ERR(phy_provider)) + return dev_err_probe(dev, PTR_ERR(phy_provider), + "failed to register phy provider\n"); + + pm_runtime_enable(dev); + + sw_desc.fwnode =3D dev_fwnode(dev); + sw_desc.drvdata =3D gphy; + sw_desc.name =3D fwnode_get_name(dev_fwnode(dev)); + sw_desc.set =3D google_usb_set_orientation; + + gphy->sw =3D typec_switch_register(dev, &sw_desc); + if (IS_ERR(gphy->sw)) + return dev_err_probe(dev, PTR_ERR(gphy->sw), + "failed to register typec switch\n"); + + return 0; +} + +static void google_usb_phy_remove(struct platform_device *pdev) +{ + struct google_usb_phy *gphy =3D dev_get_drvdata(&pdev->dev); + + typec_switch_unregister(gphy->sw); + pm_runtime_disable(&pdev->dev); +} + +static const struct of_device_id google_usb_phy_of_match[] =3D { + { + .compatible =3D "google,lga-usb-phy", + }, + { } +}; +MODULE_DEVICE_TABLE(of, google_usb_phy_of_match); + +static struct platform_driver google_usb_phy =3D { + .probe =3D google_usb_phy_probe, + .remove =3D google_usb_phy_remove, + .driver =3D { + .name =3D "google-usb-phy", + .of_match_table =3D google_usb_phy_of_match, + } +}; + +module_platform_driver(google_usb_phy); +MODULE_LICENSE("GPL"); +MODULE_DESCRIPTION("Google USB phy driver"); --=20 2.52.0.223.gf5cc29aaa4-goog