From nobody Fri Dec 19 20:15:27 2025 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 63652321456 for ; Fri, 5 Dec 2025 14:22:53 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.251.105.195 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764944576; cv=none; b=dfZLhLz4OaycgIZ8LJwzO1531J5OqxbewWGKXAdX94A1AlKiknMJz/kNRCveCLA8mEm95upp2HGWCGC5jYx6zWtX0WPWof0RK9dLH+DnuY8od4ar32Da2JptCg4ZsOPGA/Gl9UylFkxfYbr16Gd0ldquxITwrpLFTt9nYsZ7RJA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764944576; c=relaxed/simple; bh=pMwPFJMTtIP4dtXu2+MjCXusZPpj26s41YMtdPqsIt4=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=MLJcsPhOGlMrzmgDEK95A80Tmlqo3e1/5YqCKsa4K1wvHJ7Ri3GvIL3eDGHsz1h3tNn+8O+N2BDcMgDMGuiLWHsnA1sLNKX7PjYrjKp3BSuoFWGvjB0Stapj/2V4kCnqhnxJZGOX6lbCEvYc7qYVqUxWsY296evsVGpzC8b2TMQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com; spf=pass smtp.mailfrom=collabora.com; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b=EW8jcJsl; arc=none smtp.client-ip=148.251.105.195 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=collabora.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b="EW8jcJsl" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1764944571; bh=pMwPFJMTtIP4dtXu2+MjCXusZPpj26s41YMtdPqsIt4=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=EW8jcJsl8AuIKgt2RnlWlpw5uHAJm4116T5wJU3U1sotbOySHa012kPNTE6ZPugbv lfc2GLM23lNhhY8bFIPsZmnbHujBAK8bxIc1rMaXdibjUmcJ3zvWi1Ai6mT+Tcvqc/ NucXXe1iAgLdvm/hZziItXZA0/QCBpZq7zXZoMwmwIDdkX16UkA4w+q5Y9HbxQFRyg KBuooa6EYQsl6Et9fh7eEiZAg16Fgw9UL9gsXS3C0Tv4Eo93EU+J6BAgHTV3fVtM3n OKD+79Yby0ab4mrqst3a83TFDurxhWEOJeNcyx5v9B7yaT/5uHKU0JBfeRQJ8pSCyQ t94vMxilcSqEg== Received: from yukiji.home (amontpellier-657-1-116-247.w83-113.abo.wanadoo.fr [83.113.51.247]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: laeyraud) by bali.collaboradmins.com (Postfix) with ESMTPSA id C3E5517E1149; Fri, 5 Dec 2025 15:22:50 +0100 (CET) From: Louis-Alexis Eyraud Date: Fri, 05 Dec 2025 15:22:26 +0100 Subject: [PATCH 1/2] drm/mediatek: mtk_hdmi_ddc_v2: Add transfer abort on timeout cases Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251205-mtk-hdmi-ddc-v2-fixes-v1-1-260dd0d320f4@collabora.com> References: <20251205-mtk-hdmi-ddc-v2-fixes-v1-0-260dd0d320f4@collabora.com> In-Reply-To: <20251205-mtk-hdmi-ddc-v2-fixes-v1-0-260dd0d320f4@collabora.com> To: Chun-Kuang Hu , Philipp Zabel , David Airlie , Simona Vetter , Matthias Brugger , AngeloGioacchino Del Regno , CK Hu Cc: kernel@collabora.com, dri-devel@lists.freedesktop.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Louis-Alexis Eyraud X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1764944570; l=1808; i=louisalexis.eyraud@collabora.com; s=20250113; h=from:subject:message-id; bh=pMwPFJMTtIP4dtXu2+MjCXusZPpj26s41YMtdPqsIt4=; b=IjONvCPU1h33wadF1IH3+uR6UHWidUH2F80MCy1EokeaQlxCEKOuMrbZFVVpXy3voIsmgiWJY GjFZaRMC5owAXNkD5kAGFZL6Iz2rL06MN+OO/YUROptJlgeIhhc20N5 X-Developer-Key: i=louisalexis.eyraud@collabora.com; a=ed25519; pk=CHFBDB2Kqh4EHc6JIqFn69GhxJJAzc0Zr4e8QxtumuM= During a read or write transfer, the mtk_hdmi_ddc_v2 driver polls the DDC_I2C_IN_PROG bit of HPD_DDC_STATUS register to check if the transfer completes but do no particular action if a timeout is reached. It could lead the next transfer attempts to fail because the faulty transfer was not aborted. So, add in both low level read and write functions a abort action by writing the DDC_CTRL register with the ABORT_XFER command value. Fixes: 8d0f79886273 ("drm/mediatek: Introduce HDMI/DDC v2 for MT8195/MT8188= ") Signed-off-by: Louis-Alexis Eyraud --- drivers/gpu/drm/mediatek/mtk_hdmi_ddc_v2.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/drivers/gpu/drm/mediatek/mtk_hdmi_ddc_v2.c b/drivers/gpu/drm/m= ediatek/mtk_hdmi_ddc_v2.c index b844e2c10f28060baef64bd36c5464758b08e162..6ae7cbba8cb6dacf46c2f7ab74a= 2d7446d698b69 100644 --- a/drivers/gpu/drm/mediatek/mtk_hdmi_ddc_v2.c +++ b/drivers/gpu/drm/mediatek/mtk_hdmi_ddc_v2.c @@ -96,6 +96,11 @@ static int mtk_ddc_wr_one(struct mtk_hdmi_ddc *ddc, u16 = addr_id, !(val & DDC_I2C_IN_PROG), 500, 1000); if (ret) { dev_err(ddc->dev, "DDC I2C write timeout\n"); + + /* Abort transfer if it is still in progress */ + regmap_update_bits(ddc->regs, DDC_CTRL, DDC_CTRL_CMD, + FIELD_PREP(DDC_CTRL_CMD, DDC_CMD_ABORT_XFER)); + return ret; } =20 @@ -179,6 +184,11 @@ static int mtk_ddcm_read_hdmi(struct mtk_hdmi_ddc *ddc= , u16 uc_dev, 500 * (temp_length + 5)); if (ret) { dev_err(ddc->dev, "Timeout waiting for DDC I2C\n"); + + /* Abort transfer if it is still in progress */ + regmap_update_bits(ddc->regs, DDC_CTRL, DDC_CTRL_CMD, + FIELD_PREP(DDC_CTRL_CMD, DDC_CMD_ABORT_XFER)); + return ret; } =20 --=20 2.52.0 From nobody Fri Dec 19 20:15:27 2025 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5C190317710 for ; Fri, 5 Dec 2025 14:22:53 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.251.105.195 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764944577; cv=none; b=tpuuBTjaCC+MkEZRG/hCKSOrEpHolsBmjcilZLNMHWx3F05w/J7gRW87N/yryWLcjm72gYoe3gQiLAkBwG+kbZpuHFKxhONIBgHg9WoHnxaBCJj0AkOIZUDLwvGdmH79aWYxUSwZEhmCkKvS9RFwk3orvPjaYvml3Ok9y0C6uqg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764944577; c=relaxed/simple; bh=IOwQM3PEyoGk9c+YMqTQPC9Ut+gviCgxV81ozkF0ZiE=; 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h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=kw6/jWMtvdFR8GgKDF6dqeFAdLZy1ayqifYxDoFC6DjRUscZFWIW67AqjNmc8WLKq Xg2Fmv+uhB3vBEzVmK8oOHE0UR6XKWda0fUGJ7i85AfVk8q2ao6ayjpW2BqO3UEhJD 3EJ24nY9MBe/XpqAz688d37M9B71nzsm7lJu5TIZy6HBOTHc+t7NRkamqH0g0mKbWV 8QrLrlqL5MxvdJoKvvkd01FwewMwGejS+8dZfY9NeS+f1EJE7hqOj9apeNXWFBIU7a t/ZEF+7FY87IoGbkmKm/Yiyr4rVLhAZvap89zQgAyS0ZGleqUoCpZaI+zQmOX6nVuK 3cuzOjaA5FUuw== Received: from yukiji.home (amontpellier-657-1-116-247.w83-113.abo.wanadoo.fr [83.113.51.247]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: laeyraud) by bali.collaboradmins.com (Postfix) with ESMTPSA id 7C98417E126B; Fri, 5 Dec 2025 15:22:51 +0100 (CET) From: Louis-Alexis Eyraud Date: Fri, 05 Dec 2025 15:22:27 +0100 Subject: [PATCH 2/2] drm/mediatek: mtk_hdmi_ddc_v2: Fix multi-byte writes Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251205-mtk-hdmi-ddc-v2-fixes-v1-2-260dd0d320f4@collabora.com> References: <20251205-mtk-hdmi-ddc-v2-fixes-v1-0-260dd0d320f4@collabora.com> In-Reply-To: <20251205-mtk-hdmi-ddc-v2-fixes-v1-0-260dd0d320f4@collabora.com> To: Chun-Kuang Hu , Philipp Zabel , David Airlie , Simona Vetter , Matthias Brugger , AngeloGioacchino Del Regno , CK Hu Cc: kernel@collabora.com, dri-devel@lists.freedesktop.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Louis-Alexis Eyraud X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1764944570; l=3878; i=louisalexis.eyraud@collabora.com; s=20250113; h=from:subject:message-id; bh=IOwQM3PEyoGk9c+YMqTQPC9Ut+gviCgxV81ozkF0ZiE=; b=ZHXJGgrjt5YRp7XxbPnmM+GfhkFFN8m9c+Eyr+pVK3MkP7ZDb6KBS5H+DVoblJUtWVYnRoYpV CrfSLQ1vBEqBluyd9Jq0wM8r7ttHzspDcIsVi2zqnnns9smNrsJd86l X-Developer-Key: i=louisalexis.eyraud@collabora.com; a=ed25519; pk=CHFBDB2Kqh4EHc6JIqFn69GhxJJAzc0Zr4e8QxtumuM= Currently, the mtk_hdmi_ddc_v2 driver sends a i2c message by calling the mtk_ddc_wr_one function for each byte of the payload to setup SI2C_CTRL and DDC_CTRL registers, and perform a sequential write transfer of one byte at a time to the target device. This leads to incorrect transfers as the target address (at least) is also sent each time. So, rename mtk_ddc_wr_one function to mtk_ddcm_write_hdmi to match the read function name (mtk_ddcm_read_hdmi) and modify its behaviour to send all payload data in a single sequential write transfer by filling the transfer fifo first then starting the transfer with a size equal to the payload size and not one anymore. Fixes: 8d0f79886273 ("drm/mediatek: Introduce HDMI/DDC v2 for MT8195/MT8188= ") Signed-off-by: Louis-Alexis Eyraud --- drivers/gpu/drm/mediatek/mtk_hdmi_ddc_v2.c | 48 ++++++++++++++------------= ---- 1 file changed, 23 insertions(+), 25 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_hdmi_ddc_v2.c b/drivers/gpu/drm/m= ediatek/mtk_hdmi_ddc_v2.c index 6ae7cbba8cb6dacf46c2f7ab74a2d7446d698b69..d937219fdb7ee0ed6a4ac25e950= f69f90ff431a3 100644 --- a/drivers/gpu/drm/mediatek/mtk_hdmi_ddc_v2.c +++ b/drivers/gpu/drm/mediatek/mtk_hdmi_ddc_v2.c @@ -66,11 +66,19 @@ static int mtk_ddc_check_and_rise_low_bus(struct mtk_hd= mi_ddc *ddc) return 0; } =20 -static int mtk_ddc_wr_one(struct mtk_hdmi_ddc *ddc, u16 addr_id, - u16 offset_id, u8 *wr_data) +static int mtk_ddcm_write_hdmi(struct mtk_hdmi_ddc *ddc, u16 addr_id, + u16 offset_id, u16 data_cnt, u8 *wr_data) { u32 val; - int ret; + int ret, i; + + /* Don't allow transfer with a size over than the transfer fifo size + * (16 byte) + */ + if (data_cnt > 16) { + dev_err(ddc->dev, "Invalid DDCM write request\n"); + return -EINVAL; + } =20 /* If down, rise bus for write operation */ mtk_ddc_check_and_rise_low_bus(ddc); @@ -78,16 +86,21 @@ static int mtk_ddc_wr_one(struct mtk_hdmi_ddc *ddc, u16= addr_id, regmap_update_bits(ddc->regs, HPD_DDC_CTRL, HPD_DDC_DELAY_CNT, FIELD_PREP(HPD_DDC_DELAY_CNT, DDC2_DLY_CNT)); =20 + /* In case there is no payload data, just do a single write for the + * address only + */ if (wr_data) { - regmap_write(ddc->regs, SI2C_CTRL, - FIELD_PREP(SI2C_ADDR, SI2C_ADDR_READ) | - FIELD_PREP(SI2C_WDATA, *wr_data) | - SI2C_WR); + /* Fill transfer fifo with payload data */ + for (i =3D 0; i < data_cnt; i++) { + regmap_write(ddc->regs, SI2C_CTRL, + FIELD_PREP(SI2C_ADDR, SI2C_ADDR_READ) | + FIELD_PREP(SI2C_WDATA, wr_data[i]) | + SI2C_WR); + } } - regmap_write(ddc->regs, DDC_CTRL, FIELD_PREP(DDC_CTRL_CMD, DDC_CMD_SEQ_WRITE) | - FIELD_PREP(DDC_CTRL_DIN_CNT, wr_data =3D=3D NULL ? 0 : 1) | + FIELD_PREP(DDC_CTRL_DIN_CNT, wr_data =3D=3D NULL ? 0 : data_cnt) | FIELD_PREP(DDC_CTRL_OFFSET, offset_id) | FIELD_PREP(DDC_CTRL_ADDR, addr_id)); usleep_range(1000, 1250); @@ -260,24 +273,9 @@ static int mtk_hdmi_fg_ddc_data_read(struct mtk_hdmi_d= dc *ddc, u16 b_dev, static int mtk_hdmi_ddc_fg_data_write(struct mtk_hdmi_ddc *ddc, u16 b_dev, u8 data_addr, u16 data_cnt, u8 *pr_data) { - int i, ret; - regmap_set_bits(ddc->regs, HDCP2X_POL_CTRL, HDCP2X_DIS_POLL_EN); - /* - * In case there is no payload data, just do a single write for the - * address only - */ - if (data_cnt =3D=3D 0) - return mtk_ddc_wr_one(ddc, b_dev, data_addr, NULL); - - i =3D 0; - do { - ret =3D mtk_ddc_wr_one(ddc, b_dev, data_addr + i, pr_data + i); - if (ret) - return ret; - } while (++i < data_cnt); =20 - return 0; + return mtk_ddcm_write_hdmi(ddc, b_dev, data_addr, data_cnt, pr_data); } =20 static int mtk_hdmi_ddc_v2_xfer(struct i2c_adapter *adapter, struct i2c_ms= g *msgs, int num) --=20 2.52.0