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[73.183.52.120]) by smtp.gmail.com with ESMTPSA id 956f58d0204a3-6443f2b80casm2151181d50.9.2025.12.05.11.46.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 05 Dec 2025 11:46:54 -0800 (PST) From: Brian Masney Date: Fri, 05 Dec 2025 14:46:30 -0500 Subject: [PATCH v3 4/4] clk: microchip: core: allow driver to be compiled with COMPILE_TEST Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251205-clk-microchip-fixes-v3-4-a02190705e47@redhat.com> References: <20251205-clk-microchip-fixes-v3-0-a02190705e47@redhat.com> In-Reply-To: <20251205-clk-microchip-fixes-v3-0-a02190705e47@redhat.com> To: Michael Turquette , Stephen Boyd , Maxime Ripard , Claudiu Beznea , Conor Dooley , Dan Carpenter Cc: linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, Brian Masney X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=2718; i=bmasney@redhat.com; s=20250903; h=from:subject:message-id; bh=KPcvmdhFm9HlslOyuHv2lYXxtXtxadeQa7HuDvwARJc=; b=owGbwMvMwCW2/dJd9di6A+2Mp9WSGDKNzZaE29yyi489dtTVc0XbdPOjIi93X/Jck5Xi5BoRm qFUK1reUcrCIMbFICumyLIk16ggInWV7b07miwwc1iZQIYwcHEKwETsShj+CuwuOK7ntu5AUuqm kFs/c3K5L1z/2f1DuSMgWNmOdeHyXwz/7OO9ElP/30p6KxG0MGD5oWt50/N9Xuz+vDecfWtmQbw qNwA= X-Developer-Key: i=bmasney@redhat.com; a=openpgp; fpr=A46D32705865AA3DDEDC2904B7D2DD275D7EC087 This driver currently only supports builds against a PIC32 target. To avoid future breakage in the future, let's update the Kconfig and the driver so that it can be built with CONFIG_COMPILE_TEST enabled. Note that with the existing asm calls is not how I'd want to do this today if this was a new driver, however I don't have access to this hardware. To avoid any breakage, let's keep the existing behavior. Signed-off-by: Brian Masney --- drivers/clk/microchip/Kconfig | 2 +- drivers/clk/microchip/clk-core.c | 32 +++++++++++++++++++++++--------- 2 files changed, 24 insertions(+), 10 deletions(-) diff --git a/drivers/clk/microchip/Kconfig b/drivers/clk/microchip/Kconfig index 1b9e43eb54976b219a0277cc971f353fd6af226a..1e56a057319d97e20440fe4e107= d26fa85c95ab1 100644 --- a/drivers/clk/microchip/Kconfig +++ b/drivers/clk/microchip/Kconfig @@ -1,7 +1,7 @@ # SPDX-License-Identifier: GPL-2.0 =20 config COMMON_CLK_PIC32 - def_bool COMMON_CLK && MACH_PIC32 + def_bool (COMMON_CLK && MACH_PIC32) || COMPILE_TEST =20 config MCHP_CLK_MPFS bool "Clk driver for PolarFire SoC" diff --git a/drivers/clk/microchip/clk-core.c b/drivers/clk/microchip/clk-c= ore.c index f467d7bc28c87a50fb18dc527574f973c4b7e615..fad4b45d908310ffb59e4ed57c5= 5ae4266253444 100644 --- a/drivers/clk/microchip/clk-core.c +++ b/drivers/clk/microchip/clk-core.c @@ -9,7 +9,15 @@ #include #include #include + +#if !defined(CONFIG_MACH_PIC32) && defined(CONFIG_COMPILE_TEST) +#define PIC32_CLR(_reg) ((_reg) + 0x04) +#define PIC32_SET(_reg) ((_reg) + 0x08) +#define PIC32_INV(_reg) ((_reg) + 0x0C) +#define pic32_syskey_unlock() +#else #include +#endif =20 #include "clk-core.h" =20 @@ -74,15 +82,21 @@ /* SoC specific clock needed during SPLL clock rate switch */ static struct clk_hw *pic32_sclk_hw; =20 -/* add instruction pipeline delay while CPU clock is in-transition. */ -#define cpu_nop5() \ -do { \ - __asm__ __volatile__("nop"); \ - __asm__ __volatile__("nop"); \ - __asm__ __volatile__("nop"); \ - __asm__ __volatile__("nop"); \ - __asm__ __volatile__("nop"); \ -} while (0) +#if !defined(CONFIG_MACH_PIC32) && defined(CONFIG_COMPILE_TEST) +#define cpu_nop5() +#else +{ + /* add instruction pipeline delay while CPU clock is in-transition. */ + #define cpu_nop5() \ + do { \ + __asm__ __volatile__("nop"); \ + __asm__ __volatile__("nop"); \ + __asm__ __volatile__("nop"); \ + __asm__ __volatile__("nop"); \ + __asm__ __volatile__("nop"); \ + } while (0) +} +#endif =20 /* Perpheral bus clocks */ struct pic32_periph_clk { --=20 2.52.0