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[73.183.52.120]) by smtp.gmail.com with ESMTPSA id 956f58d0204a3-6443f2b80casm2151181d50.9.2025.12.05.11.46.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 05 Dec 2025 11:46:47 -0800 (PST) From: Brian Masney Date: Fri, 05 Dec 2025 14:46:27 -0500 Subject: [PATCH v3 1/4] clk: microchip: core: remove duplicate determine_rate on pic32_sclk_ops Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251205-clk-microchip-fixes-v3-1-a02190705e47@redhat.com> References: <20251205-clk-microchip-fixes-v3-0-a02190705e47@redhat.com> In-Reply-To: <20251205-clk-microchip-fixes-v3-0-a02190705e47@redhat.com> To: Michael Turquette , Stephen Boyd , Maxime Ripard , Claudiu Beznea , Conor Dooley , Dan Carpenter Cc: linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, Brian Masney , kernel test robot X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=2011; i=bmasney@redhat.com; s=20250903; h=from:subject:message-id; bh=z65zBnwhMmCjmLXWrNn9LKYrNxyaLvGh7xymTom1ePE=; b=owGbwMvMwCW2/dJd9di6A+2Mp9WSGDKNzZZ4TfoyvWCL9QRtXoeVf+102S4tmrv007W3G5JWi udldi7R6ShlYRDjYpAVU2RZkmtUEJG6yvbeHU0WmDmsTCBDGLg4BWAiK6sZ/vD7qDhvO5O/NOdX scF/YctlCjIHo9x9JG9dDf/neuYSCzsjw1Gto0VFRzNs7i5j3HTtRqfYrK+tFn9dYitS/xc88HT N5wQA X-Developer-Key: i=bmasney@redhat.com; a=openpgp; fpr=A46D32705865AA3DDEDC2904B7D2DD275D7EC087 pic32_sclk_ops previously had a sclk_round_rate() member, and this was recently converted over to sclk_determine_rate() with the help of a Coccinelle semantic patch. pic32_sclk_ops now has two conflicting determine_rate ops members. Prior to the conversion, pic32_sclk_ops already had a determine_rate member that points to __clk_mux_determine_rate(). When both the round_rate() and determine_rate() ops are defined, the clk core only uses the determine_rate() op. Let's go ahead and drop the recently converted sclk_determine_rate() to match the previous functionality prior to the conversion. Fixes: e9f039c08cdc ("clk: microchip: core: convert from round_rate() to de= termine_rate()") Reported-by: kernel test robot Closes: https://lore.kernel.org/oe-kbuild-all/202511222115.uvHrP95A-lkp@int= el.com/ Signed-off-by: Brian Masney Reviewed-by: Claudiu Beznea --- drivers/clk/microchip/clk-core.c | 10 ---------- 1 file changed, 10 deletions(-) diff --git a/drivers/clk/microchip/clk-core.c b/drivers/clk/microchip/clk-c= ore.c index b34348d491f3e1b576b2b9a8a66bfddd8c2296ea..a0163441dfe5c1dfc27dae48e64= cf3cb3d6b764f 100644 --- a/drivers/clk/microchip/clk-core.c +++ b/drivers/clk/microchip/clk-core.c @@ -780,15 +780,6 @@ static unsigned long sclk_get_rate(struct clk_hw *hw, = unsigned long parent_rate) return parent_rate / div; } =20 -static int sclk_determine_rate(struct clk_hw *hw, - struct clk_rate_request *req) -{ - req->rate =3D calc_best_divided_rate(req->rate, req->best_parent_rate, - SLEW_SYSDIV, 1); - - return 0; -} - static int sclk_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate) { @@ -912,7 +903,6 @@ static int sclk_init(struct clk_hw *hw) const struct clk_ops pic32_sclk_ops =3D { .get_parent =3D sclk_get_parent, .set_parent =3D sclk_set_parent, - .determine_rate =3D sclk_determine_rate, .set_rate =3D sclk_set_rate, .recalc_rate =3D sclk_get_rate, .init =3D sclk_init, --=20 2.52.0