From nobody Fri Dec 19 16:43:23 2025 Received: from out-189.mta1.migadu.com (out-189.mta1.migadu.com [95.215.58.189]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 157258634C for ; Fri, 5 Dec 2025 06:29:27 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=95.215.58.189 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764916170; cv=none; b=nkXy/ToYbp0UhieQ03MMWPHJfywqFBkKugVZL6weTNu7BMYwRmZzAsUwPTkzbtpqWLXY+4kTD6XfK3F2Y0YT2OWZlvqHyea8rWr18jC3QU2bXKeO8m3LLEvyzWHk2HuOfxxtJtYOqqV8e4L4w6v41TnI7xRR/BMlaxIhdkYNZLk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764916170; c=relaxed/simple; bh=CHhZrO+seigQep4EcilCQI+NM2vFrNNb290ys6kF5LI=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=H3h0BBo1bc79SszEe7w+LgBKqmTBct7MCc99YQbe4xSMB7thkymIgXJFHHR4pWC3DTu26zXtAtDgsp4TCCzCFd4y8A8ipSPaQenpFDKwBP4eUk2IH1TPu2BV+RULVlNsZ1IxwvVwXQKTX09NWhnqc3Ea4PmCYHDFEF1ruC5fnr8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.dev; spf=pass smtp.mailfrom=linux.dev; dkim=pass (1024-bit key) header.d=linux.dev header.i=@linux.dev header.b=MBUeISDt; arc=none smtp.client-ip=95.215.58.189 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.dev Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.dev Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linux.dev header.i=@linux.dev header.b="MBUeISDt" X-Report-Abuse: Please report any abuse attempt to abuse@migadu.com and include these headers. DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.dev; s=key1; t=1764916166; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=6KDuNOF7zwOqq4SGBvigFpNcY4PTnIkUpXxey+/fvOw=; b=MBUeISDtkCNLQKQ3KegCfIWXqWWsr3INUUNFKXiAV6d/33DjeOP0l005PdB/8zMSkIj9HO H91HL+h439tF0Y6NwHeo1ksSqKyoGt2uwYBaiHFRORS+YUibepNkbA9xJ/V+wX23c2Wqp2 YrKyZuEFHFBRMVdA0emM2yk+ahiQT0A= From: George Guo Date: Fri, 05 Dec 2025 14:29:04 +0800 Subject: [PATCH v4 1/4] LoongArch: Add 128-bit atomic cmpxchg support Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251205-2-v4-1-e5ab932cf219@linux.dev> References: <20251205-2-v4-0-e5ab932cf219@linux.dev> In-Reply-To: <20251205-2-v4-0-e5ab932cf219@linux.dev> To: Huacai Chen , WANG Xuerui Cc: loongarch@lists.linux.dev, linux-kernel@vger.kernel.org, George Guo , George Guo X-Developer-Signature: v=1; a=ed25519-sha256; t=1764916159; l=2734; i=dongtai.guo@linux.dev; s=20251103; h=from:subject:message-id; bh=G9Rok0Fvrnc2B8Tx4x6JiuOW/GjTomdEObq8AwW7z40=; b=p6MsxaxhhQBgLsZkCDMOZpfjMMOauwytYCV0P0szR5s/vExh0iCmIv+ktcOeYgkgnloNQ+3Dg wE2LJyhSOFxA0cfV3DJ+p1MB3JpB5XP7nu8bih36dIu7AAe/Sxk9GEL X-Developer-Key: i=dongtai.guo@linux.dev; a=ed25519; pk=yHUJPGx/kAXutP/NSHpj7hWW0KQNlv3w9H6ju4qUoTM= X-Migadu-Flow: FLOW_OUT From: George Guo Implement 128-bit atomic compare-and-exchange using LoongArch's LL.D/SC.Q instructions. At the same time, fix BPF scheduler test failures (scx_central scx_qmap) caused by kmalloc_nolock_noprof returning NULL due to missing 128-bit atomics. The NULL returns led to -ENOMEM errors during scheduler initialization, causing test cases to fail. Verified by testing with the scx_qmap scheduler (located in tools/sched_ext/). Building with `make` and running ./tools/sched_ext/build/bin/scx_qmap. Signed-off-by: George Guo --- arch/loongarch/include/asm/cmpxchg.h | 47 ++++++++++++++++++++++++++++++++= ++++ 1 file changed, 47 insertions(+) diff --git a/arch/loongarch/include/asm/cmpxchg.h b/arch/loongarch/include/= asm/cmpxchg.h index 979fde61bba8a42cb4f019f13ded2a3119d4aaf4..f7a0a9a032c513196ef186a5493= b500787e0e9b6 100644 --- a/arch/loongarch/include/asm/cmpxchg.h +++ b/arch/loongarch/include/asm/cmpxchg.h @@ -111,6 +111,44 @@ __arch_xchg(volatile void *ptr, unsigned long x, int s= ize) __ret; \ }) =20 +union __u128_halves { + u128 full; + struct { + u64 low; + u64 high; + }; +}; + +#define __cmpxchg128_asm(ptr, old, new) \ +({ \ + union __u128_halves __old, __new, __ret; \ + volatile u64 *__ptr =3D (volatile u64 *)(ptr); \ + \ + __old.full =3D (old); \ + __new.full =3D (new); \ + \ + __asm__ __volatile__( \ + "1: ll.d %0, %3 # 128-bit cmpxchg low \n" \ + __WEAK_LLSC_MB \ + " ld.d %1, %4 # 128-bit cmpxchg high \n" \ + " bne %0, %z5, 2f \n" \ + " bne %1, %z6, 2f \n" \ + " move $t0, %z7 \n" \ + " move $t1, %z8 \n" \ + " sc.q $t0, $t1, %2 \n" \ + " beqz $t0, 1b \n" \ + "2: \n" \ + __WEAK_LLSC_MB \ + : "=3D&r" (__ret.low), "=3D&r" (__ret.high) \ + : "r" (__ptr), \ + "ZC" (__ptr[0]), "m" (__ptr[1]), \ + "Jr" (__old.low), "Jr" (__old.high), \ + "Jr" (__new.low), "Jr" (__new.high) \ + : "t0", "t1", "memory"); \ + \ + __ret.full; \ +}) + static inline unsigned int __cmpxchg_small(volatile void *ptr, unsigned in= t old, unsigned int new, unsigned int size) { @@ -198,6 +236,15 @@ __cmpxchg(volatile void *ptr, unsigned long old, unsig= ned long new, unsigned int __res; \ }) =20 +/* cmpxchg128 */ +#define system_has_cmpxchg128() 1 + +#define arch_cmpxchg128(ptr, o, n) \ +({ \ + BUILD_BUG_ON(sizeof(*(ptr)) !=3D 16); \ + __cmpxchg128_asm(ptr, o, n); \ +}) + #ifdef CONFIG_64BIT #define arch_cmpxchg64_local(ptr, o, n) \ ({ \ --=20 2.49.0 From nobody Fri Dec 19 16:43:23 2025 Received: from out-181.mta1.migadu.com (out-181.mta1.migadu.com [95.215.58.181]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 327BC2F4A06 for ; Fri, 5 Dec 2025 06:29:31 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=95.215.58.181 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764916173; cv=none; b=Cg9b62TzFQDvEb/J4a+plaWby/3rnHxucOzBVTxnG5SWXTHhc5FSRf8RwjveivYGhqWgsM+7m3rqIKgcfQUbaP2XuPsAZvV40FP6hwajXAcfhgpIaXiV9AsYAxr15Muq9AzToyXeHNT6R2JtFRKH918ZohdAofn6piNwFjgNBEs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764916173; c=relaxed/simple; bh=sSbavY35pohbv0p0NsDDkXc9ND0MsdY6Tj9RlR06H5g=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=SFhzyX0OrB9M5lloc+KmqMUa2Gcnlu4VGe0jS2Jh1drPqeCmdcqhSrjgqMx3Y19ftbDrUpDE3IQn0K48CxPLzrUIm68NViwS/8q6tX4QITzWvE5/y2TDjKliIqynQ3+YgxNZk7xPrjjPtgZcYsqyzuB4AakPXQ8Qu4wq3h6LIuQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.dev; spf=pass smtp.mailfrom=linux.dev; dkim=pass (1024-bit key) header.d=linux.dev header.i=@linux.dev header.b=DNCQh2EF; arc=none smtp.client-ip=95.215.58.181 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.dev Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.dev Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linux.dev header.i=@linux.dev header.b="DNCQh2EF" X-Report-Abuse: Please report any abuse attempt to abuse@migadu.com and include these headers. DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.dev; s=key1; t=1764916169; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=rbIP4FIfXgyVPybkD2AC4h5SfDq/AjeNenIArga2wk0=; b=DNCQh2EFq1iix0Mzg93W3aSVGvDQiklzlKNaV7broKc7tHU6tgqE9KUjve5D2tpu3BgyHq XzOFfO7V6cQ27+Osy9pj2DuDPMudoNaKlkFKlj19ZWUaAVC0mN9juov/QVWtarrZJIEx7O seWy12CehzbU2aqSu1CLjKgCb8sPYRM= From: George Guo Date: Fri, 05 Dec 2025 14:29:05 +0800 Subject: [PATCH v4 2/4] LoongArch: Add SCQ support detection Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251205-2-v4-2-e5ab932cf219@linux.dev> References: <20251205-2-v4-0-e5ab932cf219@linux.dev> In-Reply-To: <20251205-2-v4-0-e5ab932cf219@linux.dev> To: Huacai Chen , WANG Xuerui Cc: loongarch@lists.linux.dev, linux-kernel@vger.kernel.org, George Guo , george , Yangyang Lian , George Guo X-Developer-Signature: v=1; a=ed25519-sha256; t=1764916160; l=3297; i=dongtai.guo@linux.dev; s=20251103; h=from:subject:message-id; bh=asp3zEGHKQM1Bn/cuBBd7v6/IsNBRe16HsbU8xem4UU=; b=/P6G/eCKOSjxgXbKSENqdFeumz02U7FA4KflSyaG0WIeJezJnftCBly8F9n7//ca+GB9ZWuTl 28pcGk98/hYBJ1S4QS57DmeS5F6OHa8QdAwN9tq0jEnyV2sz2HavYZg X-Developer-Key: i=dongtai.guo@linux.dev; a=ed25519; pk=yHUJPGx/kAXutP/NSHpj7hWW0KQNlv3w9H6ju4qUoTM= X-Migadu-Flow: FLOW_OUT From: george Check CPUCFG2_SCQ bit to determin if the CPU supports SCQ instrction. Co-developed-by: Yangyang Lian Signed-off-by: Yangyang Lian Signed-off-by: George Guo --- arch/loongarch/include/asm/cpu-features.h | 1 + arch/loongarch/include/asm/cpu.h | 2 ++ arch/loongarch/include/asm/loongarch.h | 1 + arch/loongarch/kernel/cpu-probe.c | 4 ++++ 4 files changed, 8 insertions(+) diff --git a/arch/loongarch/include/asm/cpu-features.h b/arch/loongarch/inc= lude/asm/cpu-features.h index bd5f0457ad21d89ab902fb1971cc8b41b1d340ad..860cb58a92ba0c0316a8009d974= 41043374e7f10 100644 --- a/arch/loongarch/include/asm/cpu-features.h +++ b/arch/loongarch/include/asm/cpu-features.h @@ -70,5 +70,6 @@ #define cpu_has_msgint cpu_opt(LOONGARCH_CPU_MSGINT) #define cpu_has_avecint cpu_opt(LOONGARCH_CPU_AVECINT) #define cpu_has_redirectint cpu_opt(LOONGARCH_CPU_REDIRECTINT) +#define cpu_has_scq cpu_opt(LOONGARCH_CPU_SCQ) =20 #endif /* __ASM_CPU_FEATURES_H */ diff --git a/arch/loongarch/include/asm/cpu.h b/arch/loongarch/include/asm/= cpu.h index f3efb00b61414a9b111ade9fe9beb410b927d937..5531039027ec763f21c7a6a8868= 5ec81fa61d3cc 100644 --- a/arch/loongarch/include/asm/cpu.h +++ b/arch/loongarch/include/asm/cpu.h @@ -125,6 +125,7 @@ static inline char *id_to_core_name(unsigned int id) #define CPU_FEATURE_MSGINT 29 /* CPU has MSG interrupt */ #define CPU_FEATURE_AVECINT 30 /* CPU has AVEC interrupt */ #define CPU_FEATURE_REDIRECTINT 31 /* CPU has interrupt remapping */ +#define CPU_FEATURE_SCQ 32 /* CPU has SC.Q instruction */ =20 #define LOONGARCH_CPU_CPUCFG BIT_ULL(CPU_FEATURE_CPUCFG) #define LOONGARCH_CPU_LAM BIT_ULL(CPU_FEATURE_LAM) @@ -158,5 +159,6 @@ static inline char *id_to_core_name(unsigned int id) #define LOONGARCH_CPU_MSGINT BIT_ULL(CPU_FEATURE_MSGINT) #define LOONGARCH_CPU_AVECINT BIT_ULL(CPU_FEATURE_AVECINT) #define LOONGARCH_CPU_REDIRECTINT BIT_ULL(CPU_FEATURE_REDIRECTINT) +#define LOONGARCH_CPU_SCQ BIT_ULL(CPU_FEATURE_SCQ) =20 #endif /* _ASM_CPU_H */ diff --git a/arch/loongarch/include/asm/loongarch.h b/arch/loongarch/includ= e/asm/loongarch.h index 3de03cb864b248cd0fb5de9ec5a86b1436ccbdef..be04b3e6f5b0cd6c5d561efcfd9= 9502bc24e5eee 100644 --- a/arch/loongarch/include/asm/loongarch.h +++ b/arch/loongarch/include/asm/loongarch.h @@ -94,6 +94,7 @@ #define CPUCFG2_LSPW BIT(21) #define CPUCFG2_LAM BIT(22) #define CPUCFG2_PTW BIT(24) +#define CPUCFG2_SCQ BIT(30) =20 #define LOONGARCH_CPUCFG3 0x3 #define CPUCFG3_CCDMA BIT(0) diff --git a/arch/loongarch/kernel/cpu-probe.c b/arch/loongarch/kernel/cpu-= probe.c index a2060a24b39fd78fa255816fa5518e0ee99b8a8e..47815a55b7b48bbffd4954a9b8b= df7021d7e234d 100644 --- a/arch/loongarch/kernel/cpu-probe.c +++ b/arch/loongarch/kernel/cpu-probe.c @@ -201,6 +201,10 @@ static void cpu_probe_common(struct cpuinfo_loongarch = *c) c->options |=3D LOONGARCH_CPU_PTW; elf_hwcap |=3D HWCAP_LOONGARCH_PTW; } + if (config & CPUCFG2_SCQ) + c->options |=3D LOONGARCH_CPU_SCQ; + else + pr_warn_once("CPU does NOT support SCQ\n"); if (config & CPUCFG2_LSPW) { c->options |=3D LOONGARCH_CPU_LSPW; elf_hwcap |=3D HWCAP_LOONGARCH_LSPW; --=20 2.49.0 From nobody Fri Dec 19 16:43:23 2025 Received: from out-188.mta1.migadu.com (out-188.mta1.migadu.com [95.215.58.188]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8ED592F4A16 for ; Fri, 5 Dec 2025 06:29:33 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=95.215.58.188 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764916175; cv=none; b=FGHIn010DJgEL8DS0FvEqyNQRB7uqe18DJ6W6AdDqsGNlR6bppHau8KJIUnhdtAUBOwmMcgnrrDw1PDlaiuE+66wtVBTWT4cseVOz35pR2DbTMrBP3hQjeh00U3I24pKHp9S9oI0S7nlYnMrUwKneTUChhhHww5R96RlXho1OPc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764916175; c=relaxed/simple; bh=1ydGX2ckPcbDTOaBlko8S4H7H/Su4Cxx0zFDcMsJB+g=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=Tb6zF6hyZWCBX8IthW8qvuoXg/+Lv6+SvXqaNrGH19w51IePeXcHdaBjvb5FtniDUg+eZM/TMdxbsp51cSl52fMTq+2vikz95dsoC+NDmyhj6IDsQZMua0+PkTYA8wAKCJS/YqvczZ4ly3Sc34wZoMDH1vzKetjmHn3uN1Lm6r8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.dev; spf=pass smtp.mailfrom=linux.dev; dkim=pass (1024-bit key) header.d=linux.dev header.i=@linux.dev header.b=p2hsCRx4; arc=none smtp.client-ip=95.215.58.188 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.dev Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.dev Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linux.dev header.i=@linux.dev header.b="p2hsCRx4" X-Report-Abuse: Please report any abuse attempt to abuse@migadu.com and include these headers. DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.dev; s=key1; t=1764916171; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=wbG/hNpFVx1z8RtgsmITOX2lkUrENsQeLW2JOQQh7ZM=; b=p2hsCRx4cjeCdOBEt3LFrEhSYdlbXgLO87AWrUHkHdZ8KWawKtAuURiGVX68ACqKD5fLkb LsdvimaZuOkJFY+8sG/op1iucxPw+YATBfmyL/7qUp7Pt0JzVRc715GhVnflA5AROrYPDK K0tYH18uKtIuP9Yn/c5XhLICeDYUSg4= From: George Guo Date: Fri, 05 Dec 2025 14:29:06 +0800 Subject: [PATCH v4 3/4] LoongArch: Use spinlock to emulate 128-bit cmpxchg Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251205-2-v4-3-e5ab932cf219@linux.dev> References: <20251205-2-v4-0-e5ab932cf219@linux.dev> In-Reply-To: <20251205-2-v4-0-e5ab932cf219@linux.dev> To: Huacai Chen , WANG Xuerui Cc: loongarch@lists.linux.dev, linux-kernel@vger.kernel.org, George Guo , George Guo X-Developer-Signature: v=1; a=ed25519-sha256; t=1764916160; l=1861; i=dongtai.guo@linux.dev; s=20251103; h=from:subject:message-id; bh=PCzsPV7oGfaIDaA0cqRcyRoMNSMiHxOqDWfuZv8Lz68=; b=b1E4ZG6uN9WDJE/vipRaXfZvLCZmbV2hDts/s0UlRdZ6VWJwtqJOuf1Xsgx4F4vSvUG0Ce+Zj 3vFrubDIQMsCq+4+K3cnFD9sQmyVkFzXim9KOkACeJhJKUcQ8CwC//W X-Developer-Key: i=dongtai.guo@linux.dev; a=ed25519; pk=yHUJPGx/kAXutP/NSHpj7hWW0KQNlv3w9H6ju4qUoTM= X-Migadu-Flow: FLOW_OUT From: George Guo For LoongArch CPUs lacking 128-bit atomic instruction(e.g., the SCQ instruction on 3A5000), provide a fallback implementation of __cmpxchg128 using a spinlock to emulate the atomic operation. Signed-off-by: George Guo --- arch/loongarch/include/asm/cmpxchg.h | 21 ++++++++++++++++++++- 1 file changed, 20 insertions(+), 1 deletion(-) diff --git a/arch/loongarch/include/asm/cmpxchg.h b/arch/loongarch/include/= asm/cmpxchg.h index f7a0a9a032c513196ef186a5493b500787e0e9b6..814097bfc334184018747e47fb9= 0fd2d2fb27ee2 100644 --- a/arch/loongarch/include/asm/cmpxchg.h +++ b/arch/loongarch/include/asm/cmpxchg.h @@ -8,6 +8,7 @@ #include #include #include +#include =20 #define __xchg_asm(amswap_db, m, val) \ ({ \ @@ -149,6 +150,23 @@ union __u128_halves { __ret.full; \ }) =20 +#define __cmpxchg128_locked(ptr, old, new) \ +({ \ + u128 __ret; \ + static DEFINE_SPINLOCK(lock); \ + unsigned long flags; \ + \ + spin_lock_irqsave(&lock, flags); \ + \ + __ret =3D *(volatile u128 *)(ptr); \ + if (__ret =3D=3D (old)) \ + *(volatile u128 *)(ptr) =3D (new); \ + \ + spin_unlock_irqrestore(&lock, flags); \ + \ + __ret; \ +}) + static inline unsigned int __cmpxchg_small(volatile void *ptr, unsigned in= t old, unsigned int new, unsigned int size) { @@ -242,7 +260,8 @@ __cmpxchg(volatile void *ptr, unsigned long old, unsign= ed long new, unsigned int #define arch_cmpxchg128(ptr, o, n) \ ({ \ BUILD_BUG_ON(sizeof(*(ptr)) !=3D 16); \ - __cmpxchg128_asm(ptr, o, n); \ + cpu_has_scq ? __cmpxchg128_asm(ptr, o, n) : \ + __cmpxchg128_locked(ptr, o, n); \ }) =20 #ifdef CONFIG_64BIT --=20 2.49.0 From nobody Fri Dec 19 16:43:23 2025 Received: from out-189.mta1.migadu.com (out-189.mta1.migadu.com [95.215.58.189]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B69B32F3C27 for ; Fri, 5 Dec 2025 06:29:36 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=95.215.58.189 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764916178; cv=none; b=Ikwo9bxHn9pm5KihrxfAyaTtjcTpa3xsEQZ1+KL9bgOUJnGRKB1mENstPWXYAkZuS/0aFmpDdErtSA8KC+yACWJtSP+TOd31OzRvQ4yDJgj88tl7ME8EdzzmHo1LOiuqhTwf2MAprmTw5AmbA1NtBrTOHF1N5JAdrWoI5oiG7/k= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764916178; c=relaxed/simple; bh=jBTSf1NBjHQ0A85ubxl+1PskFCEAy3vCJ4zJY+SfPYU=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=KocCs0LAghI8xq8GeUa4qlRu1bZwKBejT+DqXkatJYMHZ5r2WuLIgLsuc2EDgfW6qLBxI7vXUv67ETlBWPk+joyvwKULFSm6U1GImi0R9n7DRedujcQbrkjKPooMWGU9VliuvgM64gO2mcDfqp1EAsfS66WmXTFKq4QULAuVZ0Y= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.dev; spf=pass smtp.mailfrom=linux.dev; dkim=pass (1024-bit key) header.d=linux.dev header.i=@linux.dev header.b=AV31+iMp; arc=none smtp.client-ip=95.215.58.189 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.dev Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.dev Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linux.dev header.i=@linux.dev header.b="AV31+iMp" X-Report-Abuse: Please report any abuse attempt to abuse@migadu.com and include these headers. DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.dev; s=key1; t=1764916175; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=XnHdPbNZY+icNHDhsU00WTTGxUuRI5fAPK2EbH7Tj7Q=; b=AV31+iMpTXKQcElWK/hU5Kcj1Wmv6dXqia85uaEROKfWssCby6m62e6S7kv4dAeKBDh1Bn tsrhIBqL/r5xDroCQUE0JNQTOOFOU4eqNS8ONNvZdgxgEz1NgK6wV2RbOH9BrxFHynDOCG D7BBUiTlwQwNRwFrfUWO2ryTXPJbzQI= From: George Guo Date: Fri, 05 Dec 2025 14:29:07 +0800 Subject: [PATCH v4 4/4] LoongArch: Enable 128-bit atomics cmpxchg support Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251205-2-v4-4-e5ab932cf219@linux.dev> References: <20251205-2-v4-0-e5ab932cf219@linux.dev> In-Reply-To: <20251205-2-v4-0-e5ab932cf219@linux.dev> To: Huacai Chen , WANG Xuerui Cc: loongarch@lists.linux.dev, linux-kernel@vger.kernel.org, George Guo , George Guo X-Developer-Signature: v=1; a=ed25519-sha256; t=1764916160; l=1046; i=dongtai.guo@linux.dev; s=20251103; h=from:subject:message-id; bh=ciDWXt3BQSm1RCVw/2AyrNMAA+62PK+Q6MPycedHCU8=; b=BLAmpMY9tnhJlSwlaGTR8TBDvVc4J0Qd0e2os0lEFKVfdi9+KzRrAlXdrHT3q3rt+FxYoCmux xQBdiUrePU/CvkEaR5mH0o7Gg45W2JF5pcLvOmBdqBq1NCEJIt15ORQ X-Developer-Key: i=dongtai.guo@linux.dev; a=ed25519; pk=yHUJPGx/kAXutP/NSHpj7hWW0KQNlv3w9H6ju4qUoTM= X-Migadu-Flow: FLOW_OUT From: George Guo Add select HAVE_CMPXCHG_DOUBLE and select HAVE_ALIGNED_STRUCT_PAGE in Kconf= ig to enable 128-bit atomic cmpxchg support on LoongArch. Signed-off-by: George Guo --- arch/loongarch/Kconfig | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/loongarch/Kconfig b/arch/loongarch/Kconfig index 5b1116733d881bc2b1b43fb93f20367add4dbc54..6fb2c253969f9ddece547892042= 3d7326c3ec046 100644 --- a/arch/loongarch/Kconfig +++ b/arch/loongarch/Kconfig @@ -114,6 +114,7 @@ config LOONGARCH select GENERIC_TIME_VSYSCALL select GPIOLIB select HAS_IOPORT + select HAVE_ALIGNED_STRUCT_PAGE select HAVE_ARCH_AUDITSYSCALL select HAVE_ARCH_JUMP_LABEL select HAVE_ARCH_JUMP_LABEL_RELATIVE @@ -140,6 +141,7 @@ config LOONGARCH select HAVE_DYNAMIC_FTRACE_WITH_DIRECT_CALLS select HAVE_DYNAMIC_FTRACE_WITH_REGS select HAVE_EBPF_JIT + select HAVE_CMPXCHG_DOUBLE select HAVE_EFFICIENT_UNALIGNED_ACCESS if !ARCH_STRICT_ALIGN select HAVE_EXIT_THREAD select HAVE_GENERIC_TIF_BITS --=20 2.49.0