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Thu, 4 Dec 2025 16:03:00 -0500 (EST) From: Rebecca Cran To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Joel Stanley , Andrew Jeffery , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-aspeed@lists.ozlabs.org, linux-kernel@vger.kernel.org Cc: Rebecca Cran , Billy Tsai , Conor Dooley Subject: [PATCH v3 1/3] dt-bindings: arm: aspeed: add ASRock Rack ALTRAD8 board Date: Thu, 4 Dec 2025 14:02:34 -0700 Message-ID: <20251204210238.40742-2-rebecca@bsdio.com> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20251204210238.40742-1-rebecca@bsdio.com> References: <20251204210238.40742-1-rebecca@bsdio.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Document ASRock Rack ALTRAD8 (ALTRAD8UD-1L2T and ALTRAD8UD2-1L2Q) compatibles. Signed-off-by: Rebecca Cran Acked-by: Conor Dooley --- Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml b/Doc= umentation/devicetree/bindings/arm/aspeed/aspeed.yaml index aedefca7cf4a..049e86107c50 100644 --- a/Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml +++ b/Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml @@ -34,6 +34,7 @@ properties: - amd,ethanolx-bmc - ampere,mtjade-bmc - aspeed,ast2500-evb + - asrock,altrad8-bmc - asrock,e3c246d4i-bmc - asrock,e3c256d4i-bmc - asrock,romed8hm3-bmc --=20 2.47.3 From nobody Fri Dec 19 17:18:30 2025 Received: from fhigh-b2-smtp.messagingengine.com (fhigh-b2-smtp.messagingengine.com [202.12.124.153]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8D7CC3563C6; Thu, 4 Dec 2025 21:03:06 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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Thu, 4 Dec 2025 16:03:04 -0500 (EST) From: Rebecca Cran To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Joel Stanley , Andrew Jeffery , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-aspeed@lists.ozlabs.org, linux-kernel@vger.kernel.org Cc: Rebecca Cran , Billy Tsai Subject: [PATCH v3 2/3] ARM: dts: aspeed: add device tree for ASRock Rack ALTRAD8 BMC Date: Thu, 4 Dec 2025 14:02:35 -0700 Message-ID: <20251204210238.40742-3-rebecca@bsdio.com> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20251204210238.40742-1-rebecca@bsdio.com> References: <20251204210238.40742-1-rebecca@bsdio.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The ALTRAD8 BMC is an Aspeed AST2500-based BMC for the ASRock Rack ALTRAD8UD-1L2T and ALTRAD8UD2-1L2Q boards. Signed-off-by: Rebecca Cran --- arch/arm/boot/dts/aspeed/Makefile | 1 + arch/arm/boot/dts/aspeed/aspeed-bmc-asrock-altrad8.dts | 612 +++++++++++++= +++++++ 2 files changed, 613 insertions(+) diff --git a/arch/arm/boot/dts/aspeed/Makefile b/arch/arm/boot/dts/aspeed/M= akefile index 0f0b5b707654..9fd42a30c56d 100644 --- a/arch/arm/boot/dts/aspeed/Makefile +++ b/arch/arm/boot/dts/aspeed/Makefile @@ -9,6 +9,7 @@ dtb-$(CONFIG_ARCH_ASPEED) +=3D \ aspeed-bmc-ampere-mtjefferson.dtb \ aspeed-bmc-ampere-mtmitchell.dtb \ aspeed-bmc-arm-stardragon4800-rep2.dtb \ + aspeed-bmc-asrock-altrad8.dtb \ aspeed-bmc-asrock-e3c246d4i.dtb \ aspeed-bmc-asrock-e3c256d4i.dtb \ aspeed-bmc-asrock-romed8hm3.dtb \ diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-asrock-altrad8.dts b/arch/= arm/boot/dts/aspeed/aspeed-bmc-asrock-altrad8.dts new file mode 100644 index 000000000000..2696a8692607 --- /dev/null +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-asrock-altrad8.dts @@ -0,0 +1,612 @@ +// SPDX-License-Identifier: GPL-2.0+ +/dts-v1/; + +#include "aspeed-g5.dtsi" +#include +#include +#include + +/ { + model =3D "ASRock ALTRAD8 BMC"; + compatible =3D "asrock,altrad8-bmc", "aspeed,ast2500"; + + aliases { + serial4 =3D &uart5; + i2c50 =3D &nvme1; + i2c51 =3D &pcie4; + i2c52 =3D &pcie5; + i2c53 =3D &pcie6; + i2c54 =3D &pcie7; + i2c55 =3D &nvme3; + i2c56 =3D &nvme2; + i2c57 =3D &nvme0; + i2c58 =3D &nvme4; + i2c59 =3D &nvme5; + i2c60 =3D &nvme6; + i2c61 =3D &nvme7; + i2c62 =3D &nvme8; + i2c63 =3D &nvme9; + i2c64 =3D &nvme10; + i2c65 =3D &nvme11; + }; + + chosen { + stdout-path =3D "uart5:115200n8"; + }; + + iio-hwmon { + compatible =3D "iio-hwmon"; + io-channels =3D <&adc 0>, <&adc 1>, <&adc 2>, <&adc 3>, + <&adc 4> ,<&adc 5>, <&adc 6>, <&adc 7>, + <&adc 8>, <&adc 9>, <&adc 10>, <&adc 11>, + <&adc 12>, <&adc 13>, <&adc 14>, <&adc 15>; + }; + + leds { + compatible =3D "gpio-leds"; + + led-heartbeat { + gpios =3D <&gpio ASPEED_GPIO(G,0) GPIO_ACTIVE_LOW>; + label =3D "platform:green:heartbeat"; + color =3D ; + function =3D LED_FUNCTION_INDICATOR; + }; + + led-fan1-fault { + retain-state-shutdown; + default-state =3D "off"; + gpios =3D <&io_expander0 0 GPIO_ACTIVE_LOW>; + label =3D "fan1:red:fault"; + color =3D ; + function =3D LED_FUNCTION_FAULT; + }; + + led-fan2-fault { + retain-state-shutdown; + default-state =3D "off"; + gpios =3D <&io_expander0 1 GPIO_ACTIVE_LOW>; + label =3D "fan2:red:fault"; + color =3D ; + function =3D LED_FUNCTION_FAULT; + }; + + led-fan3-fault { + retain-state-shutdown; + default-state =3D "off"; + gpios =3D <&io_expander0 2 GPIO_ACTIVE_LOW>; + label =3D "fan3:red:fault"; + color =3D ; + function =3D LED_FUNCTION_FAULT; + }; + + led-fan4-fault { + retain-state-shutdown; + default-state =3D "off"; + gpios =3D <&io_expander0 3 GPIO_ACTIVE_LOW>; + label =3D "fan4:red:fault"; + color =3D ; + function =3D LED_FUNCTION_FAULT; + }; + + led-fan5-fault { + retain-state-shutdown; + default-state =3D "off"; + gpios =3D <&io_expander0 4 GPIO_ACTIVE_LOW>; + label =3D "fan5:red:fault"; + color =3D ; + function =3D LED_FUNCTION_FAULT; + }; + }; + + memory@80000000 { + reg =3D <0x80000000 0x20000000>; + }; + + reserved-memory { + #address-cells =3D <1>; + #size-cells =3D <1>; + ranges; + + gfx_memory: framebuffer { + compatible =3D "shared-dma-pool"; + size =3D <0x01000000>; + alignment =3D <0x01000000>; + reusable; + }; + + vga_memory: framebuffer@9f000000 { + no-map; + reg =3D <0x9f000000 0x01000000>; /* 16M */ + }; + + video_engine_memory: jpegbuffer { + compatible =3D "shared-dma-pool"; + size =3D <0x02000000>; /* 32M */ + alignment =3D <0x01000000>; + reusable; + }; + }; +}; + +&adc { + status =3D "okay"; +}; + +&fmc { + status =3D "okay"; + + flash@0 { + label =3D "bmc"; + m25p,fast-read; + spi-max-frequency =3D <50000000>; + status =3D "okay"; +#include "openbmc-flash-layout-64.dtsi" + }; +}; + +&gfx { + memory-region =3D <&gfx_memory>; + status =3D "okay"; +}; + +&gpio { + gpio-line-names =3D + /*A0-A7*/ "","","","bmc-ready","","","","", + /*B0-B7*/ "i2c-backup-sel","","","","","","","host0-shd-ack-n", + /*C0-C7*/ "","","","","","","","", + /*D0-D7*/ "power-button","power-out","button-reset", + "host0-sysreset-n","","","power-chassis-good","", + /*E0-E7*/ "","s0-vrd1-vddq0123-fault-n", + "s0-vrd1-vddq4567-fault-n","s0-vrd0-vddc-fault-n", + "s0-vrd3-p0v75-fault-n","","","", + /*F0-F7*/ "","","ps-atx-on-n","","","","","", + /*G0-G7*/ "led-identify","button-identify","","","uboot-ready",\ + "bmc-salt2-n","","", + /*H0-H7*/ "ps-pwr-ok","uart1-mode1","uart2-mode1","uart3-mode1", + "uart4-mode1","","led-bmc-heartbeat","", + /*I0-I7*/ "","","","","","","","", + /*J0-J7*/ "s0-hightemp-n","","","","","","","", + /*K0-K7*/ "","","","","","","","", + /*L0-L7*/ "","","","","","","","", + /*M0-M7*/ "","","","","","s0-spi-auth-fail-n","","", + /*N0-N7*/ "","","","","","","","", + /*O0-O7*/ "","","","","","","","", + /*P0-P7*/ "","","cpld-disable-bmc","","","","","", + /*Q0-Q7*/ "","","ext-hightemp-n","","","","", + "chassis-intrusion", + /*R0-R7*/ "","","ext-hightemp-n","spi0-program-sel","", + "hwm-bat-en","","", + /*S0-S7*/ "s0-vr-hot-n","","","bmc-sysreset-n","","","","", + /*T0-T7*/ "","","","","","","","", + /*U0-U7*/ "","","","","","","","", + /*V0-V7*/ "","","","","","","","", + /*W0-W7*/ "","","","","","","","", + /*X0-X7*/ "","","","","","","","", + /*Y0-Y7*/ "sio-s3","sio-s5","sio-pwr-req","sio-on-ctrl","","","","", + /*Z0-Z7*/ "","sio-pwr-good","","s0-rtc-lock","","","","", + /*AA0-AA7*/ "rtc-int","","","","","pmbus-sel-n","","", + /*AB0-AB7*/ "host0-reboot-ack-n","s0-sys-auth-failure-n", + "","","","","","", + /*AC0-AC7*/ "s0-fault-alert","host0-ready","s0-overtemp-n", + "","bmc-ok","host0-special-boot","presence-cpu0", + "host0-shd-req-n"; + + status =3D "okay"; +}; + +&i2c0 { + status =3D "okay"; + + ipmb@10 { + compatible =3D "ipmb-dev"; + reg =3D <(0x10 | I2C_OWN_SLAVE_ADDRESS)>; + i2c-protocol; + }; + +}; + +&i2c1 { + status =3D "okay"; + + i2c-mux1@73 { + compatible =3D "nxp,pca9548"; + reg =3D <0x73>; + #address-cells =3D <1>; + #size-cells =3D <0>; + i2c-mux-idle-disconnect; + + nvme1: i2c@0 { + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <0>; + }; + + pcie4: i2c@1 { + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <1>; + }; + + pcie5: i2c@2 { + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <2>; + }; + + pcie6: i2c@3 { + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <3>; + }; + + pcie7: i2c@4 { + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <4>; + }; + + nvme3: i2c@5 { + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <5>; + }; + + nvme2: i2c@6 { + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <6>; + }; + + nvme0: i2c@7 { + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <7>; + }; + }; + + i2c-mux2@75 { + compatible =3D "nxp,pca9548"; + reg =3D <0x75>; + #address-cells =3D <1>; + #size-cells =3D <0>; + i2c-mux-idle-disconnect; + + nvme4: i2c@0 { + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <0>; + }; + + nvme5: i2c@1 { + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <1>; + }; + + nvme6: i2c@2 { + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <2>; + }; + + nvme7: i2c@3 { + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <3>; + }; + + nvme8: i2c@4 { + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <4>; + }; + + nvme9: i2c@5 { + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <5>; + }; + + nvme10: i2c@6 { + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <6>; + }; + + nvme11: i2c@7 { + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <7>; + }; + }; +}; + +&i2c2 { + status =3D "okay"; + + smpro@4f { + compatible =3D "ampere,smpro"; + reg =3D <0x4f>; + }; +}; + +&i2c3 { + status =3D "okay"; + + // PSU FRU + eeprom@38 { + compatible =3D "atmel,24c02"; + reg =3D <0x38>; + }; +}; + +&i2c4 { + status =3D "okay"; + + temperature-sensor@29 { + compatible =3D "nuvoton,nct7802"; + reg =3D <0x29>; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + channel@0 { /* LTD */ + reg =3D <0>; + status =3D "okay"; + }; + + channel@1 { /* RTD1 */ + reg =3D <1>; + sensor-type =3D "temperature"; + temperature-mode =3D "thermistor"; + }; + + channel@2 { /* RTD2 */ + reg =3D <2>; + sensor-type =3D "temperature"; + temperature-mode =3D "thermal-diode"; + }; + }; + + temperature-sensor@4c { + compatible =3D "nuvoton,w83773g"; + reg =3D <0x4c>; + }; +}; + +&i2c5 { + status =3D "okay"; +}; + +&i2c6 { + status =3D "okay"; + + rtc@6f { + compatible =3D "isil,isl1208"; + reg =3D <0x6f>; + }; +}; + +&i2c7 { + status =3D "okay"; + + // BMC FRU + eeprom@57 { + compatible =3D "atmel,24c128"; + reg =3D <0x57>; + + nvmem-layout { + compatible =3D "fixed-layout"; + #address-cells =3D <1>; + #size-cells =3D <1>; + + eth1_macaddress: macaddress@3f80 { + reg =3D <0x3f80 6>; + }; + + eth0_macaddress: macaddress@3f88 { + reg =3D <0x3f88 6>; + }; + }; + }; +}; + +&i2c8 { + status =3D "okay"; + + io_expander0: gpio@1c { + compatible =3D "nxp,pca9557"; + reg =3D <0x1c>; + gpio-controller; + #gpio-cells =3D <2>; + }; +}; + +&i2c9 { + status =3D "okay"; +}; + +&i2c10 { + status =3D "okay"; +}; + +&i2c11 { + status =3D "okay"; +}; + +&i2c12 { + status =3D "okay"; +}; + +&i2c13 { + status =3D "okay"; + + ssif-bmc@10 { + compatible =3D "ssif-bmc"; + reg =3D <0x10>; + }; +}; + +// Connected to host Intel X550 (ALTRAD8UD-1L2T) or +// Broadcom BCM57414 (ALTRAD8UD2-1L2Q) interface +&mac0 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_rmii1_default>; + clocks =3D <&syscon ASPEED_CLK_GATE_MAC1CLK>, + <&syscon ASPEED_CLK_MAC1RCLK>; + clock-names =3D "MACCLK", "RCLK"; + use-ncsi; + nvmem-cells =3D <ð0_macaddress>; + nvmem-cell-names =3D "mac-address"; + + status =3D "okay"; +}; + +// Connected to Realtek RTL8211E +&mac1 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_rgmii2_default &pinctrl_mdio2_default>; + + nvmem-cells =3D <ð1_macaddress>; + nvmem-cell-names =3D "mac-address"; + + status =3D "okay"; +}; + +&pinctrl { + aspeed,external-nodes =3D <&gfx &lhc>; +}; + +&pwm_tacho { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_pwm0_default + &pinctrl_pwm1_default + &pinctrl_pwm2_default + &pinctrl_pwm3_default + &pinctrl_pwm4_default + &pinctrl_pwm5_default + &pinctrl_pwm6_default + &pinctrl_pwm7_default>; + + status =3D "okay"; + + fan@0 { + reg =3D <0x00>; + aspeed,fan-tach-ch =3D /bits/ 8 <0x00 0x08>; + }; + + fan@1 { + reg =3D <0x01>; + aspeed,fan-tach-ch =3D /bits/ 8 <0x01 0x09>; + }; + + fan@2 { + reg =3D <0x02>; + aspeed,fan-tach-ch =3D /bits/ 8 <0x02 0x0a>; + }; + + fan@3 { + reg =3D <0x03>; + aspeed,fan-tach-ch =3D /bits/ 8 <0x03 0x0b>; + }; + + fan@4 { + reg =3D <0x04>; + aspeed,fan-tach-ch =3D /bits/ 8 <0x04 0x0c>; + }; + + fan@5 { + reg =3D <0x05>; + aspeed,fan-tach-ch =3D /bits/ 8 <0x05 0x0d>; + }; + + fan@6 { + reg =3D <0x06>; + aspeed,fan-tach-ch =3D /bits/ 8 <0x06 0x0e>; + }; + + fan@7 { + reg =3D <0x07>; + aspeed,fan-tach-ch =3D /bits/ 8 <0x07 0x0f>; + }; +}; + +&spi1 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_spi1_default>; + + status =3D "okay"; + + // Host BIOS/UEFI EEPROM + flash@0 { + m25p,fast-read; + label =3D "pnor"; + spi-max-frequency =3D <100000000>; + status =3D "okay"; + + partitions { + compatible =3D "fixed-partitions"; + #address-cells =3D <1>; + #size-cells =3D <1>; + + tfa@400000 { + reg =3D <0x400000 0x200000>; + label =3D "pnor-tfa"; + }; + + uefi@600000 { + reg =3D <0x600000 0x1A00000>; + label =3D "pnor-uefi"; + }; + }; + }; +}; + +&uart1 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_txd1_default + &pinctrl_rxd1_default + &pinctrl_ncts1_default + &pinctrl_nrts1_default>; + + status =3D "okay"; +}; + +&uart2 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_txd2_default + &pinctrl_rxd2_default>; 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Thu, 4 Dec 2025 16:03:06 -0500 (EST) From: Rebecca Cran To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Joel Stanley , Andrew Jeffery , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-aspeed@lists.ozlabs.org, linux-kernel@vger.kernel.org Cc: Rebecca Cran , Billy Tsai Subject: [PATCH v3 3/3] dt-bindings: hwmon: (aspeed,g5-pwm-tacho) Move info from txt to yaml Date: Thu, 4 Dec 2025 14:02:36 -0700 Message-ID: <20251204210238.40742-4-rebecca@bsdio.com> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20251204210238.40742-1-rebecca@bsdio.com> References: <20251204210238.40742-1-rebecca@bsdio.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Move the documentation for the aspeed,ast2400-pwm-tacho and aspeed,ast2500-pwm-tacho devices from a text file to yaml file. This allows for dts files containing these devices to be validated. Where the text file documenation of required properties differ from the implementation, prefer the implementation and update the schema to match. "#size-cells" was 1 but implementation is 0. "#cooling-cells" was marked as required but appears optional. In the fan subnode, "cooling-levels" is optional according to the code in drivers/hwmon/aspeed-pwm-tacho.c. Signed-off-by: Rebecca Cran --- Documentation/devicetree/bindings/hwmon/aspeed,pwm-tacho.yaml | 91 +++++++= +++++++++++++ Documentation/devicetree/bindings/hwmon/aspeed-pwm-tacho.txt | 73 -------= --------- 2 files changed, 91 insertions(+), 73 deletions(-) diff --git a/Documentation/devicetree/bindings/hwmon/aspeed,pwm-tacho.yaml = b/Documentation/devicetree/bindings/hwmon/aspeed,pwm-tacho.yaml new file mode 100644 index 000000000000..b23c3519604b --- /dev/null +++ b/Documentation/devicetree/bindings/hwmon/aspeed,pwm-tacho.yaml @@ -0,0 +1,91 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +# Copyright (C) 2023 Aspeed, Inc. +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/hwmon/aspeed,g5-pwm-tacho.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: ASPEED AST2400/AST2500 PWM and Fan Tacho controller + +maintainers: + - Billy Tsai + +description: | + The ASPEED PWM controller can support up to 8 PWM outputs. The ASPEED Fan + Tacho controller can support up to 16 Fan tachometer inputs. + + There can be up to 8 fans supported. Each fan can have one PWM output and + one/two Fan tach inputs. + +properties: + compatible: + enum: + - aspeed,ast2400-pwm-tacho + - aspeed,ast2500-pwm-tacho + + "#address-cells": + const: 1 + + "#size-cells": + const: 0 + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + resets: + maxItems: 1 + +patternProperties: + "^fan@[0-9]+$": + $ref: fan-common.yaml# + unevaluatedProperties: false + properties: + aspeed,fan-tach-ch: + description: + The tach channel used for the fan. + $ref: /schemas/types.yaml#/definitions/uint8-array + + required: + - reg + - aspeed,fan-tach-ch + +required: + - compatible + - "#address-cells" + - "#size-cells" + - reg + - pinctrl-names + - pinctrl-0 + - clocks + - resets + +additionalProperties: false + +examples: + - | + #include + pwm_tacho: pwmtachocontroller@1e786000 { + #address-cells =3D <1>; + #size-cells =3D <0>; + #cooling-cells =3D <2>; + reg =3D <0x1E786000 0x1000>; + compatible =3D "aspeed,ast2500-pwm-tacho"; + clocks =3D <&syscon ASPEED_CLK_APB>; + resets =3D <&syscon ASPEED_RESET_PWM>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_pwm0_default &pinctrl_pwm1_default>; + + fan@0 { + reg =3D <0x00>; + cooling-levels =3D /bits/ 8 <125 151 177 203 229 255>; + aspeed,fan-tach-ch =3D /bits/ 8 <0x00>; + }; + + fan@1 { + reg =3D <0x01>; + aspeed,fan-tach-ch =3D /bits/ 8 <0x01 0x02>; + }; + }; diff --git a/Documentation/devicetree/bindings/hwmon/aspeed-pwm-tacho.txt b= /Documentation/devicetree/bindings/hwmon/aspeed-pwm-tacho.txt deleted file mode 100644 index 8645cd3b867a..000000000000 --- a/Documentation/devicetree/bindings/hwmon/aspeed-pwm-tacho.txt +++ /dev/null @@ -1,73 +0,0 @@ -ASPEED AST2400/AST2500 PWM and Fan Tacho controller device driver - -The ASPEED PWM controller can support upto 8 PWM outputs. The ASPEED Fan T= acho -controller can support upto 16 Fan tachometer inputs. - -There can be upto 8 fans supported. Each fan can have one PWM output and -one/two Fan tach inputs. - -Required properties for pwm-tacho node: -- #address-cells : should be 1. - -- #size-cells : should be 1. - -- #cooling-cells: should be 2. - -- reg : address and length of the register set for the device. - -- pinctrl-names : a pinctrl state named "default" must be defined. - -- pinctrl-0 : phandle referencing pin configuration of the PWM ports. - -- compatible : should be "aspeed,ast2400-pwm-tacho" for AST2400 and - "aspeed,ast2500-pwm-tacho" for AST2500. - -- clocks : phandle to clock provider with the clock number in the second c= ell - -- resets : phandle to reset controller with the reset number in the second= cell - -fan subnode format: -=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D -Under fan subnode there can upto 8 child nodes, with each child node -representing a fan. If there are 8 fans each fan can have one PWM port and -one/two Fan tach inputs. -For PWM port can be configured cooling-levels to create cooling device. -Cooling device could be bound to a thermal zone for the thermal control. - -Required properties for each child node: -- reg : should specify PWM source port. - integer value in the range 0 to 7 with 0 indicating PWM port A and - 7 indicating PWM port H. - -- cooling-levels: PWM duty cycle values in a range from 0 to 255 - which correspond to thermal cooling states. - -- aspeed,fan-tach-ch : should specify the Fan tach input channel. - integer value in the range 0 through 15, with 0 indicating - Fan tach channel 0 and 15 indicating Fan tach channel 15. - At least one Fan tach input channel is required. - -Examples: - -pwm_tacho: pwmtachocontroller@1e786000 { - #address-cells =3D <1>; - #size-cells =3D <1>; - #cooling-cells =3D <2>; - reg =3D <0x1E786000 0x1000>; - compatible =3D "aspeed,ast2500-pwm-tacho"; - clocks =3D <&syscon ASPEED_CLK_APB>; - resets =3D <&syscon ASPEED_RESET_PWM>; - pinctrl-names =3D "default"; - pinctrl-0 =3D <&pinctrl_pwm0_default &pinctrl_pwm1_default>; - - fan@0 { - reg =3D <0x00>; - cooling-levels =3D /bits/ 8 <125 151 177 203 229 255>; - aspeed,fan-tach-ch =3D /bits/ 8 <0x00>; - }; - - fan@1 { - reg =3D <0x01>; - aspeed,fan-tach-ch =3D /bits/ 8 <0x01 0x02>; - }; -}; --=20 2.47.3