From nobody Fri Dec 19 19:01:20 2025 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.13]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 61E25326D77 for ; Thu, 4 Dec 2025 20:54:24 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.13 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764881667; cv=none; b=kU/2kuwDftuxqD42wfhsv18Fa3G8o2pdOq8fpOjZDUxmS7PtVQImWCYSsDdrR43Q5Z8abvSrQNNgGQ+fFZRYPTmN1JEOxpH37dJN9D2yq5qdExiL2bl5LHem0E0H/njy5oyMnMSIl1u0sB9GihmJ4eFbDknvLAkbuzVE1549cx8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764881667; c=relaxed/simple; bh=5vWaOQZcSEmnlAOkjv9XHLHkBufwrmqBLbyXGGLw3Eo=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=oC+TMUdeQ21yvL6lKNR3Whk18cr5bMYZFc2MLKVFcfcAVMdtUaZgwOX83u2PDwQx9bZY/nb3jDIH10YsdDSDn0RDjrq9aTtWQmaxzpH415/Ijstf/xMWTQIFgyxz9+o1yaRVKjyDyIc/KA3LOEu6TNSAqJ5KfMYO6/lvpo2pBs0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=HA5OUcMT; arc=none smtp.client-ip=192.198.163.13 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="HA5OUcMT" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1764881664; x=1796417664; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=5vWaOQZcSEmnlAOkjv9XHLHkBufwrmqBLbyXGGLw3Eo=; b=HA5OUcMTUko9ZW2mw2vzqOwWMfj+qiTFwg4SzBGFP+eqbCNzu1GNI3Vb TA5BDH+Fe7T8EuuTjBeTRDdjTlnJLKTDap7C+smKoYBIdImvuiKOwMq8N QBvB9uX25OtsnmLWCEBLtqfSlCQPNwHiC7fg/KprIqFQYGcZUYIDmXy/s XskkFEHAJTo7U3fx5mLEMgRJxzRZKFoxgo0AoQdLTe+/xoqFv6xwXNWsU nv7OpT864FbRZU6dhgbN7WPTNe4Rc4D1hv+unUvOMrDYnlm51UzNytkMP aJRAlijF+bEJJiJWPJ+3lJ2/FQ//0puSQFjIZVPpdpd9CdpY5WK3jNkw4 w==; X-CSE-ConnectionGUID: Z8TVDdq8TYqAOLJrtD9TKQ== X-CSE-MsgGUID: UNjkRw9LTJ2ERMPhgeTKKw== X-IronPort-AV: E=McAfee;i="6800,10657,11632"; a="69510934" X-IronPort-AV: E=Sophos;i="6.20,250,1758610800"; d="scan'208";a="69510934" Received: from orviesa002.jf.intel.com ([10.64.159.142]) by fmvoesa107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Dec 2025 12:54:20 -0800 X-CSE-ConnectionGUID: skGn2I/hQv+bUCqU2Cac2Q== X-CSE-MsgGUID: CAJmVeKoTJSF/6osynOdUQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.20,250,1758610800"; d="scan'208";a="225752765" Received: from mgerlach-mobl1.amr.corp.intel.com (HELO agluck-desk3.intel.com) ([10.124.220.165]) by orviesa002-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Dec 2025 12:54:19 -0800 From: Tony Luck To: Fenghua Yu , Reinette Chatre , Maciej Wieczor-Retman , Peter Newman , James Morse , Babu Moger , Drew Fustini , Dave Martin , Chen Yu Cc: x86@kernel.org, linux-kernel@vger.kernel.org, patches@lists.linux.dev, Tony Luck Subject: [PATCH v15 11/32] x86,fs/resctrl: Handle events that can be read from any CPU Date: Thu, 4 Dec 2025 12:53:41 -0800 Message-ID: <20251204205404.12763-12-tony.luck@intel.com> X-Mailer: git-send-email 2.51.1 In-Reply-To: <20251204205404.12763-1-tony.luck@intel.com> References: <20251204205404.12763-1-tony.luck@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" resctrl assumes that monitor events can only be read from a CPU in the cpumask_t set of each domain. This is true for x86 events accessed with an MSR interface, but may not be true for other access methods such as MMIO. Introduce and use flag mon_evt::any_cpu, settable by architecture, that indicates there are no restrictions on which CPU can read that event. Signed-off-by: Tony Luck --- include/linux/resctrl.h | 2 +- fs/resctrl/internal.h | 2 ++ arch/x86/kernel/cpu/resctrl/core.c | 6 +++--- fs/resctrl/ctrlmondata.c | 6 ++++++ fs/resctrl/monitor.c | 9 ++++++--- 5 files changed, 18 insertions(+), 7 deletions(-) diff --git a/include/linux/resctrl.h b/include/linux/resctrl.h index 79aaaabcdd3f..22c5d07fe9ff 100644 --- a/include/linux/resctrl.h +++ b/include/linux/resctrl.h @@ -412,7 +412,7 @@ u32 resctrl_arch_get_num_closid(struct rdt_resource *r); u32 resctrl_arch_system_num_rmid_idx(void); int resctrl_arch_update_domains(struct rdt_resource *r, u32 closid); =20 -void resctrl_enable_mon_event(enum resctrl_event_id eventid); +void resctrl_enable_mon_event(enum resctrl_event_id eventid, bool any_cpu); =20 bool resctrl_is_mon_event_enabled(enum resctrl_event_id eventid); =20 diff --git a/fs/resctrl/internal.h b/fs/resctrl/internal.h index 86cf38ab08a7..fb0b6e40d022 100644 --- a/fs/resctrl/internal.h +++ b/fs/resctrl/internal.h @@ -61,6 +61,7 @@ static inline struct rdt_fs_context *rdt_fc2context(struc= t fs_context *fc) * READS_TO_REMOTE_MEM) being tracked by @evtid. * Only valid if @evtid is an MBM event. * @configurable: true if the event is configurable + * @any_cpu: true if the event can be read from any CPU * @enabled: true if the event is enabled */ struct mon_evt { @@ -69,6 +70,7 @@ struct mon_evt { char *name; u32 evt_cfg; bool configurable; + bool any_cpu; bool enabled; }; =20 diff --git a/arch/x86/kernel/cpu/resctrl/core.c b/arch/x86/kernel/cpu/resct= rl/core.c index b3a2dc56155d..bd4a98106153 100644 --- a/arch/x86/kernel/cpu/resctrl/core.c +++ b/arch/x86/kernel/cpu/resctrl/core.c @@ -902,15 +902,15 @@ static __init bool get_rdt_mon_resources(void) bool ret =3D false; =20 if (rdt_cpu_has(X86_FEATURE_CQM_OCCUP_LLC)) { - resctrl_enable_mon_event(QOS_L3_OCCUP_EVENT_ID); + resctrl_enable_mon_event(QOS_L3_OCCUP_EVENT_ID, false); ret =3D true; } if (rdt_cpu_has(X86_FEATURE_CQM_MBM_TOTAL)) { - resctrl_enable_mon_event(QOS_L3_MBM_TOTAL_EVENT_ID); + resctrl_enable_mon_event(QOS_L3_MBM_TOTAL_EVENT_ID, false); ret =3D true; } if (rdt_cpu_has(X86_FEATURE_CQM_MBM_LOCAL)) { - resctrl_enable_mon_event(QOS_L3_MBM_LOCAL_EVENT_ID); + resctrl_enable_mon_event(QOS_L3_MBM_LOCAL_EVENT_ID, false); ret =3D true; } if (rdt_cpu_has(X86_FEATURE_ABMC)) diff --git a/fs/resctrl/ctrlmondata.c b/fs/resctrl/ctrlmondata.c index 7f9b2fed117a..2c69fcd70eeb 100644 --- a/fs/resctrl/ctrlmondata.c +++ b/fs/resctrl/ctrlmondata.c @@ -578,6 +578,11 @@ void mon_event_read(struct rmid_read *rr, struct rdt_r= esource *r, } } =20 + if (evt->any_cpu) { + mon_event_count(rr); + goto out_ctx_free; + } + cpu =3D cpumask_any_housekeeping(cpumask, RESCTRL_PICK_ANY_CPU); =20 /* @@ -591,6 +596,7 @@ void mon_event_read(struct rmid_read *rr, struct rdt_re= source *r, else smp_call_on_cpu(cpu, smp_mon_event_count, rr, false); =20 +out_ctx_free: if (rr->arch_mon_ctx) resctrl_arch_mon_ctx_free(r, evt->evtid, rr->arch_mon_ctx); } diff --git a/fs/resctrl/monitor.c b/fs/resctrl/monitor.c index 340b847ab397..081ff659b52c 100644 --- a/fs/resctrl/monitor.c +++ b/fs/resctrl/monitor.c @@ -518,10 +518,12 @@ static int __mon_event_count(struct rdtgroup *rdtgrp,= struct rmid_read *rr) { switch (rr->r->rid) { case RDT_RESOURCE_L3: - if (rr->hdr) + if (rr->hdr) { + WARN_ON_ONCE(rr->evt->any_cpu); return __l3_mon_event_count(rdtgrp, rr); - else + } else { return __l3_mon_event_count_sum(rdtgrp, rr); + } default: rr->err =3D -EINVAL; return -EINVAL; @@ -987,7 +989,7 @@ struct mon_evt mon_event_all[QOS_NUM_EVENTS] =3D { }, }; =20 -void resctrl_enable_mon_event(enum resctrl_event_id eventid) +void resctrl_enable_mon_event(enum resctrl_event_id eventid, bool any_cpu) { if (WARN_ON_ONCE(eventid < QOS_FIRST_EVENT || eventid >=3D QOS_NUM_EVENTS= )) return; @@ -996,6 +998,7 @@ void resctrl_enable_mon_event(enum resctrl_event_id eve= ntid) return; } =20 + mon_event_all[eventid].any_cpu =3D any_cpu; mon_event_all[eventid].enabled =3D true; } =20 --=20 2.51.1