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Thu, 04 Dec 2025 08:13:19 -0800 (PST) Received: from NB-6746.corp.yadro.com ([188.243.183.84]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-597d7c283c9sm612087e87.79.2025.12.04.08.13.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 04 Dec 2025 08:13:19 -0800 (PST) From: Artem Shimko To: Mika Westerberg , Andy Shevchenko , Jan Dabros , Andi Shyti Cc: Artem Shimko , linux-i2c@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v3] i2c: designware: Replace magic numbers with named constants Date: Thu, 4 Dec 2025 19:13:08 +0300 Message-ID: <20251204161309.750032-1-a.shimko.dev@gmail.com> X-Mailer: git-send-email 2.43.0 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Replace various magic numbers with properly named constants to improve code readability and maintainability. This includes constants for register access, timing adjustments, timeouts, FIFO parameters, and default values. The change makes the code more self-documenting without altering any functionality. Signed-off-by: Artem Shimko --- Hello maintainers and reviewers, Fix replaces magic numbers throughout the DesignWare I2C driver with named=20 constants to improve code readability and maintainability. The change introduces constants for register access, timing adjustments,=20 timeouts, FIFO parameters, and default values, all properly documented=20 with comments. No functional changes. Thank you for your consideration. -- Regards, Artem ChangeLog: v1: * https://lore.kernel.org/all/20251105161845.2535367-1-a.shimko.dev@gma= il.com/T/#u v2: * https://lore.kernel.org/all/20251106160206.2617785-1-a.shimko.dev@gma= il.com/T/#u v3: * Add missing include for linux/bitfield.h drivers/i2c/busses/i2c-designware-common.c | 33 ++++++++++++++-------- drivers/i2c/busses/i2c-designware-core.h | 13 +++++++++ 2 files changed, 35 insertions(+), 11 deletions(-) diff --git a/drivers/i2c/busses/i2c-designware-common.c b/drivers/i2c/busse= s/i2c-designware-common.c index 5b1e8f74c4ac..3bc55068da03 100644 --- a/drivers/i2c/busses/i2c-designware-common.c +++ b/drivers/i2c/busses/i2c-designware-common.c @@ -12,6 +12,7 @@ #define DEFAULT_SYMBOL_NAMESPACE "I2C_DW_COMMON" =20 #include +#include #include #include #include @@ -34,6 +35,14 @@ =20 #include "i2c-designware-core.h" =20 +#define DW_IC_DEFAULT_BUS_CAPACITANCE_PF 100 + +#define DW_IC_ABORT_TIMEOUT_US 10 +#define DW_IC_ABORT_TOTAL_TIMEOUT_US 100 + +#define DW_IC_BUSY_POLL_TIMEOUT_US 1100 +#define DW_IC_BUSY_TOTAL_TIMEOUT_US 20000 + static const char *const abort_sources[] =3D { [ABRT_7B_ADDR_NOACK] =3D "slave address not acknowledged (7bit mode)", @@ -106,7 +115,7 @@ static int dw_reg_read_word(void *context, unsigned int= reg, unsigned int *val) struct dw_i2c_dev *dev =3D context; =20 *val =3D readw(dev->base + reg) | - (readw(dev->base + reg + 2) << 16); + (readw(dev->base + reg + DW_IC_REG_STEP_BYTES) << DW_IC_REG_WORD_SHIFT); =20 return 0; } @@ -116,7 +125,7 @@ static int dw_reg_write_word(void *context, unsigned in= t reg, unsigned int val) struct dw_i2c_dev *dev =3D context; =20 writew(val, dev->base + reg); - writew(val >> 16, dev->base + reg + 2); + writew(val >> DW_IC_REG_WORD_SHIFT, dev->base + reg + DW_IC_REG_STEP_BYTE= S); =20 return 0; } @@ -165,7 +174,7 @@ int i2c_dw_init_regmap(struct dw_i2c_dev *dev) if (reg =3D=3D swab32(DW_IC_COMP_TYPE_VALUE)) { map_cfg.reg_read =3D dw_reg_read_swab; map_cfg.reg_write =3D dw_reg_write_swab; - } else if (reg =3D=3D (DW_IC_COMP_TYPE_VALUE & 0x0000ffff)) { + } else if (reg =3D=3D lower_16_bits(DW_IC_COMP_TYPE_VALUE)) { map_cfg.reg_read =3D dw_reg_read_word; map_cfg.reg_write =3D dw_reg_write_word; } else if (reg !=3D DW_IC_COMP_TYPE_VALUE) { @@ -384,7 +393,7 @@ int i2c_dw_fw_parse_and_configure(struct dw_i2c_dev *de= v) i2c_parse_fw_timings(device, t, false); =20 if (device_property_read_u32(device, "snps,bus-capacitance-pf", &dev->bus= _capacitance_pF)) - dev->bus_capacitance_pF =3D 100; + dev->bus_capacitance_pF =3D DW_IC_DEFAULT_BUS_CAPACITANCE_PF; =20 dev->clk_freq_optimized =3D device_property_read_bool(device, "snps,clk-f= req-optimized"); =20 @@ -539,8 +548,9 @@ void __i2c_dw_disable(struct dw_i2c_dev *dev) =20 regmap_write(dev->map, DW_IC_ENABLE, enable | DW_IC_ENABLE_ABORT); ret =3D regmap_read_poll_timeout(dev->map, DW_IC_ENABLE, enable, - !(enable & DW_IC_ENABLE_ABORT), 10, - 100); + !(enable & DW_IC_ENABLE_ABORT), + DW_IC_ABORT_TIMEOUT_US, + DW_IC_ABORT_TOTAL_TIMEOUT_US); if (ret) dev_err(dev->dev, "timeout while trying to abort current transfer\n"); } @@ -552,7 +562,7 @@ void __i2c_dw_disable(struct dw_i2c_dev *dev) * in that case this test reads zero and exits the loop. */ regmap_read(dev->map, DW_IC_ENABLE_STATUS, &status); - if ((status & 1) =3D=3D 0) + if (!(status & 1)) return; =20 /* @@ -635,7 +645,8 @@ int i2c_dw_wait_bus_not_busy(struct dw_i2c_dev *dev) =20 ret =3D regmap_read_poll_timeout(dev->map, DW_IC_STATUS, status, !(status & DW_IC_STATUS_ACTIVITY), - 1100, 20000); + DW_IC_BUSY_POLL_TIMEOUT_US, + DW_IC_BUSY_TOTAL_TIMEOUT_US); if (ret) { dev_warn(dev->dev, "timeout waiting for bus ready\n"); =20 @@ -699,12 +710,12 @@ int i2c_dw_set_fifo_size(struct dw_i2c_dev *dev) if (ret) return ret; =20 - tx_fifo_depth =3D ((param >> 16) & 0xff) + 1; - rx_fifo_depth =3D ((param >> 8) & 0xff) + 1; + tx_fifo_depth =3D FIELD_GET(DW_IC_FIFO_TX_FIELD, param) + 1; + rx_fifo_depth =3D FIELD_GET(DW_IC_FIFO_RX_FIELD, param) + 1; if (!dev->tx_fifo_depth) { dev->tx_fifo_depth =3D tx_fifo_depth; dev->rx_fifo_depth =3D rx_fifo_depth; - } else if (tx_fifo_depth >=3D 2) { + } else if (tx_fifo_depth >=3D DW_IC_FIFO_MIN_DEPTH) { dev->tx_fifo_depth =3D min_t(u32, dev->tx_fifo_depth, tx_fifo_depth); dev->rx_fifo_depth =3D min_t(u32, dev->rx_fifo_depth, diff --git a/drivers/i2c/busses/i2c-designware-core.h b/drivers/i2c/busses/= i2c-designware-core.h index 347843b4f5dd..a699953bf5ae 100644 --- a/drivers/i2c/busses/i2c-designware-core.h +++ b/drivers/i2c/busses/i2c-designware-core.h @@ -41,6 +41,19 @@ #define DW_IC_DATA_CMD_DAT GENMASK(7, 0) #define DW_IC_DATA_CMD_FIRST_DATA_BYTE BIT(11) =20 +/* + * Register access parameters + */ +#define DW_IC_REG_STEP_BYTES 2 +#define DW_IC_REG_WORD_SHIFT 16 + +/* + * FIFO depth configuration + */ +#define DW_IC_FIFO_TX_FIELD GENMASK(23, 16) +#define DW_IC_FIFO_RX_FIELD GENMASK(15, 8) +#define DW_IC_FIFO_MIN_DEPTH 2 + /* * Registers offset */ --=20 2.43.0