From nobody Fri Dec 19 21:12:41 2025 Received: from out28-52.mail.aliyun.com (out28-52.mail.aliyun.com [115.124.28.52]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CBB834502F for ; Thu, 4 Dec 2025 02:54:20 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=115.124.28.52 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764816865; cv=none; b=tzLP582przOkPSWKVnlB0SvZ9//TGj23a1B1kePkhY+Sj3K0TboeoSZj3ibhi0vF/azKY69x+1d4Oj+SR1W+Tl3liSO4UY9n6mzztV/eg8S963Wz2nRMAOWzspsRxtN6+a91wGzArnQMzmDHqYrRD7oaSeu+85/54OZqtvGSQzc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764816865; c=relaxed/simple; bh=LyRMQf8XZ7fapz5OJwZ0rSQSZvBkGzFU0/d7jbNT8DM=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=tArt7wNUJ/Cd30uhGs2pXE3v/FK/VM12nQ2abJaD9WTNHoDQuESJ7hLJ14WDq/7e/c68TaqTF6PkbOZ3QdVtZjW3bp1RzlDysLzbMiiU36ABrpXop1+QKlhJTDRjV7R8JLVe9ydbwuyFwCySA+L8hcAn3XmTals6gYQVHF+164o= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=open-hieco.net; spf=pass smtp.mailfrom=open-hieco.net; arc=none smtp.client-ip=115.124.28.52 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=open-hieco.net Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=open-hieco.net Received: from localhost.localdomain(mailfrom:shenxiaochen@open-hieco.net fp:SMTPD_---.fcVtMUP_1764815921 cluster:ay29) by smtp.aliyun-inc.com; Thu, 04 Dec 2025 10:38:44 +0800 From: Xiaochen Shen To: tony.luck@intel.com, reinette.chatre@intel.com, bp@alien8.de, fenghuay@nvidia.com Cc: babu.moger@amd.com, james.morse@arm.com, Dave.Martin@arm.com, x86@kernel.org, linux-kernel@vger.kernel.org, shenxiaochen@open-hieco.net Subject: [PATCH 2/2] x86/resctrl: Fix memory bandwidth counter width for Hygon Date: Thu, 4 Dec 2025 10:37:50 +0800 Message-ID: <20251204023750.994143-3-shenxiaochen@open-hieco.net> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20251204023750.994143-1-shenxiaochen@open-hieco.net> References: <20251204023750.994143-1-shenxiaochen@open-hieco.net> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The memory bandwidth calculation relies on reading the hardware counter and measuring the delta between samples. To ensure accurate measurement, the software reads the counter frequently enough to prevent it from rolling over twice between reads. The default Memory Bandwidth Monitoring (MBM) counter width is 24 bits. Hygon CPUs provide a 32-bit width counter, but they do not support the MBM capability CPUID leaf (0xF.[ECX=3D1]:EAX) to report the width offset (from 24 bits). Consequently, the kernel falls back to the 24-bit default counter width, which causes incorrect overflow handling on Hygon CPUs. Fix this by explicitly setting the counter width offset to 8 bits (resulting in a 32-bit total counter width) for Hygon CPUs. Fixes: d8df126349da ("x86/cpu/hygon: Add missing resctrl_cpu_detect() in bs= p_init helper") Fixes: 923f3a2b48bd ("x86/resctrl: Query LLC monitoring properties once dur= ing boot") Cc: stable@vger.kernel.org Signed-off-by: Xiaochen Shen Reviewed-by: Tony Luck --- arch/x86/kernel/cpu/resctrl/core.c | 15 +++++++++++++-- arch/x86/kernel/cpu/resctrl/internal.h | 3 +++ 2 files changed, 16 insertions(+), 2 deletions(-) diff --git a/arch/x86/kernel/cpu/resctrl/core.c b/arch/x86/kernel/cpu/resct= rl/core.c index 10de1594d328..6ebff44a3f75 100644 --- a/arch/x86/kernel/cpu/resctrl/core.c +++ b/arch/x86/kernel/cpu/resctrl/core.c @@ -1021,8 +1021,19 @@ void resctrl_cpu_detect(struct cpuinfo_x86 *c) c->x86_cache_occ_scale =3D ebx; c->x86_cache_mbm_width_offset =3D eax & 0xff; =20 - if (c->x86_vendor =3D=3D X86_VENDOR_AMD && !c->x86_cache_mbm_width_offse= t) - c->x86_cache_mbm_width_offset =3D MBM_CNTR_WIDTH_OFFSET_AMD; + if (!c->x86_cache_mbm_width_offset) { + switch (c->x86_vendor) { + case X86_VENDOR_AMD: + c->x86_cache_mbm_width_offset =3D MBM_CNTR_WIDTH_OFFSET_AMD; + break; + case X86_VENDOR_HYGON: + c->x86_cache_mbm_width_offset =3D MBM_CNTR_WIDTH_OFFSET_HYGON; + break; + default: + /* Leave c->x86_cache_mbm_width_offset as 0 */ + break; + } + } } } =20 diff --git a/arch/x86/kernel/cpu/resctrl/internal.h b/arch/x86/kernel/cpu/r= esctrl/internal.h index 4a916c84a322..79c18657ede0 100644 --- a/arch/x86/kernel/cpu/resctrl/internal.h +++ b/arch/x86/kernel/cpu/resctrl/internal.h @@ -14,6 +14,9 @@ =20 #define MBM_CNTR_WIDTH_OFFSET_AMD 20 =20 +/* Hygon MBM counter width as an offset from MBM_CNTR_WIDTH_BASE */ +#define MBM_CNTR_WIDTH_OFFSET_HYGON 8 + #define RMID_VAL_ERROR BIT_ULL(63) =20 #define RMID_VAL_UNAVAIL BIT_ULL(62) --=20 2.47.3