From nobody Sun Feb 8 07:21:46 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 664F62F657A; Thu, 4 Dec 2025 16:32:47 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764865967; cv=none; b=i3jZrs15oNZnA6Yo6cFUZdTqfzk9E/CjHWzTdQsd4XI7HpPIcLMUnci5h76/tdM/D9A21HJQM4Lc8hWK8OkasGFt+XIsQ+2asOTbGwbWrkiP+SaiIcGPso5Qw3LQ/6RVdVAFMGc2Tyrjj48wGzCZLEop5/D19nhjaE+EH8yzDb8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764865967; c=relaxed/simple; bh=O0VSdYVLQ03hNWa2dtSXZv8m0AqnGu38C6aAyY/kdv4=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=tXQIolr0ZcirkIeKi6hTVxm1r1jf07T6alKfD7Ch61CQPCdyEUs4JQCjBF4khbYW7fJrnbE27zL9O2MuTFtJCrRX9sD9G7T+j/+GMrZe8U8KbdxdpMVBfGUUkVcfjYYgEEz+h05qldQbUBoQEyb+jdfDfhNkUAXghUbGUTLs3Xk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=madw//cp; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="madw//cp" Received: by smtp.kernel.org (Postfix) with ESMTPS id EE449C116D0; Thu, 4 Dec 2025 16:32:46 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1764865967; bh=O0VSdYVLQ03hNWa2dtSXZv8m0AqnGu38C6aAyY/kdv4=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=madw//cp3zydh2bdEhoexF6p52XH7ddI54fzH642dLuleNsUljQ8jV64CFyb4Cwl7 4Uaieccz6DJbo7O882UvgZC5FkckiXmZ1MdYXe/Ag+D9fCc4TmOxnsnK7imQm2GAHg lByU4fCCmBxsxT4IXLTzpBDZRkJmZBLpgUNZLAcr3Rq2rZlRqplbDQfUC9VxuqGoqV KQr83/6Orze+/hN+LihARHL8EIhfxjmMsp/FKbqAk6U5mSuRH12b76YcaVxPgPFyIH O8iMMg3PDSVGc/K7R6sZ4kfMhNvT2caah9l7xtH1TjOeUPPsIUScPfRRp6855jgOwu 4ihjH5ZePl+NQ== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id DBCEAD216B0; Thu, 4 Dec 2025 16:32:46 +0000 (UTC) From: David Heidelberg via B4 Relay Date: Thu, 04 Dec 2025 17:32:35 +0100 Subject: [PATCH WIP v2 1/8] media: qcom: camss: csiphy: Introduce PHY configuration Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251204-qcom-cphy-v2-1-6b35ef8b071e@ixit.cz> References: <20251204-qcom-cphy-v2-0-6b35ef8b071e@ixit.cz> In-Reply-To: <20251204-qcom-cphy-v2-0-6b35ef8b071e@ixit.cz> To: Robert Foss , Todor Tomov , Bryan O'Donoghue , Vladimir Zapolskiy , Mauro Carvalho Chehab , Luca Weiss , Petr Hodina , Casey Connolly , "Dr. Git" Cc: Joel Selvaraj , Kieran Bingham , Sakari Ailus , linux-media@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, phone-devel@vger.kernel.org, David Heidelberg X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=openpgp-sha256; l=2442; i=david@ixit.cz; h=from:subject:message-id; bh=xEPoDiy43IGVbS6hFNBkYfzUa5KA1Mw5KmgqffUeD6M=; b=owEBbQKS/ZANAwAIAWACP8TTSSByAcsmYgBpMbesc0tnVqr8cwPWlSiKcumYfxuzqIBw0NK6/ RHWgXEXgRqJAjMEAAEIAB0WIQTXegnP7twrvVOnBHRgAj/E00kgcgUCaTG3rAAKCRBgAj/E00kg csg0EAC6bEUcxHMUs9HLM6R7beX56GcmLnId0ppw1WPOdqf3B5rCR0rMjXEXmEYW254tKeV2wdj QcrZc0xPVZcJGBq/+dfR8bA+Ox32uTRuxRbB2OiTGgDlNtGbjdsK50gJuKcpL7wuJvy5XeVsJL1 ZrUvTTRJph4LkgfbnTk0uqM6np3ZnnGn65pKFAMU2IxiaDFCAM7xIrgTTQo9H2Y7IwnMtag2PGR yXDUKaasAfStJWB29TV1xdx9x7ExXrhAOrIMRpkW7c1pejrpjiaftdR0HgYADUGpyVkRgJCpo06 pUNXLecS/Itf1woDLgQhgfLss6zzjce2YhoVqKbAKhq+SyKTyXjsLEGrJM9e10iCID8WMb2O02n /yL9ku9xRuKY631d1Ix4CipAfCGo36Hi/jgvMpKIeo3Fqg0AGDPJT6FrGDl9SPeMx10OMUwPdeJ 4WNxDBkKr2CnfUm5o90iwv8bwFTYDLlukEguerLjBa42HLLhyLLpofjxIYsOnr48bqvePxwWNwM TlawIvsVykbZhVEXNrqLB76L0cfV0RT6DGfhlse7q9j1jdwEYuouTXB++uT3CIud3eb+swP8VT8 cDebvDNWJWwsWXq+KSuWM0munN1LcUzcSt7rsgAH2bGGGxm4psk1GkAluTyrwy4k85CFB5Pfgjs slK4G+k3Ig6NZKA== X-Developer-Key: i=david@ixit.cz; a=openpgp; fpr=D77A09CFEEDC2BBD53A7047460023FC4D3492072 X-Endpoint-Received: by B4 Relay for david@ixit.cz/default with auth_id=355 X-Original-From: David Heidelberg Reply-To: david@ixit.cz From: David Heidelberg Read PHY configuration from the device-tree bus-type and save it into the c= siphy structure for later use. For C-PHY, skip clock line configuration, as there is none. Signed-off-by: David Heidelberg --- drivers/media/platform/qcom/camss/camss-csiphy.h | 2 ++ drivers/media/platform/qcom/camss/camss.c | 18 +++++++++++------- 2 files changed, 13 insertions(+), 7 deletions(-) diff --git a/drivers/media/platform/qcom/camss/camss-csiphy.h b/drivers/med= ia/platform/qcom/camss/camss-csiphy.h index 895f80003c441..8dcd933b151ec 100644 --- a/drivers/media/platform/qcom/camss/camss-csiphy.h +++ b/drivers/media/platform/qcom/camss/camss-csiphy.h @@ -28,11 +28,13 @@ struct csiphy_lane { =20 /** * struct csiphy_lanes_cfg - CSIPHY lanes configuration + * @phy_cfg: interface selection (C-PHY or D-PHY) * @num_data: number of data lanes * @data: data lanes configuration * @clk: clock lane configuration (only for D-PHY) */ struct csiphy_lanes_cfg { + enum v4l2_mbus_type phy_cfg; int num_data; struct csiphy_lane *data; struct csiphy_lane clk; diff --git a/drivers/media/platform/qcom/camss/camss.c b/drivers/media/plat= form/qcom/camss/camss.c index fcc2b2c3cba07..414646760ae6b 100644 --- a/drivers/media/platform/qcom/camss/camss.c +++ b/drivers/media/platform/qcom/camss/camss.c @@ -4043,11 +4043,11 @@ static int camss_of_parse_endpoint_node(struct devi= ce *dev, if (ret) return ret; =20 - /* - * Most SoCs support both D-PHY and C-PHY standards, but currently only - * D-PHY is supported in the driver. - */ - if (vep.bus_type !=3D V4L2_MBUS_CSI2_DPHY) { + switch (vep.bus_type) { + case V4L2_MBUS_CSI2_CPHY: + case V4L2_MBUS_CSI2_DPHY: + break; + default: dev_err(dev, "Unsupported bus type %d\n", vep.bus_type); return -EINVAL; } @@ -4055,9 +4055,13 @@ static int camss_of_parse_endpoint_node(struct devic= e *dev, csd->interface.csiphy_id =3D vep.base.port; =20 mipi_csi2 =3D &vep.bus.mipi_csi2; - lncfg->clk.pos =3D mipi_csi2->clock_lane; - lncfg->clk.pol =3D mipi_csi2->lane_polarities[0]; lncfg->num_data =3D mipi_csi2->num_data_lanes; + lncfg->phy_cfg =3D vep.bus_type; + + if (lncfg->phy_cfg !=3D V4L2_MBUS_CSI2_CPHY) { + lncfg->clk.pos =3D mipi_csi2->clock_lane; + lncfg->clk.pol =3D mipi_csi2->lane_polarities[0]; + } =20 lncfg->data =3D devm_kcalloc(dev, lncfg->num_data, sizeof(*lncfg->data), --=20 2.51.0 From nobody Sun Feb 8 07:21:46 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 69E1D2F691E; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251204-qcom-cphy-v2-2-6b35ef8b071e@ixit.cz> References: <20251204-qcom-cphy-v2-0-6b35ef8b071e@ixit.cz> In-Reply-To: <20251204-qcom-cphy-v2-0-6b35ef8b071e@ixit.cz> To: Robert Foss , Todor Tomov , Bryan O'Donoghue , Vladimir Zapolskiy , Mauro Carvalho Chehab , Luca Weiss , Petr Hodina , Casey Connolly , "Dr. Git" Cc: Joel Selvaraj , Kieran Bingham , Sakari Ailus , linux-media@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, phone-devel@vger.kernel.org, David Heidelberg X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=openpgp-sha256; l=2870; i=david@ixit.cz; h=from:subject:message-id; bh=zMHCyEJPdxX9cis7L+GGrY7/CXmo0Mx11zOGySF6/qI=; b=owEBbQKS/ZANAwAIAWACP8TTSSByAcsmYgBpMbesUfOFn4Vy+wbIv2D+YGLZke2bctd6Vo1AA YwOJC2tbp6JAjMEAAEIAB0WIQTXegnP7twrvVOnBHRgAj/E00kgcgUCaTG3rAAKCRBgAj/E00kg cqOKEACp5uzdPKtSfwWGzBCqJ+JHTo0Al2kmtIfTe3mrR/Rj5CKSfbNsQcO/4hjL6mUfYVBlq+E sd5aR3VO8N0Y6Geuo1tusyac0Fd3YDwSJv/AIXaV4qRHQiF/6dg+KI4jZNsxL4GuK6FzNkSGLdz 1RnbTlJlOwEEE6Fw7Ujbj3yXqfP7FgZPa1EKGKSLSsW7koEOnRHDmFEaOJ4VkMrU7tvaVuWbF7s PLl3ZrDVlVMCIv3VPMSiVDrPUM7a4ycgejo/4U22o8SUZSum7HeQjviLLQ94fEY3PYFJCqTPdRA lN6DOuQzapeEpHWqj/GtOf2ccgVIiHzclWuUQbJKpdWAiTaJaNEnYTKuNSkjWdsx01JKCrviVvN qFQBk5jTwQzHFQEiIQqhLzKxbqPztNxLIjKU6vZl8NLgEdK7L85pYbq0QMM2WQKdck3ZMS784U2 POkiv18fYHIJDJeBC8Q1X0mV3TKIcfgmF/5a9P5VT5sYoxGTEmMuCyXjgpdUcJiXwesAHWxnpy9 KDh9mkoVNNVqT6yh6KPcbNQnyJMGpV16HBeuyee6Lv5MnZZFvcGuv/w9YKFRDtukwb8NU4Cf9E1 w1IXZL7JF34M26COddoN4izdNeALsU3d+b6cCf3+POaKjLl/WhpoNo6ZkY5+I0jvOK1L5aQtX7J gM+EVELMa7hsL/A== X-Developer-Key: i=david@ixit.cz; a=openpgp; fpr=D77A09CFEEDC2BBD53A7047460023FC4D3492072 X-Endpoint-Received: by B4 Relay for david@ixit.cz/default with auth_id=355 X-Original-From: David Heidelberg Reply-To: david@ixit.cz From: David Heidelberg So far, only D-PHY mode was supported, which uses even bits when enabling or masking lanes. For C-PHY configuration, the hardware instead requires using the odd bits. Signed-off-by: David Heidelberg --- .../platform/qcom/camss/camss-csiphy-3ph-1-0.c | 41 +++++++++++++++++-= ---- 1 file changed, 33 insertions(+), 8 deletions(-) diff --git a/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c b/dri= vers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c index 619abbf607813..9ff79f789fa06 100644 --- a/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c +++ b/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c @@ -14,6 +14,7 @@ #include #include #include +#include =20 #define CSIPHY_3PH_LNn_CFG1(n) (0x000 + 0x100 * (n)) #define CSIPHY_3PH_LNn_CFG1_SWI_REC_DLY_PRG (BIT(7) | BIT(6)) @@ -987,13 +988,22 @@ static void csiphy_gen2_config_lanes(struct csiphy_de= vice *csiphy, =20 static u8 csiphy_get_lane_mask(struct csiphy_lanes_cfg *lane_cfg) { - u8 lane_mask; - int i; + u8 lane_mask =3D 0; =20 - lane_mask =3D CSIPHY_3PH_CMN_CSI_COMMON_CTRL5_CLK_ENABLE; + switch (lane_cfg->phy_cfg) { + case V4L2_MBUS_CSI2_CPHY: + for (int i =3D 0; i < lane_cfg->num_data; i++) + lane_mask |=3D (1 << lane_cfg->data[i].pos) + 1; + break; + case V4L2_MBUS_CSI2_DPHY: + lane_mask =3D CSIPHY_3PH_CMN_CSI_COMMON_CTRL5_CLK_ENABLE; =20 - for (i =3D 0; i < lane_cfg->num_data; i++) - lane_mask |=3D 1 << lane_cfg->data[i].pos; + for (int i =3D 0; i < lane_cfg->num_data; i++) + lane_mask |=3D 1 << lane_cfg->data[i].pos; + break; + default: + break; + } =20 return lane_mask; } @@ -1024,6 +1034,7 @@ static void csiphy_lanes_enable(struct csiphy_device = *csiphy, struct csiphy_config *cfg, s64 link_freq, u8 lane_mask) { + struct device *dev =3D csiphy->camss->dev; struct csiphy_lanes_cfg *c =3D &cfg->csi2->lane_cfg; struct csiphy_device_regs *regs =3D csiphy->regs; u8 settle_cnt; @@ -1032,9 +1043,23 @@ static void csiphy_lanes_enable(struct csiphy_device= *csiphy, =20 settle_cnt =3D csiphy_settle_cnt_calc(link_freq, csiphy->timer_clk_rate); =20 - val =3D CSIPHY_3PH_CMN_CSI_COMMON_CTRL5_CLK_ENABLE; - for (i =3D 0; i < c->num_data; i++) - val |=3D BIT(c->data[i].pos * 2); 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251204-qcom-cphy-v2-3-6b35ef8b071e@ixit.cz> References: <20251204-qcom-cphy-v2-0-6b35ef8b071e@ixit.cz> In-Reply-To: <20251204-qcom-cphy-v2-0-6b35ef8b071e@ixit.cz> To: Robert Foss , Todor Tomov , Bryan O'Donoghue , Vladimir Zapolskiy , Mauro Carvalho Chehab , Luca Weiss , Petr Hodina , Casey Connolly , "Dr. Git" Cc: Joel Selvaraj , Kieran Bingham , Sakari Ailus , linux-media@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, phone-devel@vger.kernel.org, David Heidelberg X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=openpgp-sha256; l=2138; i=david@ixit.cz; h=from:subject:message-id; bh=YHgfSaDVk+a2Lqw1ZwLVeEXKLVx1/k08TjKR7W1kIA8=; b=owEBbQKS/ZANAwAIAWACP8TTSSByAcsmYgBpMbesFQujztf3KdNxWDVcx5BHVMJOVNjPLdozA 0n6IuihTIiJAjMEAAEIAB0WIQTXegnP7twrvVOnBHRgAj/E00kgcgUCaTG3rAAKCRBgAj/E00kg chziEACs9Snvcu/70HqB/xfrUyY3IdKXqz3buIP/QGbF+uU4ohHFMCDw04h2OBL8z6SxKjAevPS U5qRWOxiH3fX8iDOihzM5QRpfu1ZOYgO0TNWvFiJtWYQH5dFZx93eO2fGVHhZ5cFCI0Gtl7yYCW Uli34WXEpuunLt1DfkPZuwuJdogo6/QUI0UpoTfsJsPuIekkRw653h65ZXjeVr5Z9m2KJ6Sb/Ib NlIXMlO6jZqP7vUdN6CFV/wOR2ADlccMDZV38Wst8faQmd+sq982fQUQKq7ld95KkW5D7qIGLjd uEpEs/MXfAXIuFaRLeJwiy1XVj7HidtmM9bto7tZOpHG8v9Kq8kGWp2N4z3Q4aOPWjXIZCdowRS 1bckbeBGFMF9DFlIA+LTRVz09izmyARIJJt1b3JYY4ZHKvd9cpEAXtr7W2Lgtts1+D3I6SaA4nH ptmTmtqkt5h+Q4r9Hm3HHT59xqI2BK/cI7QVby86ppwoVnIaA9ZLGShftOG1ZuWN3lTH88iBq5k tmLexjGt0JH6h/SW9Ua3nJ6h69SOl63rv3yIKzNOULTFm7E9dJ/wYscFou0RBgf880KjMb8oTw9 jQdW3XS78QBqCPhNXWAKu2WLb0CWidyq8PFxLY7Wzbdr0+Fn4cb7zhw5IrmS1ygUkijzWweEIJq Qjlh/RXP6JyQBOw== X-Developer-Key: i=david@ixit.cz; a=openpgp; fpr=D77A09CFEEDC2BBD53A7047460023FC4D3492072 X-Endpoint-Received: by B4 Relay for david@ixit.cz/default with auth_id=355 X-Original-From: David Heidelberg Reply-To: david@ixit.cz From: David Heidelberg Inherit C-PHY information from CSIPHY, so we can configure CSID properly. CSI2_RX_CFG0_PHY_TYPE_SEL must be set to 1, when C-PHY mode is used. Signed-off-by: David Heidelberg --- drivers/media/platform/qcom/camss/camss-csid-gen2.c | 1 + drivers/media/platform/qcom/camss/camss-csid.c | 1 + drivers/media/platform/qcom/camss/camss-csid.h | 1 + 3 files changed, 3 insertions(+) diff --git a/drivers/media/platform/qcom/camss/camss-csid-gen2.c b/drivers/= media/platform/qcom/camss/camss-csid-gen2.c index 2a1746dcc1c5b..033036ae28a4f 100644 --- a/drivers/media/platform/qcom/camss/camss-csid-gen2.c +++ b/drivers/media/platform/qcom/camss/camss-csid-gen2.c @@ -183,6 +183,7 @@ static void __csid_configure_rx(struct csid_device *csi= d, val =3D (lane_cnt - 1) << CSI2_RX_CFG0_NUM_ACTIVE_LANES; val |=3D phy->lane_assign << CSI2_RX_CFG0_DL0_INPUT_SEL; val |=3D phy->csiphy_id << CSI2_RX_CFG0_PHY_NUM_SEL; + val |=3D csid->phy.cphy << CSI2_RX_CFG0_PHY_TYPE_SEL; writel_relaxed(val, csid->base + CSID_CSI2_RX_CFG0); =20 val =3D 1 << CSI2_RX_CFG1_PACKET_ECC_CORRECTION_EN; diff --git a/drivers/media/platform/qcom/camss/camss-csid.c b/drivers/media= /platform/qcom/camss/camss-csid.c index 5284b5857368c..d9026fd829d61 100644 --- a/drivers/media/platform/qcom/camss/camss-csid.c +++ b/drivers/media/platform/qcom/camss/camss-csid.c @@ -1287,6 +1287,7 @@ static int csid_link_setup(struct media_entity *entit= y, csid->phy.csiphy_id =3D csiphy->id; =20 lane_cfg =3D &csiphy->cfg.csi2->lane_cfg; + csid->phy.cphy =3D (lane_cfg->phy_cfg =3D=3D V4L2_MBUS_CSI2_CPHY); csid->phy.lane_cnt =3D lane_cfg->num_data; csid->phy.lane_assign =3D csid_get_lane_assign(lane_cfg); } diff --git a/drivers/media/platform/qcom/camss/camss-csid.h b/drivers/media= /platform/qcom/camss/camss-csid.h index aedc96ed84b2f..a82db31bd2335 100644 --- a/drivers/media/platform/qcom/camss/camss-csid.h +++ b/drivers/media/platform/qcom/camss/camss-csid.h @@ -70,6 +70,7 @@ struct csid_phy_config { u32 lane_assign; u32 en_vc; u8 need_vc_update; + bool cphy; }; =20 struct csid_device; --=20 2.51.0 From nobody Sun Feb 8 07:21:46 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8607C2F7AB0; Thu, 4 Dec 2025 16:32:47 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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a=openpgp; fpr=D77A09CFEEDC2BBD53A7047460023FC4D3492072 X-Endpoint-Received: by B4 Relay for david@ixit.cz/default with auth_id=355 X-Original-From: David Heidelberg Reply-To: david@ixit.cz From: Petr Hodina The lanes must not be initialized before the driver has access to the lane configuration, as it depends on whether D-PHY or C-PHY mode is in use. Move the lane initialization to a later stage where the configuration structures are available. Signed-off-by: Petr Hodina Reviewed-by: Bryan O'Donoghue Signed-off-by: David Heidelberg --- .../platform/qcom/camss/camss-csiphy-3ph-1-0.c | 73 ++++++++++++------= ---- 1 file changed, 40 insertions(+), 33 deletions(-) diff --git a/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c b/dri= vers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c index 9ff79f789fa06..3d30cdce33f96 100644 --- a/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c +++ b/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c @@ -1041,6 +1041,45 @@ static void csiphy_lanes_enable(struct csiphy_device= *csiphy, u8 val; int i; =20 + switch (csiphy->camss->res->version) { + case CAMSS_845: + regs->lane_regs =3D &lane_regs_sdm845[0]; + regs->lane_array_size =3D ARRAY_SIZE(lane_regs_sdm845); + break; + case CAMSS_2290: + regs->lane_regs =3D &lane_regs_qcm2290[0]; + regs->lane_array_size =3D ARRAY_SIZE(lane_regs_qcm2290); + break; + case CAMSS_7280: + case CAMSS_8250: + regs->lane_regs =3D &lane_regs_sm8250[0]; + regs->lane_array_size =3D ARRAY_SIZE(lane_regs_sm8250); + break; + case CAMSS_8280XP: + regs->lane_regs =3D &lane_regs_sc8280xp[0]; + regs->lane_array_size =3D ARRAY_SIZE(lane_regs_sc8280xp); + break; + case CAMSS_X1E80100: + regs->lane_regs =3D &lane_regs_x1e80100[0]; + regs->lane_array_size =3D ARRAY_SIZE(lane_regs_x1e80100); + break; + case CAMSS_8550: + regs->lane_regs =3D &lane_regs_sm8550[0]; + regs->lane_array_size =3D ARRAY_SIZE(lane_regs_sm8550); + break; + case CAMSS_8650: + regs->lane_regs =3D &lane_regs_sm8650[0]; + regs->lane_array_size =3D ARRAY_SIZE(lane_regs_sm8650); + break; + case CAMSS_8300: + case CAMSS_8775P: + regs->lane_regs =3D &lane_regs_sa8775p[0]; + regs->lane_array_size =3D ARRAY_SIZE(lane_regs_sa8775p); + break; + default: + break; + } + settle_cnt =3D csiphy_settle_cnt_calc(link_freq, csiphy->timer_clk_rate); =20 val =3D 0; @@ -1110,47 +1149,15 @@ static int csiphy_init(struct csiphy_device *csiphy) return -ENOMEM; =20 csiphy->regs =3D regs; - regs->offset =3D 0x800; =20 switch (csiphy->camss->res->version) { - case CAMSS_845: - regs->lane_regs =3D &lane_regs_sdm845[0]; - regs->lane_array_size =3D ARRAY_SIZE(lane_regs_sdm845); - break; - case CAMSS_2290: - regs->lane_regs =3D &lane_regs_qcm2290[0]; - regs->lane_array_size =3D ARRAY_SIZE(lane_regs_qcm2290); - break; - case CAMSS_7280: - case CAMSS_8250: - regs->lane_regs =3D &lane_regs_sm8250[0]; - regs->lane_array_size =3D ARRAY_SIZE(lane_regs_sm8250); - break; - case CAMSS_8280XP: - regs->lane_regs =3D &lane_regs_sc8280xp[0]; - regs->lane_array_size =3D ARRAY_SIZE(lane_regs_sc8280xp); - break; case CAMSS_X1E80100: - regs->lane_regs =3D &lane_regs_x1e80100[0]; - regs->lane_array_size =3D ARRAY_SIZE(lane_regs_x1e80100); - regs->offset =3D 0x1000; - break; case CAMSS_8550: - regs->lane_regs =3D &lane_regs_sm8550[0]; - regs->lane_array_size =3D ARRAY_SIZE(lane_regs_sm8550); - regs->offset =3D 0x1000; - break; case CAMSS_8650: - regs->lane_regs =3D &lane_regs_sm8650[0]; - regs->lane_array_size =3D ARRAY_SIZE(lane_regs_sm8650); regs->offset =3D 0x1000; break; - case CAMSS_8300: - case CAMSS_8775P: - regs->lane_regs =3D &lane_regs_sa8775p[0]; - regs->lane_array_size =3D ARRAY_SIZE(lane_regs_sa8775p); - break; default: + regs->offset =3D 0x800; break; } =20 --=20 2.51.0 From nobody Sun Feb 8 07:21:46 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DB7BA2FBDE6; Thu, 4 Dec 2025 16:32:47 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764865968; cv=none; b=nydG/EOrEVOs3P7tBO5Ax/0ORr2RpqqdCoQ+xfv/eoMftI7Q5ykTuh2Xgnf6V11FXJRvzqaMIdMNknriM8C/iTbLCTFoOBWkyW/vAPLGZzZCxB2AVsXxJ/eQVDod8ZDnmoPi0UZ8727T3AtCE8x6fGAjZ6IJlyhFTmaWKux0HYg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; 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Thu, 4 Dec 2025 16:32:47 +0000 (UTC) From: David Heidelberg via B4 Relay Date: Thu, 04 Dec 2025 17:32:39 +0100 Subject: [PATCH WIP v2 5/8] media: qcom: camss: csiphy-3ph: Add Gen2 v1.1 MIPI CSI-2 CPHY init Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251204-qcom-cphy-v2-5-6b35ef8b071e@ixit.cz> References: <20251204-qcom-cphy-v2-0-6b35ef8b071e@ixit.cz> In-Reply-To: <20251204-qcom-cphy-v2-0-6b35ef8b071e@ixit.cz> To: Robert Foss , Todor Tomov , Bryan O'Donoghue , Vladimir Zapolskiy , Mauro Carvalho Chehab , Luca Weiss , Petr Hodina , Casey Connolly , "Dr. Git" Cc: Joel Selvaraj , Kieran Bingham , Sakari Ailus , linux-media@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, phone-devel@vger.kernel.org, David Heidelberg X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=openpgp-sha256; l=4969; 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The PHY can be configured as two phase or three phase in C-PHY or D-PHY mode. This configuration supports three-phase C-PHY mode. Signed-off-by: Casey Connolly Reviewed-by: Vladimir Zapolskiy Reviewed-by: Bryan O'Donoghue Co-developed-by: David Heidelberg Signed-off-by: David Heidelberg --- .../platform/qcom/camss/camss-csiphy-3ph-1-0.c | 74 ++++++++++++++++++= +++- 1 file changed, 72 insertions(+), 2 deletions(-) diff --git a/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c b/dri= vers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c index 3d30cdce33f96..7121aa97a19c4 100644 --- a/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c +++ b/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c @@ -145,6 +145,7 @@ csiphy_lane_regs lane_regs_sa8775p[] =3D { }; =20 /* GEN2 1.0 2PH */ +/* 5 entries: clock + 4 lanes */ static const struct csiphy_lane_regs lane_regs_sdm845[] =3D { {0x0004, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS}, @@ -219,6 +220,69 @@ csiphy_lane_regs lane_regs_sdm845[] =3D { {0x0664, 0x7F, 0x00, CSIPHY_DEFAULT_PARAMS}, }; =20 +/* GEN2 1.0 3PH */ +/* 3 entries: 3 lanes (C-PHY) */ +static const struct +csiphy_lane_regs lane_regs_sdm845_3ph[] =3D { + {0x015C, 0x43, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0168, 0xA0, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x016C, 0x25, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0104, 0x06, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x010C, 0x12, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {0x0108, 0x00, 0x00, CSIPHY_SETTLE_CNT_HIGHER_BYTE}, + {0x0114, 0x20, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0150, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0118, 0x3e, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x011C, 0x41, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0120, 0x41, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0124, 0x7F, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0128, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x012C, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0144, 0x12, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0160, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x01CC, 0x41, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0164, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x01DC, 0x51, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x035C, 0x43, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0368, 0xA0, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x036C, 0x25, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0304, 0x06, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x030C, 0x12, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {0x0308, 0x00, 0x00, CSIPHY_SETTLE_CNT_HIGHER_BYTE}, + {0x0314, 0x20, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0350, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0318, 0x3e, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x031C, 0x41, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0320, 0x41, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0324, 0x7F, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0328, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x032C, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0344, 0x12, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0360, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x03CC, 0x41, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0364, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x03DC, 0x51, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x055C, 0x43, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0568, 0xA0, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x056C, 0x25, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0504, 0x06, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x050C, 0x12, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {0x0508, 0x00, 0x00, CSIPHY_SETTLE_CNT_HIGHER_BYTE}, + {0x0514, 0x20, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0550, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0518, 0x3e, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x051C, 0x41, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0520, 0x41, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0524, 0x7F, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0528, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x052C, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0544, 0x12, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0560, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x05CC, 0x41, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0564, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x05DC, 0x51, 0x00, CSIPHY_DEFAULT_PARAMS}, +}; + /* GEN2 1.1 2PH */ static const struct csiphy_lane_regs lane_regs_sc8280xp[] =3D { @@ -1043,8 +1107,14 @@ static void csiphy_lanes_enable(struct csiphy_device= *csiphy, =20 switch (csiphy->camss->res->version) { case CAMSS_845: - regs->lane_regs =3D &lane_regs_sdm845[0]; - regs->lane_array_size =3D ARRAY_SIZE(lane_regs_sdm845); + if (c->phy_cfg =3D=3D V4L2_MBUS_CSI2_CPHY) { + regs->lane_regs =3D &lane_regs_sdm845_3ph[0]; + regs->lane_array_size =3D ARRAY_SIZE(lane_regs_sdm845_3ph); + + } else { /* V4L2_MBUS_CSI2_DPHY */ + regs->lane_regs =3D &lane_regs_sdm845[0]; + regs->lane_array_size =3D ARRAY_SIZE(lane_regs_sdm845); + } break; case CAMSS_2290: regs->lane_regs =3D &lane_regs_qcm2290[0]; --=20 2.51.0 From nobody Sun Feb 8 07:21:46 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CFBB62FB99B; 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a=openpgp; fpr=D77A09CFEEDC2BBD53A7047460023FC4D3492072 X-Endpoint-Received: by B4 Relay for david@ixit.cz/default with auth_id=355 X-Original-From: David Heidelberg Reply-To: david@ixit.cz From: Luca Weiss Add a PHY configuration sequence for the sm8250 which uses a Qualcomm Gen 2 version 1.2.1 CSI-2 PHY. The PHY can be configured as two phase or three phase in C-PHY or D-PHY mode. This configuration supports three-phase C-PHY mode. Signed-off-by: Luca Weiss Signed-off-by: David Heidelberg Reviewed-by: Konrad Dybcio --- .../platform/qcom/camss/camss-csiphy-3ph-1-0.c | 114 +++++++++++++++++= +++- 1 file changed, 112 insertions(+), 2 deletions(-) diff --git a/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c b/dri= vers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c index 7121aa97a19c4..6d6dd54c5ac9c 100644 --- a/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c +++ b/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c @@ -547,6 +547,111 @@ csiphy_lane_regs lane_regs_qcm2290[] =3D { {0x0664, 0x3f, 0x00, CSIPHY_DEFAULT_PARAMS}, }; =20 +/* GEN2 1.2.1 3PH */ +/* 3 entries: 3 lanes (C-PHY) */ +static const struct +csiphy_lane_regs lane_regs_sm8250_3ph[] =3D { + {0x0990, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0994, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0998, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0990, 0x08, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0994, 0x08, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0998, 0x1a, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x098c, 0xaf, 0x01, CSIPHY_DEFAULT_PARAMS}, + {0x015c, 0x46, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0168, 0xa0, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0104, 0x06, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x010c, 0x12, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {0x0108, 0x00, 0x00, CSIPHY_SETTLE_CNT_HIGHER_BYTE}, + {0x0114, 0x20, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0150, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0188, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x018c, 0x7f, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0190, 0x7f, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0118, 0x3e, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x011c, 0x41, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0120, 0x41, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0124, 0x7f, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0128, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x012c, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0160, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x01cc, 0x41, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x01dc, 0x50, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0984, 0x20, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0988, 0x05, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0980, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x09ac, 0x35, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x09b0, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0800, 0x0e, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0884, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0a90, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0a94, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0a98, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0a90, 0x08, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0a94, 0x08, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0a98, 0x1a, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0a8c, 0xaf, 0x01, CSIPHY_DEFAULT_PARAMS}, + {0x035c, 0x46, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0368, 0xa0, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0304, 0x06, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x030c, 0x12, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {0x0308, 0x00, 0x00, CSIPHY_SETTLE_CNT_HIGHER_BYTE}, + {0x0314, 0x20, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0350, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0388, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x038c, 0x7f, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0390, 0x7f, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0318, 0x3e, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x031c, 0x41, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0320, 0x41, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0324, 0x7f, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0328, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x032c, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0360, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x03cc, 0x41, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x03dc, 0x50, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0a84, 0x20, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0a88, 0x05, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0a80, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0aac, 0x35, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0ab0, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0800, 0x0e, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0884, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0b90, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0b94, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0b98, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0b90, 0x08, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0b94, 0x08, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0b98, 0x1a, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0b8c, 0xaf, 0x01, CSIPHY_DEFAULT_PARAMS}, + {0x055c, 0x46, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0568, 0xa0, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0504, 0x06, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x050c, 0x12, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {0x0508, 0x00, 0x00, CSIPHY_SETTLE_CNT_HIGHER_BYTE}, + {0x0514, 0x20, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0550, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0588, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x058c, 0x7f, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0590, 0x7f, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0518, 0x3e, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x051c, 0x41, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0520, 0x41, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0524, 0x7f, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0528, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x052c, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0560, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x05cc, 0x41, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x05dc, 0x50, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0b84, 0x20, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0b88, 0x05, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0b80, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0bac, 0x35, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0bb0, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0800, 0x0e, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0884, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, +}; + /* GEN2 2.1.2 2PH DPHY mode */ static const struct csiphy_lane_regs lane_regs_sm8550[] =3D { @@ -1122,8 +1227,13 @@ static void csiphy_lanes_enable(struct csiphy_device= *csiphy, break; case CAMSS_7280: case CAMSS_8250: - regs->lane_regs =3D &lane_regs_sm8250[0]; - regs->lane_array_size =3D ARRAY_SIZE(lane_regs_sm8250); + if (c->phy_cfg =3D=3D V4L2_MBUS_CSI2_CPHY) { + regs->lane_regs =3D &lane_regs_sm8250_3ph[0]; + regs->lane_array_size =3D ARRAY_SIZE(lane_regs_sm8250_3ph); + } else { /* V4L2_MBUS_CSI2_DPHY */ + regs->lane_regs =3D &lane_regs_sm8250[0]; + regs->lane_array_size =3D ARRAY_SIZE(lane_regs_sm8250); + } break; case CAMSS_8280XP: regs->lane_regs =3D &lane_regs_sc8280xp[0]; --=20 2.51.0 From nobody Sun Feb 8 07:21:46 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CD19B2FB999; Thu, 4 Dec 2025 16:32:47 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764865968; cv=none; b=SMiTCPIvjInZ8k00K8lomAlX8scHoxEKuekff9bXMTg2cNYypQqqY+g+aNDRoP9xeOerx4FN+1d0tQwI1ngGwuOLed46uRe2pFcU7m0c6E2dXVCVOW8Is6NsXqQP/6KCNdBuXijJ2TEutjTfkkU9cLnczd0cuFUs49O5+muFQyI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764865968; 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b=eKIH+Urn+PUmoBYTkRxl6GqHTwmhNszbDC+ZszQrRDFz+l88yvVg+tSaON2iZVrme fu1HnhkM3WZhpAI94nDJ/WSeptV40GNq+vvKBmDvD6n8aee+FoBt8iec2OFjZvx33M uy3ND1HZ/CNMfIUqdXft3nyMicnyws4IvBRWKwK4ehxcR0SCHyV9yX8oc92jzTZ9gC cfjwL+ug2O9eipqqOysPkjDRNytFkNaAkgiX9n2R/y2s0JcFkTTd8dHMvdx7slFRvx e8KsJHPCD20fpdT2hj/tw/xOyuiO0yt8OdIDbz5wsrbMlUI36GWyq6REW+9hpK8gBR N6YQmDwfLdVpQ== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6C05BD216B2; Thu, 4 Dec 2025 16:32:47 +0000 (UTC) From: David Heidelberg via B4 Relay Date: Thu, 04 Dec 2025 17:32:41 +0100 Subject: [PATCH WIP v2 7/8] media: qcom: camss: csiphy-3ph: C-PHY needs own lane configuration Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251204-qcom-cphy-v2-7-6b35ef8b071e@ixit.cz> References: <20251204-qcom-cphy-v2-0-6b35ef8b071e@ixit.cz> In-Reply-To: <20251204-qcom-cphy-v2-0-6b35ef8b071e@ixit.cz> To: Robert Foss , Todor Tomov , Bryan O'Donoghue , Vladimir Zapolskiy , Mauro Carvalho Chehab , Luca Weiss , Petr Hodina , Casey Connolly , "Dr. Git" Cc: Joel Selvaraj , Kieran Bingham , Sakari Ailus , linux-media@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, phone-devel@vger.kernel.org, David Heidelberg X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=openpgp-sha256; l=3333; i=david@ixit.cz; h=from:subject:message-id; bh=wbIQ6Ecj4wb9GDskxbpQu5QF2zKRS8sSbJFfBe0x2TA=; b=owEBbQKS/ZANAwAIAWACP8TTSSByAcsmYgBpMbetd8v/yjEvP1o+sLSzIMRSIM9tVDlys2CAf 3lSHLzUfEyJAjMEAAEIAB0WIQTXegnP7twrvVOnBHRgAj/E00kgcgUCaTG3rQAKCRBgAj/E00kg cgpgD/sFQSUlh2CaJiY5XFpIXxppoSIWoQgAvO3hMY5mdfUIY55IKkeSZDBqRgxMaFtgrpALS3r qi1iZ6bk7EiheUcWnBkx7KDigWFLg4mbsvp8vCahVfXt7PKy21aLml/JCk6IV0yPX6CTpTY6Ltj M4WbXA3TYQCur68zkVmRbGwei7gtJfZd9K/ZNq7KNDnQSkcZCVJB8OM5HLlEU+YqOx/LTS3FMn3 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Signed-off-by: David Heidelberg --- .../platform/qcom/camss/camss-csiphy-3ph-1-0.c | 48 ++++++++++++++++--= ---- 1 file changed, 36 insertions(+), 12 deletions(-) diff --git a/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c b/dri= vers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c index 6d6dd54c5ac9c..c957f7dbfb243 100644 --- a/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c +++ b/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c @@ -1222,8 +1222,12 @@ static void csiphy_lanes_enable(struct csiphy_device= *csiphy, } break; case CAMSS_2290: - regs->lane_regs =3D &lane_regs_qcm2290[0]; - regs->lane_array_size =3D ARRAY_SIZE(lane_regs_qcm2290); + if (c->phy_cfg =3D=3D V4L2_MBUS_CSI2_CPHY) { + dev_err(dev, "Missing lane_regs definition for %d\n", c->phy_cfg); + } else { /* V4L2_MBUS_CSI2_DPHY */ + regs->lane_regs =3D &lane_regs_qcm2290[0]; + regs->lane_array_size =3D ARRAY_SIZE(lane_regs_qcm2290); + } break; case CAMSS_7280: case CAMSS_8250: @@ -1236,25 +1240,45 @@ static void csiphy_lanes_enable(struct csiphy_devic= e *csiphy, } break; case CAMSS_8280XP: - regs->lane_regs =3D &lane_regs_sc8280xp[0]; - regs->lane_array_size =3D ARRAY_SIZE(lane_regs_sc8280xp); + if (c->phy_cfg =3D=3D V4L2_MBUS_CSI2_CPHY) { + dev_err(dev, "Missing lane_regs definition for %d\n", c->phy_cfg); + } else { /* V4L2_MBUS_CSI2_DPHY */ + regs->lane_regs =3D &lane_regs_sc8280xp[0]; + regs->lane_array_size =3D ARRAY_SIZE(lane_regs_sc8280xp); + } break; case CAMSS_X1E80100: - regs->lane_regs =3D &lane_regs_x1e80100[0]; - regs->lane_array_size =3D ARRAY_SIZE(lane_regs_x1e80100); + if (c->phy_cfg =3D=3D V4L2_MBUS_CSI2_CPHY) { + dev_err(dev, "Missing lane_regs definition for %d\n", c->phy_cfg); + } else { /* V4L2_MBUS_CSI2_DPHY */ + regs->lane_regs =3D &lane_regs_x1e80100[0]; + regs->lane_array_size =3D ARRAY_SIZE(lane_regs_x1e80100); + } break; case CAMSS_8550: - regs->lane_regs =3D &lane_regs_sm8550[0]; - regs->lane_array_size =3D ARRAY_SIZE(lane_regs_sm8550); + if (c->phy_cfg =3D=3D V4L2_MBUS_CSI2_CPHY) { + dev_err(dev, "Missing lane_regs definition for %d\n", c->phy_cfg); + } else { /* V4L2_MBUS_CSI2_DPHY */ + regs->lane_regs =3D &lane_regs_sm8550[0]; + regs->lane_array_size =3D ARRAY_SIZE(lane_regs_sm8550); + } break; case CAMSS_8650: - regs->lane_regs =3D &lane_regs_sm8650[0]; - regs->lane_array_size =3D ARRAY_SIZE(lane_regs_sm8650); + if (c->phy_cfg =3D=3D V4L2_MBUS_CSI2_CPHY) { + dev_err(dev, "Missing lane_regs definition for %d\n", c->phy_cfg); + } else { /* V4L2_MBUS_CSI2_DPHY */ + regs->lane_regs =3D &lane_regs_sm8650[0]; + regs->lane_array_size =3D ARRAY_SIZE(lane_regs_sm8650); + } break; case CAMSS_8300: case CAMSS_8775P: - regs->lane_regs =3D &lane_regs_sa8775p[0]; - regs->lane_array_size =3D ARRAY_SIZE(lane_regs_sa8775p); + if (c->phy_cfg =3D=3D V4L2_MBUS_CSI2_CPHY) { + dev_err(dev, "Missing lane_regs definition for %d\n", c->phy_cfg); + } else { /* V4L2_MBUS_CSI2_DPHY */ + regs->lane_regs =3D &lane_regs_sa8775p[0]; + regs->lane_array_size =3D ARRAY_SIZE(lane_regs_sa8775p); + } break; default: break; --=20 2.51.0 From nobody Sun Feb 8 07:21:46 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D75F92FBDE2; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251204-qcom-cphy-v2-8-6b35ef8b071e@ixit.cz> References: <20251204-qcom-cphy-v2-0-6b35ef8b071e@ixit.cz> In-Reply-To: <20251204-qcom-cphy-v2-0-6b35ef8b071e@ixit.cz> To: Robert Foss , Todor Tomov , Bryan O'Donoghue , Vladimir Zapolskiy , Mauro Carvalho Chehab , Luca Weiss , Petr Hodina , Casey Connolly , "Dr. Git" Cc: Joel Selvaraj , Kieran Bingham , Sakari Ailus , linux-media@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, phone-devel@vger.kernel.org, David Heidelberg X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=openpgp-sha256; l=5230; i=david@ixit.cz; h=from:subject:message-id; bh=b1nclvoHacIkz7OV2Q02X6ymuveqnuBFG4Fw6qspG18=; b=owEBbQKS/ZANAwAIAWACP8TTSSByAcsmYgBpMbetO8v9IP/fCl+iBxVyeBnOtgKMpCe6yBF3S wFhmEpWu5qJAjMEAAEIAB0WIQTXegnP7twrvVOnBHRgAj/E00kgcgUCaTG3rQAKCRBgAj/E00kg cl+9EACfXP/Tbp6aGoowpOVft73F4HARvALH0Cr4oFK3BECz02pgSBIq1Huv9OWvV9xwd8jDNv7 8Ofzv2dqg1MNzlc+B24wGsh9gBCvexmRtC/MARlAcS9gzNd8dDk+S6fOU2gO7IRklOisRIyDGMu hkSIZlJnvKlXW/vi25ndaI5VY9hrg18OXGWDtosCn4pNYfIWaax+iUxndE9GNGrm7gIxQiYdC+R 4Y/vgVX7VtfrR4PF6ZR25DsE381R0/n5fJt2tXTuoBxaBhKufAbbwn7v2SuVVH3VejZheCr8jOh fQbh+YTeDED8Z6jPSNggCmHbYFhWWsDX1n5FgFIhQINEbyJ80k/Ihp5Qg0U5S0efOFxnnsvnsP8 mSkBCrCgGtpKyJ7Vz0fNsY+rCpyGGq8EW9fkQztzQYy7BDosIvuNzrDG1BNFHDEwC0uN12rl3hg Afe9lHXD4qZEPaGBhWrLkHBJx5uIOprgnt75vETEkJGtxGpv+/RPf1RI8Ja/M7w6HfR81MvBW+r SJxOKZAxyPx59BUXNVZ2mKGwiE7+OiQbiFcNmlmnlMOEEgbmVOfgiwdq6PtkO3KukqySNsDWdab 5iLrT5waOzglhzAajmBQolnj4Amwna9w9Bo3gmCKuvM4vvWEKFGzuAyc1GDV3eLSVGqnBH0Pzlb 3s9/bzkunvFTUrw== X-Developer-Key: i=david@ixit.cz; a=openpgp; fpr=D77A09CFEEDC2BBD53A7047460023FC4D3492072 X-Endpoint-Received: by B4 Relay for david@ixit.cz/default with auth_id=355 X-Original-From: David Heidelberg Reply-To: david@ixit.cz From: David Heidelberg Ensure that the link frequency divider correctly accounts for C-PHY operation. The divider differs between D-PHY and C-PHY, as described in the MIPI CSI-2 specification. For more details, see: https://docs.kernel.org/driver-api/media/tx-rx.html#pixel-rate Suggested-by: Sakari Ailus Signed-off-by: David Heidelberg --- drivers/media/platform/qcom/camss/camss-csid.c | 2 +- drivers/media/platform/qcom/camss/camss-csiphy.c | 6 ++++-- drivers/media/platform/qcom/camss/camss.c | 16 +++++++++++++--- drivers/media/platform/qcom/camss/camss.h | 2 +- 4 files changed, 19 insertions(+), 7 deletions(-) diff --git a/drivers/media/platform/qcom/camss/camss-csid.c b/drivers/media= /platform/qcom/camss/camss-csid.c index d9026fd829d61..437f51dc86f9f 100644 --- a/drivers/media/platform/qcom/camss/camss-csid.c +++ b/drivers/media/platform/qcom/camss/camss-csid.c @@ -545,7 +545,7 @@ static int csid_set_clock_rates(struct csid_device *csi= d) fmt =3D csid_get_fmt_entry(csid->res->formats->formats, csid->res->format= s->nformats, csid->fmt[MSM_CSIPHY_PAD_SINK].code); link_freq =3D camss_get_link_freq(&csid->subdev.entity, fmt->bpp, - csid->phy.lane_cnt); + csid->phy.lane_cnt, csid->phy.cphy); if (link_freq < 0) link_freq =3D 0; =20 diff --git a/drivers/media/platform/qcom/camss/camss-csiphy.c b/drivers/med= ia/platform/qcom/camss/camss-csiphy.c index a734fb7dde0a4..bac3a9fa3be50 100644 --- a/drivers/media/platform/qcom/camss/camss-csiphy.c +++ b/drivers/media/platform/qcom/camss/camss-csiphy.c @@ -144,8 +144,9 @@ static int csiphy_set_clock_rates(struct csiphy_device = *csiphy) u8 bpp =3D csiphy_get_bpp(csiphy->res->formats->formats, csiphy->res->for= mats->nformats, csiphy->fmt[MSM_CSIPHY_PAD_SINK].code); u8 num_lanes =3D csiphy->cfg.csi2->lane_cfg.num_data; + bool cphy =3D csiphy->cfg.csi2->lane_cfg.phy_cfg =3D=3D V4L2_MBUS_CSI2_CP= HY; =20 - link_freq =3D camss_get_link_freq(&csiphy->subdev.entity, bpp, num_lanes); + link_freq =3D camss_get_link_freq(&csiphy->subdev.entity, bpp, num_lanes,= cphy); if (link_freq < 0) link_freq =3D 0; =20 @@ -270,9 +271,10 @@ static int csiphy_stream_on(struct csiphy_device *csip= hy) u8 bpp =3D csiphy_get_bpp(csiphy->res->formats->formats, csiphy->res->for= mats->nformats, csiphy->fmt[MSM_CSIPHY_PAD_SINK].code); u8 num_lanes =3D csiphy->cfg.csi2->lane_cfg.num_data; + bool cphy =3D csiphy->cfg.csi2->lane_cfg.phy_cfg =3D=3D V4L2_MBUS_CSI2_CP= HY; u8 val; =20 - link_freq =3D camss_get_link_freq(&csiphy->subdev.entity, bpp, num_lanes); + link_freq =3D camss_get_link_freq(&csiphy->subdev.entity, bpp, num_lanes,= cphy); =20 if (link_freq < 0) { dev_err(csiphy->camss->dev, diff --git a/drivers/media/platform/qcom/camss/camss.c b/drivers/media/plat= form/qcom/camss/camss.c index 414646760ae6b..6333f5dd73b53 100644 --- a/drivers/media/platform/qcom/camss/camss.c +++ b/drivers/media/platform/qcom/camss/camss.c @@ -32,6 +32,14 @@ #define CAMSS_CLOCK_MARGIN_NUMERATOR 105 #define CAMSS_CLOCK_MARGIN_DENOMINATOR 100 =20 +/* + * C-PHY encodes data by 16/7 ~ 2.28 bits/symbol + * D-PHY doesn't encode data, thus 16/16 =3D 1 b/s + */ +#define CAMSS_COMMON_PHY_DIVIDENT 16 +#define CAMSS_CPHY_DIVISOR 7 +#define CAMSS_DPHY_DIVISOR 16 + static const struct parent_dev_ops vfe_parent_dev_ops; =20 static const struct camss_subdev_resources csiphy_res_8x16[] =3D { @@ -3912,20 +3920,22 @@ struct media_pad *camss_find_sensor_pad(struct medi= a_entity *entity) * camss_get_link_freq - Get link frequency from sensor * @entity: Media entity in the current pipeline * @bpp: Number of bits per pixel for the current format - * @lanes: Number of lanes in the link to the sensor + * @nr_of_lanes: Number of lanes in the link to the sensor * * Return link frequency on success or a negative error code otherwise */ s64 camss_get_link_freq(struct media_entity *entity, unsigned int bpp, - unsigned int lanes) + unsigned int nr_of_lanes, bool cphy) { struct media_pad *sensor_pad; + unsigned int div =3D nr_of_lanes * 2 * (cphy ? CAMSS_CPHY_DIVISOR : + CAMSS_DPHY_DIVISOR); =20 sensor_pad =3D camss_find_sensor_pad(entity); if (!sensor_pad) return -ENODEV; =20 - return v4l2_get_link_freq(sensor_pad, bpp, 2 * lanes); + return v4l2_get_link_freq(sensor_pad, CAMSS_COMMON_PHY_DIVIDENT * bpp, di= v); } =20 /* diff --git a/drivers/media/platform/qcom/camss/camss.h b/drivers/media/plat= form/qcom/camss/camss.h index 9d9a62640e25d..0ab908b0c037f 100644 --- a/drivers/media/platform/qcom/camss/camss.h +++ b/drivers/media/platform/qcom/camss/camss.h @@ -162,7 +162,7 @@ int camss_enable_clocks(int nclocks, struct camss_clock= *clock, void camss_disable_clocks(int nclocks, struct camss_clock *clock); struct media_pad *camss_find_sensor_pad(struct media_entity *entity); s64 camss_get_link_freq(struct media_entity *entity, unsigned int bpp, - unsigned int lanes); + unsigned int lanes, bool cphy); int camss_get_pixel_clock(struct media_entity *entity, u64 *pixel_clock); int camss_pm_domain_on(struct camss *camss, int id); void camss_pm_domain_off(struct camss *camss, int id); --=20 2.51.0