From nobody Fri Dec 19 21:12:55 2025 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 521D42EC553 for ; Wed, 3 Dec 2025 23:55:22 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.251.105.195 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764806125; cv=none; b=X8RsCieBYhx4ZKCdTfPMr3L6xFfC58IF838uYML83al7bqxYdzetLKs9124GONsSaDcfOPoQ1lu58p3SjMXGHV8+adKTFPctjiESA4cP/hC0TU17GGjZRwLs5pmCy3a8w1GCv5V5sPFpAf3VNvMWxOPbQ+fcZ0v/bJK7pPZaQNA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764806125; c=relaxed/simple; bh=lfwx5dWdmB91fro96PRWljjZswN6jZAfvgtTYs9ZWBk=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=LEXUJqqk4Jk+ez8Bw8TKvKMQNK8WMGktaYy0w4N5wYrFo4ZY0/jUfvK9xL2wlQPdZFnQdp7EPQeaqg71Vc8dn9H7pPouHTipBkKiTWGfK6X7XlXevB7XCOd2GVlnQc1okal9mZLi2vNqkd3qRWm0WeseKo7u2e1auFXPy1/VBQo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com; spf=pass smtp.mailfrom=collabora.com; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b=A3tFM4rr; arc=none smtp.client-ip=148.251.105.195 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=collabora.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b="A3tFM4rr" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1764806120; bh=lfwx5dWdmB91fro96PRWljjZswN6jZAfvgtTYs9ZWBk=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=A3tFM4rrT//Wbk5ZjB+zLf4/OdSYIzUFqkDYRA0/3ByNaRCPhUspf/vuamrTWI8eh 9KQtJ3RxIgm2xDYP+XPVttX3Y0n9ytD6LbZ5iViumpmCpM/AGqJi+YsXqu0Znr0Iji wyAJ6FIRteY69v51X/zYrzz/xBDWGZQR/RGrUTTtxLc6KbIfX28BVfZEQoO1XYIGYi f+he9MKtsq7w3ybsdyWOnS/UfV04PPMzRIrXvoQDDlkJgv0lYtm8CBRHLtYfOFC9S0 jM2Rb1nst0lTBrEztLmu5kHAEroQPnw57W1C9jBYsF5M2iRWre2RWCkSAgc7qbK75q 7tABys8PcClDA== Received: from localhost (unknown [82.79.138.145]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange ECDHE (prime256v1) server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: cristicc) by bali.collaboradmins.com (Postfix) with ESMTPSA id 5AA8D17E0CF5; Thu, 4 Dec 2025 00:55:20 +0100 (CET) From: Cristian Ciocaltea Date: Thu, 04 Dec 2025 01:54:09 +0200 Subject: [PATCH 1/2] phy: rockchip: samsung-hdptx: Pre-compute HDMI PLL config for 461.10125 MHz output Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251204-phy-hdptx-pll-fix-v1-1-d94fd6cfd59b@collabora.com> References: <20251204-phy-hdptx-pll-fix-v1-0-d94fd6cfd59b@collabora.com> In-Reply-To: <20251204-phy-hdptx-pll-fix-v1-0-d94fd6cfd59b@collabora.com> To: Vinod Koul , Neil Armstrong , Heiko Stuebner , Dmitry Baryshkov Cc: kernel@collabora.com, linux-phy@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org X-Mailer: b4 0.14.3 Attempting to make use of the 1080p@120Hz HDMI mode with 10 bpc RGB on my Acer XV275K P3 monitor results in a blank image. A similar behavior has been reported on Philips 279M1RV. The faulty modeline is created by drm_gtf_mode_complex() based on the following EDID entry from the Standard Timings block: GTF: 1920x1080 119.999987 Hz 16:9 138.840 kHz 368.759000 MHz It's worth noting the computed pixel clock ends up being slightly higher at 368.881000 MHz. Nevertheless, this seems to work consistently fine with 8 bpc RGB. After switching to 10 bpc, the TMDS character rate expected for the mode increases to 461.101250 MHz, as per drm_hdmi_compute_mode_clock(). Since there is no entry for this rate in the ropll_tmds_cfg table, the necessary HDMI PLL configuration parameters are calculated dynamically by rk_hdptx_phy_clk_pll_calc(). However, the resulting output rate is not quite a perfect match, i.e. 461.100000 MHz, that proved to be the actual root cause of the problem. Add a new entry to the TMDS configuration table and provide the necessary frequency division coefficients for the PHY PLL to generate the expected 461.101250 MHz output. Fixes: 9d0ec51d7c22 ("phy: rockchip: samsung-hdptx: Add high color depth ma= nagement") Signed-off-by: Cristian Ciocaltea Tested-by: Derek Foreman --- drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c b/drivers/ph= y/rockchip/phy-rockchip-samsung-hdptx.c index 29de2f7bdae8..cafa618d70fd 100644 --- a/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c +++ b/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c @@ -414,6 +414,8 @@ struct rk_hdptx_phy { static const struct ropll_config ropll_tmds_cfg[] =3D { { 594000000ULL, 124, 124, 1, 1, 0, 1, 1, 1, 1, 1, 1, 1, 62, 1, 16, 5, 0, 1, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, }, + { 461101250ULL, 97, 97, 1, 1, 0, 1, 1, 1, 1, 1, 1, 1, 71, 1, 53, 2, 6, + 35, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, }, { 371250000ULL, 155, 155, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 62, 1, 16, 5, 0, 1, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, }, { 297000000ULL, 124, 124, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 62, 1, 16, 5, 0, --=20 2.51.2