From nobody Fri Dec 19 21:14:38 2025 Received: from mail-qk1-f179.google.com (mail-qk1-f179.google.com [209.85.222.179]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 37C3928313D for ; Wed, 3 Dec 2025 12:12:21 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.222.179 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764763942; cv=none; b=l/m6yMTgRCUBhxSSMjvnIhtpP3SHTL89b0Ec74pxEhM0KvHgnx9+2KtlKZObxY9x7++I0/TNUydJBbSaSrkb8P27uucHYuJcbFbxoR3NlePcyP0jz3zA8R97Fq0emLprt+cpb2w1WMx2ZWxUD2GdiVUgGvZTKFVB0jxLCFPlEYI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764763942; c=relaxed/simple; bh=n22d6mzCMmzziGtUvDvzO8PMA1/MB2OVxO8lfoFv740=; h=From:To:Cc:Subject:Date:Message-ID:MIME-Version; b=ZzyDqFQ1aDNdOs4s3OhkmwN6xeMcnZ7g7y8sXqhJHQw1lZMQHM0k+K0JyojPJZvkn4zO33/BywJ/O6VKLiF36ngaxcC4TfvqMcVTnWgih35T+pd6ly2eMEkdJgaN2OCzx1TLdOHhRxoKY+PJNmGZ9sVraOVce2+Nsh+Ho2cvSKQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=sartura.hr; spf=pass smtp.mailfrom=sartura.hr; dkim=pass (2048-bit key) header.d=sartura.hr header.i=@sartura.hr header.b=d4wchvhp; arc=none smtp.client-ip=209.85.222.179 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=sartura.hr Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=sartura.hr Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=sartura.hr header.i=@sartura.hr header.b="d4wchvhp" Received: by mail-qk1-f179.google.com with SMTP id af79cd13be357-8b2d7c38352so90416285a.0 for ; Wed, 03 Dec 2025 04:12:21 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sartura.hr; s=sartura; t=1764763940; x=1765368740; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:from:to:cc:subject:date:message-id:reply-to; bh=jmZ1Nnr8hYEbUibLvWDZg2doGxe3gLL84xuGJmKYhWk=; b=d4wchvhp/fdVV+86dGpn9e3BhEf1nc/r/WIAQfwV1s+gtwvlkGktoLOK4HDBPGRIbf 74d1PGTEHFNHgVfSuqgm7jWwauiSJMwjmOfGoKH0jwLKeK2hbkvxGGdV0j5UhuogI/NM qgScIyfrBOQXA5SkuOPwg993LjJDnV3Um6N0HZbZVFImfFWoZbAm9Dldq/aFzf3xMIFz GtgEhd/DkaosYUOy+DqTxlUPBuVpCCJJRsq+u4G1f41AFK59QcL70t5K58agTQp4UyUR VfoMjY+FOs0nY1do1MY7V+XQp1caOlJDyWE/matlOvHaZh7eL0bzqrRMY3fEhqmk6M4v tbAA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1764763940; x=1765368740; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:x-gm-gg:x-gm-message-state:from:to:cc:subject:date :message-id:reply-to; bh=jmZ1Nnr8hYEbUibLvWDZg2doGxe3gLL84xuGJmKYhWk=; b=MikuYzF4ZIc/8ylL/t84nMeDGccWAq7LBR52fxArttDltb75ZoHCRzk2qSF1dOXlog bg2X6heYRpOB3gU2Q1Uas9YvFptE5jSYA45CH6ITVXKQOFMw/98maISaRJwhz2NW1C6L 8f0+bZE14jilUXSH0opKGmz+0yNZUWm6L2w7Jjttc/kxICC3tfyZAW6NqYXcouFByhDM o1qNgO510aZ2WpAeSbqieX9TuT/eIp7431mqN3UbsBL6IsDwtiIWgpJFdVzNgdTOUFyw R39rOuOdxdsrZl96XyX0o8SHQWdN2C8ywj2u90CVaJMvMCw5ihFTFePgml/JMUcALO9C apGA== X-Forwarded-Encrypted: i=1; AJvYcCX/NrS3cRSpI/MRrBp4doAGA+PqndW0GPuJ8MI95NR9fgGe6wHSJFzm8BVb16j2mT1Pu2umr40mElI4lUI=@vger.kernel.org X-Gm-Message-State: AOJu0YykeeIHlDWh4cuu3Z/KWByoFSNXpy051gHZsy+phWTfJpJb9zDC R2WEXa6p3B+pl2GsHJF/+fZ1uFYXhoGrFbpk+VrnI8DkSnqh9Ps7r3jvn+DXw49AKXqAh/hSkyP 2JyyBHzU= X-Gm-Gg: ASbGncse/N9WsjtFPg8RRB+zFJaKZgWlAwHm17rXruSpPAdttZk/1IHGYdWQ/GtPGT4 8kYukaLNG77Jt1HQxddT2BfBPdOaizgCP/Y0NYGgX+3jid76T0Gdh4J0bK9GRjPHB0GvhY3um6k ixDXie1aMAC0I0Ng0tSgqzjNg2DNNFrBnbDnghEI/lpYl7lxPGDn/c4QKAcysTKXPDDx3W3wlDM Msn0+qJx4I2xRrxJ16IJE7fNHWt8smuxNWUwiX+mJcUKrT2AxsEbAnX0fNXSFzkOpgM0yNVgi4R hryhfZY26LxNX12PZo+Hh8tjEImI9H7q4AA6FKKI1W/sLGKcOCVs7bO5xXsS8XjaiBIRQHOrxB9 i3ofkcaXMFkyfmf9Yc+3dj3brCmYliXEYRTEU1BJsN1/1sUasPk3n3cW5KTyvncOv5US9zNYqYw 3eRXsuyBQWAw72PXEAyAIFLYhckZ+EErrmMQ/EafZsxaZB X-Google-Smtp-Source: AGHT+IG6GEiIMrlIJ16aAfiqLcEureDC4oQURs3Fa/1GaHuA+RFp6sYuomKRuRIY11PjdxnazNDFvA== X-Received: by 2002:a05:620a:1aa3:b0:8b2:faa3:5639 with SMTP id af79cd13be357-8b5df10bb7bmr297923085a.11.1764763940117; Wed, 03 Dec 2025 04:12:20 -0800 (PST) Received: from fedora (cpezg-94-253-146-247-cbl.xnet.hr. [94.253.146.247]) by smtp.googlemail.com with ESMTPSA id af79cd13be357-8b52a1dd353sm1294658485a.49.2025.12.03.04.12.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 03 Dec 2025 04:12:19 -0800 (PST) From: Robert Marko To: ludovic.desroches@microchip.com, vkoul@kernel.org, linux-arm-kernel@lists.infradead.org, dmaengine@vger.kernel.org, linux-kernel@vger.kernel.org, daniel.machon@microchip.com Cc: luka.perkov@sartura.hr, Tony Han , Robert Marko Subject: [PATCH RESEND] dmaengine: at_xdmac: get the number of DMA channels from device tree Date: Wed, 3 Dec 2025 13:11:43 +0100 Message-ID: <20251203121208.1269487-1-robert.marko@sartura.hr> X-Mailer: git-send-email 2.52.0 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Tony Han In case of kernel runs in non-secure mode, the number of DMA channels can be got from device tree since the value read from GTYPE register is "0" as it's always secured. As the number of channels can never be negative, update them to the type "unsigned". This is required for LAN969x. Signed-off-by: Tony Han Signed-off-by: Robert Marko --- drivers/dma/at_xdmac.c | 26 +++++++++++++++++++++++--- 1 file changed, 23 insertions(+), 3 deletions(-) diff --git a/drivers/dma/at_xdmac.c b/drivers/dma/at_xdmac.c index 3fbc74710a13..acabf82e293c 100644 --- a/drivers/dma/at_xdmac.c +++ b/drivers/dma/at_xdmac.c @@ -2257,12 +2257,29 @@ static int __maybe_unused atmel_xdmac_runtime_resum= e(struct device *dev) return clk_enable(atxdmac->clk); } =20 +static inline int at_xdmac_get_channel_number(struct platform_device *pdev, + u32 reg, u32 *pchannels) +{ + int ret; + + if (reg) { + *pchannels =3D AT_XDMAC_NB_CH(reg); + return 0; + } + + ret =3D of_property_read_u32(pdev->dev.of_node, "dma-channels", pchannels= ); + if (ret) + dev_err(&pdev->dev, "can't get number of channels\n"); + + return ret; +} + static int at_xdmac_probe(struct platform_device *pdev) { struct at_xdmac *atxdmac; - int irq, nr_channels, i, ret; + int irq, ret; void __iomem *base; - u32 reg; + u32 nr_channels, i, reg; =20 irq =3D platform_get_irq(pdev, 0); if (irq < 0) @@ -2278,7 +2295,10 @@ static int at_xdmac_probe(struct platform_device *pd= ev) * of channels to do the allocation. */ reg =3D readl_relaxed(base + AT_XDMAC_GTYPE); - nr_channels =3D AT_XDMAC_NB_CH(reg); + ret =3D at_xdmac_get_channel_number(pdev, reg, &nr_channels); + if (ret) + return ret; + if (nr_channels > AT_XDMAC_MAX_CHAN) { dev_err(&pdev->dev, "invalid number of channels (%u)\n", nr_channels); --=20 2.52.0