From nobody Fri Dec 19 20:55:33 2025 Received: from m16.mail.163.com (m16.mail.163.com [220.197.31.5]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A431C2DCC1C; Wed, 3 Dec 2025 09:27:43 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=220.197.31.5 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764754069; cv=none; b=OjWhM1j6kd3+heozLpbKyIGCEUPM1Kx7ne0QdlHVrQ29mxpd4IX3Ece28m0hcLeQeastJ1J9bW7MGjEu9ZDo8vBe9EI/OSSqj+uz6yOWxJeH8pewn3xildgKGrQJaRUjYmkbiijnb7UhHnMVo90VBzAjMHkb76/Cbr+lRu3VqJI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764754069; c=relaxed/simple; bh=tj3Yn0tAP4tpnrKKj9WsL+Q0oiPRDvD5GkFON7KfMT0=; h=From:To:Cc:Subject:Date:Message-ID:MIME-Version; b=B6zUNiB3dZ6u1/5aHG51vAtQrbjq7xSiTx6bgursodyb9GyvXkuw5vcVhGHy3bYjX2NshC090k6Uk7yYtTxhaxQvn+De9DCz8GZqVGNOTT3cLVyuqe2GM4E0gkBgG3Iehj3GHXFQrUkujKI/LIrWpCXfqUL07YmLjk/Ulwk0QiI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=163.com; spf=pass smtp.mailfrom=163.com; dkim=pass (1024-bit key) header.d=163.com header.i=@163.com header.b=A4BHA582; arc=none smtp.client-ip=220.197.31.5 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=163.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=163.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=163.com header.i=@163.com header.b="A4BHA582" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=163.com; s=s110527; h=From:To:Subject:Date:Message-ID:MIME-Version; bh=Tc UFjhr66+t/RO+Alvz1oilaCXP3lhuhWWr/CDtGak4=; b=A4BHA582swzH02/eCK G/3cw1TyUJFO76PSe5pgGeTHMmcGDPASmR+/7MRgo5jqLv2+QvwSFeXYys4Ri8JN u7Vvqv/lELLjqKn3y3FI8IVjnJf6sIpM2kmlGGHzYuis+dCOfHFwTZ5YHsdzewrB 9uCQh850Yff8yUnvIzKicoX7k= Received: from duge-virtual-machine (unknown []) by gzga-smtp-mtada-g0-2 (Coremail) with SMTP id _____wB3hL9WAjBp0iOFDg--.607S2; Wed, 03 Dec 2025 17:26:48 +0800 (CST) From: q691800735@163.com To: linux-riscv@lists.infradead.org, devicetree@vger.kernel.org Cc: conor@kernel.org, robh@kernel.org, krzk+dt@kernel.org, pjw@kernel.org, palmer@dabbelt.com, aou@eecs.berkeley.edu, alex@ghiti.fr, linux-kernel@vger.kernel.org, jybruceupup Subject: [PATCH] riscv: dts: canaan: Add K230 clock provider DTSI Date: Wed, 3 Dec 2025 17:26:43 +0800 Message-ID: <20251203092643.219600-1-q691800735@163.com> X-Mailer: git-send-email 2.52.0 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: _____wB3hL9WAjBp0iOFDg--.607S2 X-Coremail-Antispam: 1Uf129KBjvAXoWfKF48uFyfAFy7CryUtr48Crg_yoWxKF15to Z0yFy3Ww18Ar9rKa9Fyw15KasxGFy3KrW3JFWYqa13Kr43XrW8GryUKa9xJF9Ykw48A3yD J3sa9w15Kr13Grnxn29KB7ZKAUJUUUU8529EdanIXcx71UUUUU7v73VFW2AGmfu7bjvjm3 AaLaJ3UbIYCTnIWIevJa73UjIFyTuYvjTRNmiEUUUUU X-CM-SenderInfo: jtwzimyqqxjki6rwjhhfrp/xtbBcwEZMGkv-c9t7wAAst Content-Type: text/plain; charset="utf-8" From: jybruceupup Add clock provider DTSI for Kendryte K230 SoC, required for subsystem clock management and boot. Signed-off-by: jybruceupup --- .../boot/dts/canaan/k230_clock_provider.dtsi | 2724 +++++++++++++++++ 1 file changed, 2724 insertions(+) create mode 100644 arch/riscv/boot/dts/canaan/k230_clock_provider.dtsi diff --git a/arch/riscv/boot/dts/canaan/k230_clock_provider.dtsi b/arch/ris= cv/boot/dts/canaan/k230_clock_provider.dtsi new file mode 100644 index 000000000..9d193ca22 --- /dev/null +++ b/arch/riscv/boot/dts/canaan/k230_clock_provider.dtsi @@ -0,0 +1,2724 @@ +// SPDX-License-Identifier: GPL-2.0 OR MIT +/* + * Copyright (c) 2023, Canaan Bright Sight Co., Ltd + * Copyright (c) 2025 jybruceupup + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +&sysctl_boot { +/* osc24m clock */ + osc24m: osc24m { + #clock-cells =3D <0>; /* only one clock output */ + compatible =3D "fixed-clock";/* It's clock source, no parent */ + clock-frequency =3D <24000000>; /* clock freqence is 24MHz */ + clock-accuracy =3D <0>; /* software assume clock no jitter/wander.*/ + status =3D "okay"; + read-only =3D <0>; + }; + + /* pll clock */ + pll0: pll0 { + #clock-cells =3D <0>; /* only one output */ + compatible =3D "canaan,k230-pll"; + /* pll0/1/2/3 match same clk driver, comptible is k230-pll(not k230-pll0= ,1,2,3)*/ + clocks =3D <&osc24m>; /* clk parent is osc24m */ + status =3D "okay"; + read-only =3D <0>; + + /* PLL0_CFG0 */ + clk-divide-reg-offset =3D <0x0>;/* pll divider register offset */ + clk-divide-out-reg-value-shift =3D <24>; /* start bit is 24 */ + clk-divide-out-reg-value-mask =3D <0xF>; + /* bitmask, 0xf means b'1111(4bits), bit24(start bit) to bit27 */ + clk-divide-ref-reg-value-shift =3D <16>; + clk-divide-ref-reg-value-mask =3D <0x3F>; + clk-divide-fb-reg-value-shift =3D <0>; + clk-divide-fb-reg-value-mask =3D <0x1FFF>; + + /* PLL0_CFG1: bypass */ + clk-divide-bypass-reg-offset =3D <0x4>; + clk-divide-bypass-reg-enable-bit =3D <19>; + + /* PLL0_CTL: gate */ + clk-gate-reg-offset =3D <0x8>; + clk-gate-reg-enable-bit =3D <2>; + clk-gate-reg-write-enable-bit =3D <18>; + + /* PLL0_STAT: pll0 lock status */ + clk-lock-reg-offset =3D <0xC>; + clk-lock-reg-status_bit =3D <0>; + }; + + pll0_div2: pll0_div2 { + #clock-cells =3D <0>; + compatible =3D "fixed-factor-clock"; + clocks =3D <&pll0>; + clock-div =3D <2>; + clock-mult =3D <1>; + status =3D "okay"; + read-only =3D <0>; + }; + + pll0_div3: pll0_div3 { + #clock-cells =3D <0>; + compatible =3D "fixed-factor-clock"; + clocks =3D <&pll0>; + clock-div =3D <3>; + clock-mult =3D <1>; + status =3D "okay"; + read-only =3D <0>; + }; + + pll0_div4: pll0_div4 { + #clock-cells =3D <0>; + compatible =3D "fixed-factor-clock"; + clocks =3D <&pll0>; + clock-div =3D <4>; + clock-mult =3D <1>; + status =3D "okay"; + read-only =3D <0>; + }; + + pll1: pll1 { + #clock-cells =3D <0>; /* only one output */ + compatible =3D "canaan,k230-pll"; + /* pll0/1/2/3 match same clk driver, so comptible is k230-pll(not k230-pl= l0,1,2,3)*/ + clocks =3D <&osc24m>; /* clk parent is osc24m */ + status =3D "okay"; + read-only =3D <0>; + + /* PLL1_CFG0 */ + clk-divide-reg-offset =3D <0x10>; + clk-divide-out-reg-value-shift =3D <24>; + clk-divide-out-reg-value-mask =3D <0xF>; + clk-divide-ref-reg-value-shift =3D <16>; + clk-divide-ref-reg-value-mask =3D <0x3F>; + clk-divide-fb-reg-value-shift =3D <0>; + clk-divide-fb-reg-value-mask =3D <0x1FFF>; + + /* PLL1_CFG1: bypass */ + clk-divide-bypass-reg-offset =3D <0x14>; + clk-divide-bypass-reg-enable-bit =3D <19>; + + /* PLL1_CTL: gate */ + clk-gate-reg-offset =3D <0x18>; + clk-gate-reg-enable-bit =3D <2>; + clk-gate-reg-write-enable-bit =3D <18>; + + /* PLL1_STAT: pll1 lock status */ + clk-lock-reg-offset =3D <0x1C>; + clk-lock-reg-status_bit =3D <0>; + }; + + pll1_div2: pll1_div2 { + #clock-cells =3D <0>; + compatible =3D "fixed-factor-clock"; + clocks =3D <&pll1>; + clock-div =3D <2>; + clock-mult =3D <1>; + status =3D "okay"; + read-only =3D <0>; + }; + + pll1_div3: pll1_div3 { + #clock-cells =3D <0>; + compatible =3D "fixed-factor-clock"; + clocks =3D <&pll1>; + clock-div =3D <3>; + clock-mult =3D <1>; + status =3D "okay"; + read-only =3D <0>; + }; + + pll1_div4: pll1_div4 { + #clock-cells =3D <0>; + compatible =3D "fixed-factor-clock"; + clocks =3D <&pll1>; + clock-div =3D <4>; + clock-mult =3D <1>; + status =3D "okay"; + read-only =3D <0>; + }; + + pll2: pll2 { + #clock-cells =3D <0>; /* only one output */ + compatible =3D "canaan,k230-pll"; + /* pll0/1/2/3 match same clk driver, so comptible is k230-pll(not k230-pl= l0,1,2,3)*/ + clocks =3D <&osc24m>; /* clk parent is osc24m */ + status =3D "okay"; + read-only =3D <0>; + + /* PLL2_CFG0 */ + clk-divide-reg-offset =3D <0x20>; + clk-divide-out-reg-value-shift =3D <24>; + clk-divide-out-reg-value-mask =3D <0xF>; + clk-divide-ref-reg-value-shift =3D <16>; + clk-divide-ref-reg-value-mask =3D <0x3F>; + clk-divide-fb-reg-value-shift =3D <0>; + clk-divide-fb-reg-value-mask =3D <0x1FFF>; + + /* PLL2_CFG1: bypass */ + clk-divide-bypass-reg-offset =3D <0x24>; + clk-divide-bypass-reg-enable-bit =3D <19>; + + /* PLL2_CTL: gate */ + clk-gate-reg-offset =3D <0x28>; + clk-gate-reg-enable-bit =3D <2>; + clk-gate-reg-write-enable-bit =3D <18>; + + /* PLL_STAT: pll2 lock status */ + clk-lock-reg-offset =3D <0x2C>; + clk-lock-reg-status_bit =3D <0>; + }; + + pll2_div2: pll2_div2 { + #clock-cells =3D <0>; + compatible =3D "fixed-factor-clock"; + clocks =3D <&pll2>; + clock-div =3D <2>; + clock-mult =3D <1>; + status =3D "okay"; + read-only =3D <0>; + }; + + pll2_div3: pll2_div3 { + #clock-cells =3D <0>; + compatible =3D "fixed-factor-clock"; + clocks =3D <&pll2>; + clock-div =3D <3>; + clock-mult =3D <1>; + status =3D "okay"; + read-only =3D <0>; + }; + + pll2_div4: pll2_div4 { + #clock-cells =3D <0>; + compatible =3D "fixed-factor-clock"; + clocks =3D <&pll2>; + clock-div =3D <4>; + clock-mult =3D <1>; + status =3D "okay"; + read-only =3D <0>; + }; + + pll3: pll3 { + #clock-cells =3D <0>; /* only one output */ + compatible =3D "canaan,k230-pll"; + /* pll0/1/2/3 match same clk driver, so comptible is k230-pll(not k230-pl= l0,1,2,3)*/ + clocks =3D <&osc24m>; /* clk parent is osc24m */ + status =3D "okay"; + read-only =3D <0>; + + /* PLL3_CFG0 */ + clk-divide-reg-offset =3D <0x30>; + clk-divide-out-reg-value-shift =3D <24>; + clk-divide-out-reg-value-mask =3D <0xF>; + clk-divide-ref-reg-value-shift =3D <16>; + clk-divide-ref-reg-value-mask =3D <0x3F>; + clk-divide-fb-reg-value-shift =3D <0>; + clk-divide-fb-reg-value-mask =3D <0x1FFF>; + + /* PLL3_CFG1: bypass */ + clk-divide-bypass-reg-offset =3D <0x34>; + clk-divide-bypass-reg-enable-bit =3D <19>; + + /* PLL3_CTL: gate */ + clk-gate-reg-offset =3D <0x38>; + clk-gate-reg-enable-bit =3D <2>; + clk-gate-reg-write-enable-bit =3D <18>; + + /* PLL3_STAT: pll3 lock status */ + clk-lock-reg-offset =3D <0x3C>; + clk-lock-reg-status_bit =3D <0>; + }; + + pll3_div2: pll3_div2 { + #clock-cells =3D <0>; + compatible =3D "fixed-factor-clock"; + clocks =3D <&pll3>; + clock-div =3D <2>; + clock-mult =3D <1>; + status =3D "okay"; + read-only =3D <0>; + }; + + pll3_div3: pll3_div3 { + #clock-cells =3D <0>; + compatible =3D "fixed-factor-clock"; + clocks =3D <&pll3>; + clock-div =3D <3>; + clock-mult =3D <1>; + status =3D "okay"; + read-only =3D <0>; + }; + + pll3_div4: pll3_div4 { + #clock-cells =3D <0>; + compatible =3D "fixed-factor-clock"; + clocks =3D <&pll3>; + clock-div =3D <4>; + clock-mult =3D <1>; + status =3D "okay"; + read-only =3D <0>; + }; +}; + +&sysctl_clock { + cpu0_src: cpu0_src { + #clock-cells =3D <0>; /* only one output */ + compatible =3D "canaan,k230-clk-composite"; + clocks =3D <&pll0_div2>; /* only one parent */ + status =3D "okay"; + read-only =3D <0>; + + /* rate */ + clk-rate-conf-mul-min =3D <1>; + clk-rate-conf-mul-max =3D <16>; + clk-rate-conf-div-min =3D <16>; + clk-rate-conf-div-max =3D <16>; + clk-rate-calc-method =3D <0>; + clk-rate-reg-offset =3D <0x0>; + clk-rate-reg-mul-value-shift =3D <0>; + clk-rate-reg-mul-value-mask =3D <0>; + clk-rate-reg-div-value-shift =3D <1>; + clk-rate-reg-div-value-mask =3D <0xF>; + clk-rate-reg-write-enable-bit =3D <31>; + + /* gate */ + clk-gate-reg-offset =3D <0x0>; + clk-gate-reg-bit-enable =3D <0>; + clk-gate-reg-bit-reverse =3D <0>; + /* if set to 0(clk-gate-reg-bit-enable set 1 to enable clcok), + *if set to 1(clk-gate-reg-bit-enable set 0 to enable clcok) + */ + }; + + cpu0_plic: cpu0_plic { + #clock-cells =3D <0>; /* only one output */ + compatible =3D "canaan,k230-clk-composite"; + clocks =3D <&cpu0_src>; /* only one parent */ + status =3D "okay"; + read-only =3D <0>; + + /* rate */ + clk-rate-conf-mul-min =3D <1>; + clk-rate-conf-mul-max =3D <1>; + clk-rate-conf-div-min =3D <1>; + clk-rate-conf-div-max =3D <8>; + clk-rate-calc-method =3D <1>; + + clk-rate-reg-offset =3D <0x0>; + clk-rate-reg-mul-value-shift =3D <0>; + clk-rate-reg-mul-value-mask =3D <0>; + clk-rate-reg-div-value-shift =3D <10>; + clk-rate-reg-div-value-mask =3D <0x7>; + clk-rate-reg-write-enable-bit =3D <31>; + + /* gate */ + clk-gate-reg-offset =3D <0x0>; + clk-gate-reg-bit-enable =3D <9>; + clk-gate-reg-bit-reverse =3D <0>; + }; + + cpu0_aclk: cpu0_aclk { + #clock-cells =3D <0>; /* only one output */ + compatible =3D "canaan,k230-clk-composite"; + clocks =3D <&cpu0_src>; /* only one parent */ + status =3D "okay"; + read-only =3D <0>; + + /* rate */ + clk-rate-conf-mul-min =3D <1>; + clk-rate-conf-mul-max =3D <1>; + clk-rate-conf-div-min =3D <1>; + clk-rate-conf-div-max =3D <8>; + clk-rate-calc-method =3D <1>; + + clk-rate-reg-offset =3D <0x0>; + clk-rate-reg-mul-value-shift =3D <0>; + clk-rate-reg-mul-value-mask =3D <0>; + clk-rate-reg-div-value-shift =3D <6>; + clk-rate-reg-div-value-mask =3D <0x7>; + clk-rate-reg-write-enable-bit =3D <31>; + }; + + cpu0_noc_ddrcp4: cpu0_noc_ddrcp4 { + #clock-cells =3D <0>; /* only one output */ + compatible =3D "canaan,k230-clk-composite"; + clocks =3D <&cpu0_src>;/* only one parent */ + status =3D "okay"; + read-only =3D <0>; + + /* gate */ + clk-gate-reg-offset =3D <0x60>; + clk-gate-reg-bit-enable =3D <7>; + clk-gate-reg-bit-reverse =3D <0>; + }; + + cpu0_pclk: cpu0_pclk { + #clock-cells =3D <0>; /* only one output */ + compatible =3D "canaan,k230-clk-composite"; + clocks =3D <&pll0_div4>; /* only one parent */ + status =3D "okay"; + read-only =3D <0>; + + /* rate */ + clk-rate-conf-mul-min =3D <1>; + clk-rate-conf-mul-max =3D <1>; + clk-rate-conf-div-min =3D <1>; + clk-rate-conf-div-max =3D <8>; + clk-rate-calc-method =3D <1>; + + clk-rate-reg-offset =3D <0x0>; + clk-rate-reg-mul-value-shift =3D <0>; + clk-rate-reg-mul-value-mask =3D <0>; + clk-rate-reg-div-value-shift =3D <15>; + clk-rate-reg-div-value-mask =3D <0x7>; + clk-rate-reg-write-enable-bit =3D <31>; + + /* gate */ + clk-gate-reg-offset =3D <0x0>; + clk-gate-reg-bit-enable =3D <13>; + clk-gate-reg-bit-reverse =3D <0>; + }; + + pmu_pclk: pmu_pclk { + #clock-cells =3D <0>; + compatible =3D "canaan,k230-clk-composite"; + clocks =3D <&osc24m>; + status =3D "okay"; + read-only =3D <0>; + + /* gate */ + clk-gate-reg-offset =3D <0x10>; + clk-gate-reg-bit-enable =3D <0>; + clk-gate-reg-bit-reverse =3D <0>; + }; + + hs_hclk_high_src: hs_hclk_high_src { + #clock-cells =3D <0>; + compatible =3D "canaan,k230-clk-composite"; + clocks =3D <&pll0_div4>; + status =3D "okay"; + read-only =3D <0>; + + /* rate */ + clk-rate-conf-mul-min =3D <1>; + clk-rate-conf-mul-max =3D <1>; + clk-rate-conf-div-min =3D <1>; + clk-rate-conf-div-max =3D <8>; + clk-rate-calc-method =3D <1>; + clk-rate-reg-offset =3D <0x1C>; + clk-rate-reg-mul-value-shift =3D <0>; + clk-rate-reg-mul-value-mask =3D <0>; + clk-rate-reg-div-value-shift =3D <0>; + clk-rate-reg-div-value-mask =3D <0x7>; + clk-rate-reg-write-enable-bit =3D <31>; + }; + hs_hclk_high: hs_hclk_high { + #clock-cells =3D <0>; + compatible =3D "canaan,k230-clk-composite"; + clocks =3D <&hs_hclk_high_src>; + status =3D "okay"; + read-only =3D <0>; + + /* gate */ + clk-gate-reg-offset =3D <0x18>; + clk-gate-reg-bit-enable =3D <1>; + clk-gate-reg-bit-reverse =3D <0>; + }; + hs_hclk_src: hs_hclk_src { + #clock-cells =3D <0>; + compatible =3D "canaan,k230-clk-composite"; + clocks =3D <&hs_hclk_high_src>; + status =3D "okay"; + read-only =3D <0>; + + /* rate */ + clk-rate-conf-mul-min =3D <1>; + clk-rate-conf-mul-max =3D <1>; + clk-rate-conf-div-min =3D <1>; + clk-rate-conf-div-max =3D <8>; + clk-rate-calc-method =3D <1>; + + clk-rate-reg-offset =3D <0x1C>; + clk-rate-reg-mul-value-shift =3D <0>; + clk-rate-reg-mul-value-mask =3D <0>; + clk-rate-reg-div-value-shift =3D <3>; + clk-rate-reg-div-value-mask =3D <0x7>; + clk-rate-reg-write-enable-bit =3D <31>; + + /* gate */ + clk-gate-reg-offset =3D <0x18>; + clk-gate-reg-bit-enable =3D <0>; + clk-gate-reg-bit-reverse =3D <0>; + }; + sd0_hclk_gate: sd0_hclk_gate { + #clock-cells =3D <0>; + compatible =3D "canaan,k230-clk-composite"; + clocks =3D <&hs_hclk_src>; + status =3D "okay"; + read-only =3D <0>; + + /* gate */ + clk-gate-reg-offset =3D <0x18>; + clk-gate-reg-bit-enable =3D <2>; + clk-gate-reg-bit-reverse =3D <0>; + }; + sd1_hclk_gate: sd1_hclk_gate { + #clock-cells =3D <0>; + compatible =3D "canaan,k230-clk-composite"; + clocks =3D <&hs_hclk_src>; + status =3D "okay"; + read-only =3D <0>; + + /* gate */ + clk-gate-reg-offset =3D <0x18>; + clk-gate-reg-bit-enable =3D <3>; + clk-gate-reg-bit-reverse =3D <0>; + }; + usb0_hclk_gate: usb0_hclk_gate { + #clock-cells =3D <0>; + compatible =3D "canaan,k230-clk-composite"; + clocks =3D <&hs_hclk_src>; + status =3D "okay"; + read-only =3D <0>; + + /* gate */ + clk-gate-reg-offset =3D <0x18>; + clk-gate-reg-bit-enable =3D <4>; + clk-gate-reg-bit-reverse =3D <0>; + }; + usb1_hclk_gate: usb1_hclk_gate { + #clock-cells =3D <0>; + compatible =3D "canaan,k230-clk-composite"; + clocks =3D <&hs_hclk_src>; + status =3D "okay"; + read-only =3D <0>; + + /* gate */ + clk-gate-reg-offset =3D <0x18>; + clk-gate-reg-bit-enable =3D <5>; + clk-gate-reg-bit-reverse =3D <0>; + }; + ssi1_hclk_gate: ssi1_hclk_gate { + #clock-cells =3D <0>; + compatible =3D "canaan,k230-clk-composite"; + clocks =3D <&hs_hclk_src>; + status =3D "okay"; + read-only =3D <0>; + + /* gate */ + clk-gate-reg-offset =3D <0x18>; + clk-gate-reg-bit-enable =3D <7>; + clk-gate-reg-bit-reverse =3D <0>; + }; + ssi2_hclk_gate: ssi2_hclk_gate { + #clock-cells =3D <0>; + compatible =3D "canaan,k230-clk-composite"; + clocks =3D <&hs_hclk_src>; + status =3D "okay"; + read-only =3D <0>; + + /* gate */ + clk-gate-reg-offset =3D <0x18>; + clk-gate-reg-bit-enable =3D <8>; + clk-gate-reg-bit-reverse =3D <0>; + }; + + ssi0_aclk: ssi0_aclk { + #clock-cells =3D <0>; + compatible =3D "canaan,k230-clk-composite"; + clocks =3D <&pll0_div4>; + status =3D "okay"; + read-only =3D <0>; + + /* rate */ + clk-rate-conf-mul-min =3D <1>; + clk-rate-conf-mul-max =3D <1>; + clk-rate-conf-div-min =3D <1>; + clk-rate-conf-div-max =3D <8>; + clk-rate-calc-method =3D <1>; + + clk-rate-reg-offset =3D <0x20>; + clk-rate-reg-mul-value-shift =3D <0>; + clk-rate-reg-mul-value-mask =3D <0>; + clk-rate-reg-div-value-shift =3D <9>; + clk-rate-reg-div-value-mask =3D <0x7>; + clk-rate-reg-write-enable-bit =3D <31>; + + /* gate */ + clk-gate-reg-offset =3D <0x18>; + clk-gate-reg-bit-enable =3D <27>; + clk-gate-reg-bit-reverse =3D <0>; + }; + + ssi1_clk: ssi1_clk { + #clock-cells =3D <0>; + compatible =3D "canaan,k230-clk-composite"; + clocks =3D <&pll0_div4>; + status =3D "okay"; + read-only =3D <0>; + + /* rate */ + clk-rate-conf-mul-min =3D <1>; + clk-rate-conf-mul-max =3D <1>; + clk-rate-conf-div-min =3D <1>; + clk-rate-conf-div-max =3D <8>; + clk-rate-calc-method =3D <1>; + clk-rate-reg-offset =3D <0x20>; + clk-rate-reg-mul-value-shift =3D <0>; + clk-rate-reg-mul-value-mask =3D <0>; + clk-rate-reg-div-value-shift =3D <3>; + clk-rate-reg-div-value-mask =3D <0x7>; + clk-rate-reg-write-enable-bit =3D <31>; + + /* gate */ + clk-gate-reg-offset =3D <0x18>; + clk-gate-reg-bit-enable =3D <25>; + clk-gate-reg-bit-reverse =3D <0>; + }; + + ssi2_clk: ssi2_clk { + #clock-cells =3D <0>; + compatible =3D "canaan,k230-clk-composite"; + clocks =3D <&pll0_div4>; + status =3D "okay"; + read-only =3D <0>; + + /* rate */ + clk-rate-conf-mul-min =3D <1>; + clk-rate-conf-mul-max =3D <1>; + clk-rate-conf-div-min =3D <1>; + clk-rate-conf-div-max =3D <8>; + clk-rate-calc-method =3D <1>; + clk-rate-reg-offset =3D <0x20>; + clk-rate-reg-mul-value-shift =3D <0>; + clk-rate-reg-mul-value-mask =3D <0>; + clk-rate-reg-div-value-shift =3D <6>; + clk-rate-reg-div-value-mask =3D <0x7>; + clk-rate-reg-write-enable-bit =3D <31>; + + /* gate */ + clk-gate-reg-offset =3D <0x18>; + clk-gate-reg-bit-enable =3D <26>; + clk-gate-reg-bit-reverse =3D <0>; + }; + + qspi_aclk_src: qspi_aclk_src { + #clock-cells =3D <0>; + compatible =3D "canaan,k230-clk-composite"; + clocks =3D <&pll0_div4>; + status =3D "okay"; + read-only =3D <0>; + + /* rate */ + clk-rate-conf-mul-min =3D <1>; + clk-rate-conf-mul-max =3D <1>; + clk-rate-conf-div-min =3D <1>; + clk-rate-conf-div-max =3D <8>; + clk-rate-calc-method =3D <1>; + clk-rate-reg-offset =3D <0x20>; + clk-rate-reg-mul-value-shift =3D <0>; + clk-rate-reg-mul-value-mask =3D <0>; + clk-rate-reg-div-value-shift =3D <12>; + clk-rate-reg-div-value-mask =3D <0x7>; + clk-rate-reg-write-enable-bit =3D <31>; + + /* gate */ + clk-gate-reg-offset =3D <0x18>; + clk-gate-reg-bit-enable =3D <28>; + clk-gate-reg-bit-reverse =3D <0>; + }; + ssi1_aclk_gate: ssi1_aclk_gate { + #clock-cells =3D <0>; + compatible =3D "canaan,k230-clk-composite"; + clocks =3D <&qspi_aclk_src>; + status =3D "okay"; + read-only =3D <0>; + + /* gate */ + clk-gate-reg-offset =3D <0x18>; + clk-gate-reg-bit-enable =3D <29>; + clk-gate-reg-bit-reverse =3D <0>; + }; + ssi2_aclk_gate: ssi2_aclk_gate { + #clock-cells =3D <0>; + compatible =3D "canaan,k230-clk-composite"; + clocks =3D <&qspi_aclk_src>; + status =3D "okay"; + read-only =3D <0>; + + /* gate */ + clk-gate-reg-offset =3D <0x18>; + clk-gate-reg-bit-enable =3D <30>; + clk-gate-reg-bit-reverse =3D <0>; + }; + + ssi0_clk: ssi0_clk { + #clock-cells =3D <0>; + compatible =3D "canaan,k230-clk-composite"; + status =3D "okay"; + read-only =3D <0>; + + /* parent */ + clocks =3D <&pll0_div2>, <&pll2_div4>; /* mux parent */ + clk-parent-reg-offset =3D <0x20>; + clk-parent-reg-value-shift =3D <18>; + clk-parent-reg-value-mask =3D <0x1>; + + /* gate */ + clk-gate-reg-offset =3D <0x18>; + clk-gate-reg-bit-enable =3D <24>; + clk-gate-reg-bit-reverse =3D <0>; + }; + + sd_aclk: sd_aclk { + #clock-cells =3D <0>; + compatible =3D "canaan,k230-clk-composite"; + clocks =3D <&pll2_div4>; + status =3D "okay"; + read-only =3D <0>; + + /* rate */ + clk-rate-conf-mul-min =3D <1>; + clk-rate-conf-mul-max =3D <1>; + clk-rate-conf-div-min =3D <1>; + clk-rate-conf-div-max =3D <8>; + clk-rate-calc-method =3D <1>; + clk-rate-reg-offset =3D <0x1C>; + clk-rate-reg-mul-value-shift =3D <0>; + clk-rate-reg-mul-value-mask =3D <0>; + clk-rate-reg-div-value-shift =3D <6>; + clk-rate-reg-div-value-mask =3D <0x7>; + clk-rate-reg-write-enable-bit =3D <31>; + + /* gate */ + clk-gate-reg-offset =3D <0x18>; + clk-gate-reg-bit-enable =3D <9>; + clk-gate-reg-bit-reverse =3D <0>; + }; + sd0_aclk_gate: sd0_aclk_gate { + #clock-cells =3D <0>; + compatible =3D "canaan,k230-clk-composite"; + clocks =3D <&sd_aclk>; + status =3D "okay"; + read-only =3D <0>; + + /* gate */ + clk-gate-reg-offset =3D <0x18>; + clk-gate-reg-bit-enable =3D <13>; + clk-gate-reg-bit-reverse =3D <0>; + }; + sd1_aclk_gate: sd1_aclk_gate { + #clock-cells =3D <0>; + compatible =3D "canaan,k230-clk-composite"; + clocks =3D <&sd_aclk>; + status =3D "okay"; + read-only =3D <0>; + + /* gate */ + clk-gate-reg-offset =3D <0x18>; + clk-gate-reg-bit-enable =3D <17>; + clk-gate-reg-bit-reverse =3D <0>; + }; + sd0_bclk_gate: sd0_bclk_gate { + #clock-cells =3D <0>; + compatible =3D "canaan,k230-clk-composite"; + clocks =3D <&sd_aclk>; + status =3D "okay"; + read-only =3D <0>; + + /* gate */ + clk-gate-reg-offset =3D <0x18>; + clk-gate-reg-bit-enable =3D <14>; + clk-gate-reg-bit-reverse =3D <0>; + }; + sd1_bclk_gate: sd1_bclk_gate { + #clock-cells =3D <0>; + compatible =3D "canaan,k230-clk-composite"; + clocks =3D <&sd_aclk>; + status =3D "okay"; + read-only =3D <0>; + + /* gate */ + clk-gate-reg-offset =3D <0x18>; + clk-gate-reg-bit-enable =3D <18>; + clk-gate-reg-bit-reverse =3D <0>; + }; + + sd_cclk_src: sd_cclk_src { + #clock-cells =3D <0>; + compatible =3D "canaan,k230-clk-composite"; + clocks =3D <&pll0_div4>; + status =3D "okay"; + read-only =3D <0>; + + /* rate */ + clk-rate-conf-mul-min =3D <1>; + clk-rate-conf-mul-max =3D <1>; + clk-rate-conf-div-min =3D <2>; /* maxinum =3D 1/2, 1/2, 1/3 --- 1/8 */ + clk-rate-conf-div-max =3D <8>; + clk-rate-calc-method =3D <1>; + clk-rate-reg-offset =3D <0x1C>; + clk-rate-reg-mul-value-shift =3D <0>; + clk-rate-reg-mul-value-mask =3D <0>; + clk-rate-reg-div-value-shift =3D <12>; + clk-rate-reg-div-value-mask =3D <0x7>; + clk-rate-reg-write-enable-bit =3D <31>; + + /* gate */ + clk-gate-reg-offset =3D <0x18>; + clk-gate-reg-bit-enable =3D <11>; + clk-gate-reg-bit-reverse =3D <0>; + }; + sd0_cclk_gate: sd0_cclk_gate { + #clock-cells =3D <0>; + compatible =3D "canaan,k230-clk-composite"; + clocks =3D <&sd_cclk_src>; + status =3D "okay"; + read-only =3D <0>; + + /* gate */ + clk-gate-reg-offset =3D <0x18>; + clk-gate-reg-bit-enable =3D <15>; + clk-gate-reg-bit-reverse =3D <0>; + }; + sd1_cclk_gate: sd1_cclk_gate { + #clock-cells =3D <0>; + compatible =3D "canaan,k230-clk-composite"; + clocks =3D <&sd_cclk_src>; + status =3D "okay"; + read-only =3D <0>; + + /* gate */ + clk-gate-reg-offset =3D <0x18>; + clk-gate-reg-bit-enable =3D <19>; + clk-gate-reg-bit-reverse =3D <0>; + }; + + pll0_div16: pll0_div16 { + #clock-cells =3D <0>; + compatible =3D "fixed-factor-clock"; + clocks =3D <&pll0>; + clock-div =3D <16>; + clock-mult =3D <1>; + status =3D "okay"; + read-only =3D <0>; + }; + usb_ref_50m: usb_ref_50m { + #clock-cells =3D <0>; + compatible =3D "canaan,k230-clk-composite"; + clocks =3D <&pll0_div16>; + status =3D "okay"; + read-only =3D <0>; + + /* rate */ + clk-rate-conf-mul-min =3D <1>; + clk-rate-conf-mul-max =3D <1>; + clk-rate-conf-div-min =3D <1>; + clk-rate-conf-div-max =3D <8>; + clk-rate-calc-method =3D <1>; + clk-rate-reg-offset =3D <0x20>; + clk-rate-reg-mul-value-shift =3D <0>; + clk-rate-reg-mul-value-mask =3D <0>; + clk-rate-reg-div-value-shift =3D <15>; + clk-rate-reg-div-value-mask =3D <0x7>; + clk-rate-reg-write-enable-bit =3D <31>; + }; + usb0_ref_clk: usb0_ref_clk { + #clock-cells =3D <0>; + compatible =3D "canaan,k230-clk-composite"; + status =3D "okay"; + read-only =3D <0>; + + /* parent */ + clocks =3D <&osc24m>, <&usb_ref_50m>; /* mux parent */ + clk-parent-reg-offset =3D <0x18>; + clk-parent-reg-value-shift =3D <23>; + clk-parent-reg-value-mask =3D <0x1>; + + /* gate */ + clk-gate-reg-offset =3D <0x18>; + clk-gate-reg-bit-enable =3D <21>; + clk-gate-reg-bit-reverse =3D <0>; + }; + usb1_ref_clk: usb1_ref_clk { + #clock-cells =3D <0>; + compatible =3D "canaan,k230-clk-composite"; + status =3D "okay"; + read-only =3D <0>; + + /* parent */ + clocks =3D <&osc24m>, <&usb_ref_50m>; /* mux parent */ + clk-parent-reg-offset =3D <0x18>; + clk-parent-reg-value-shift =3D <23>; + clk-parent-reg-value-mask =3D <0x1>; + + /* gate */ + clk-gate-reg-offset =3D <0x18>; + clk-gate-reg-bit-enable =3D <22>; + clk-gate-reg-bit-reverse =3D <0>; + }; + + sd_tmclk_src: sd_tmclk_src { + #clock-cells =3D <0>; + compatible =3D "canaan,k230-clk-composite"; + clocks =3D <&osc24m>; + status =3D "okay"; + read-only =3D <0>; + + /* rate */ + clk-rate-conf-mul-min =3D <1>; + clk-rate-conf-mul-max =3D <1>; + clk-rate-conf-div-min =3D <24>; + clk-rate-conf-div-max =3D <32>; + clk-rate-calc-method =3D <1>; + clk-rate-reg-offset =3D <0x1C>; + clk-rate-reg-mul-value-shift =3D <0>; + clk-rate-reg-mul-value-mask =3D <0>; + clk-rate-reg-div-value-shift =3D <15>; + clk-rate-reg-div-value-mask =3D <0x1F>; + clk-rate-reg-write-enable-bit =3D <31>; + + /* gate */ + clk-gate-reg-offset =3D <0x18>; + clk-gate-reg-bit-enable =3D <12>; + clk-gate-reg-bit-reverse =3D <0>; + }; + sd0_tmclk_gate: sd0_tmclk_gate { + #clock-cells =3D <0>; + compatible =3D "canaan,k230-clk-composite"; + clocks =3D <&sd_tmclk_src>; + status =3D "okay"; + read-only =3D <0>; + + /* gate */ + clk-gate-reg-offset =3D <0x18>; + clk-gate-reg-bit-enable =3D <16>; + clk-gate-reg-bit-reverse =3D <0>; + }; + sd1_tmclk_gate: sd1_tmclk_gate { + #clock-cells =3D <0>; + compatible =3D "canaan,k230-clk-composite"; + clocks =3D <&sd_tmclk_src>; + status =3D "okay"; + read-only =3D <0>; + + /* gate */ + clk-gate-reg-offset =3D <0x18>; + clk-gate-reg-bit-enable =3D <20>; + clk-gate-reg-bit-reverse =3D <0>; + }; + + ls_pclk_src: ls_pclk_src { + #clock-cells =3D <0>; + compatible =3D "canaan,k230-clk-composite"; + clocks =3D <&pll0_div4>; + status =3D "okay"; + read-only =3D <0>; + + /* rate */ + clk-rate-conf-mul-min =3D <1>; + clk-rate-conf-mul-max =3D <1>; + clk-rate-conf-div-min =3D <1>; + clk-rate-conf-div-max =3D <8>; + clk-rate-calc-method =3D <1>; + clk-rate-reg-offset =3D <0x30>; + clk-rate-reg-mul-value-shift =3D <0>; + clk-rate-reg-mul-value-mask =3D <0>; + clk-rate-reg-div-value-shift =3D <0>; + clk-rate-reg-div-value-mask =3D <0x7>; + clk-rate-reg-write-enable-bit =3D <31>; + + /* gate */ + clk-gate-reg-offset =3D <0x24>; + clk-gate-reg-bit-enable =3D <0>; + clk-gate-reg-bit-reverse =3D <0>; + }; + uart0_pclk_gate: uart0_pclk_gate { + #clock-cells =3D <0>; + compatible =3D "canaan,k230-clk-composite"; + clocks =3D <&ls_pclk_src>; + status =3D "okay"; + read-only =3D <0>; + + /* gate */ + clk-gate-reg-offset =3D <0x24>; + clk-gate-reg-bit-enable =3D <1>; + clk-gate-reg-bit-reverse =3D <0>; + }; + uart1_pclk_gate: uart1_pclk_gate { + #clock-cells =3D <0>; + compatible =3D "canaan,k230-clk-composite"; + clocks =3D <&ls_pclk_src>; + status =3D "okay"; + read-only =3D <0>; + + /* gate */ + clk-gate-reg-offset =3D <0x24>; + clk-gate-reg-bit-enable =3D <2>; + clk-gate-reg-bit-reverse =3D <0>; + }; + uart2_pclk_gate: uart2_pclk_gate { + #clock-cells =3D <0>; + compatible =3D "canaan,k230-clk-composite"; + clocks =3D <&ls_pclk_src>; + status =3D "okay"; + read-only =3D <0>; + + /* gate */ + clk-gate-reg-offset =3D <0x24>; + clk-gate-reg-bit-enable =3D <3>; + clk-gate-reg-bit-reverse =3D <0>; + }; + uart3_pclk_gate: uart3_pclk_gate { + #clock-cells =3D <0>; + compatible =3D "canaan,k230-clk-composite"; + clocks =3D <&ls_pclk_src>; + status =3D "okay"; + read-only =3D <0>; + + /* gate */ + clk-gate-reg-offset =3D <0x24>; + clk-gate-reg-bit-enable =3D <4>; + clk-gate-reg-bit-reverse =3D <0>; + }; + uart4_pclk_gate: uart4_pclk_gate { + #clock-cells =3D <0>; + compatible =3D "canaan,k230-clk-composite"; + clocks =3D <&ls_pclk_src>; + status =3D "okay"; + read-only =3D <0>; + + /* gate */ + clk-gate-reg-offset =3D <0x24>; + clk-gate-reg-bit-enable =3D <5>; + clk-gate-reg-bit-reverse =3D <0>; + }; + i2c0_pclk_gate: i2c0_pclk_gate { + #clock-cells =3D <0>; + compatible =3D "canaan,k230-clk-composite"; + clocks =3D <&ls_pclk_src>; + status =3D "okay"; + read-only =3D <0>; + + /* gate */ + clk-gate-reg-offset =3D <0x24>; + clk-gate-reg-bit-enable =3D <6>; + clk-gate-reg-bit-reverse =3D <0>; + }; + i2c1_pclk_gate: i2c1_pclk_gate { + #clock-cells =3D <0>; + compatible =3D "canaan,k230-clk-composite"; + clocks =3D <&ls_pclk_src>; + status =3D "okay"; + read-only =3D <0>; + + /* gate */ + clk-gate-reg-offset =3D <0x24>; + clk-gate-reg-bit-enable =3D <7>; + clk-gate-reg-bit-reverse =3D <0>; + }; + i2c2_pclk_gate: i2c2_pclk_gate { + #clock-cells =3D <0>; + compatible =3D "canaan,k230-clk-composite"; + clocks =3D <&ls_pclk_src>; + status =3D "okay"; + read-only =3D <0>; + + /* gate */ + clk-gate-reg-offset =3D <0x24>; + clk-gate-reg-bit-enable =3D <8>; + clk-gate-reg-bit-reverse =3D <0>; + }; + i2c3_pclk_gate: i2c3_pclk_gate { + #clock-cells =3D <0>; + compatible =3D "canaan,k230-clk-composite"; + clocks =3D <&ls_pclk_src>; + status =3D "okay"; + read-only =3D <0>; + + /* gate */ + clk-gate-reg-offset =3D <0x24>; + clk-gate-reg-bit-enable =3D <9>; + clk-gate-reg-bit-reverse =3D <0>; + }; + i2c4_pclk_gate: i2c4_pclk_gate { + #clock-cells =3D <0>; + compatible =3D "canaan,k230-clk-composite"; + clocks =3D <&ls_pclk_src>; + status =3D "okay"; + read-only =3D <0>; + + /* gate */ + clk-gate-reg-offset =3D <0x24>; + clk-gate-reg-bit-enable =3D <10>; + clk-gate-reg-bit-reverse =3D <0>; + }; + gpio_pclk_gate: gpio_pclk_gate { + #clock-cells =3D <0>; + compatible =3D "canaan,k230-clk-composite"; + clocks =3D <&ls_pclk_src>; + status =3D "okay"; + read-only =3D <0>; + + /* gate */ + clk-gate-reg-offset =3D <0x24>; + clk-gate-reg-bit-enable =3D <11>; + clk-gate-reg-bit-reverse =3D <0>; + }; + pwm_pclk_gate: pwm_pclk_gate { + #clock-cells =3D <0>; + compatible =3D "canaan,k230-clk-composite"; + clocks =3D <&ls_pclk_src>; + status =3D "okay"; + read-only =3D <0>; + + /* gate */ + clk-gate-reg-offset =3D <0x24>; + clk-gate-reg-bit-enable =3D <12>; + clk-gate-reg-bit-reverse =3D <0>; + }; + jamlink0_pclk_gate: jamlink0_pclk_gate { + #clock-cells =3D <0>; + compatible =3D "canaan,k230-clk-composite"; + clocks =3D <&ls_pclk_src>; + status =3D "okay"; + read-only =3D <0>; + + /* gate */ + clk-gate-reg-offset =3D <0x28>; + clk-gate-reg-bit-enable =3D <4>; + clk-gate-reg-bit-reverse =3D <0>; + }; + jamlink1_pclk_gate: jamlink1_pclk_gate { + #clock-cells =3D <0>; + compatible =3D "canaan,k230-clk-composite"; + clocks =3D <&ls_pclk_src>; + status =3D "okay"; + read-only =3D <0>; + + /* gate */ + clk-gate-reg-offset =3D <0x28>; + clk-gate-reg-bit-enable =3D <5>; + clk-gate-reg-bit-reverse =3D <0>; + }; + jamlink2_pclk_gate: jamlink2_pclk_gate { + #clock-cells =3D <0>; + compatible =3D "canaan,k230-clk-composite"; + clocks =3D <&ls_pclk_src>; + status =3D "okay"; + read-only =3D <0>; + + /* gate */ + clk-gate-reg-offset =3D <0x28>; + clk-gate-reg-bit-enable =3D <6>; + clk-gate-reg-bit-reverse =3D <0>; + }; + jamlink3_pclk_gate: jamlink3_pclk_gate { + #clock-cells =3D <0>; + compatible =3D "canaan,k230-clk-composite"; + clocks =3D <&ls_pclk_src>; + status =3D "okay"; + read-only =3D <0>; + + /* gate */ + clk-gate-reg-offset =3D <0x28>; + clk-gate-reg-bit-enable =3D <7>; + clk-gate-reg-bit-reverse =3D <0>; + }; + audio_pclk_gate: audio_pclk_gate { + #clock-cells =3D <0>; + compatible =3D "canaan,k230-clk-composite"; + clocks =3D <&ls_pclk_src>; + status =3D "okay"; + read-only =3D <0>; + + /* gate */ + clk-gate-reg-offset =3D <0x24>; + clk-gate-reg-bit-enable =3D <13>; + clk-gate-reg-bit-reverse =3D <0>; + }; + adc_pclk_gate: adc_pclk_gate { + #clock-cells =3D <0>; + compatible =3D "canaan,k230-clk-composite"; + clocks =3D <&ls_pclk_src>; + status =3D "okay"; + read-only =3D <0>; + + /* gate */ + clk-gate-reg-offset =3D <0x24>; + clk-gate-reg-bit-enable =3D <15>; + clk-gate-reg-bit-reverse =3D <0>; + }; + codec_pclk_gate: codec_pclk_gate { + #clock-cells =3D <0>; + compatible =3D "canaan,k230-clk-composite"; + clocks =3D <&ls_pclk_src>; + status =3D "okay"; + read-only =3D <0>; + + /* gate */ + clk-gate-reg-offset =3D <0x24>; + clk-gate-reg-bit-enable =3D <14>; + clk-gate-reg-bit-reverse =3D <0>; + }; + + uart0_clk: uart0_clk { + #clock-cells =3D <0>; + compatible =3D "canaan,k230-clk-composite"; + clocks =3D <&pll0_div16>; + status =3D "okay"; + read-only =3D <0>; + + /* rate */ + clk-rate-conf-mul-min =3D <1>; + clk-rate-conf-mul-max =3D <1>; + clk-rate-conf-div-min =3D <1>; + clk-rate-conf-div-max =3D <8>; + clk-rate-calc-method =3D <1>; + clk-rate-reg-offset =3D <0x2C>; + clk-rate-reg-mul-value-shift =3D <0>; + clk-rate-reg-mul-value-mask =3D <0>; + clk-rate-reg-div-value-shift =3D <0>; + clk-rate-reg-div-value-mask =3D <0x7>; + clk-rate-reg-write-enable-bit =3D <31>; + + /* gate */ + clk-gate-reg-offset =3D <0x24>; + clk-gate-reg-bit-enable =3D <16>; + clk-gate-reg-bit-reverse =3D <0>; + }; + + uart1_clk: uart1_clk { + #clock-cells =3D <0>; + compatible =3D "canaan,k230-clk-composite"; + clocks =3D <&pll0_div16>; + status =3D "okay"; + read-only =3D <0>; + + /* rate */ + clk-rate-conf-mul-min =3D <1>; + clk-rate-conf-mul-max =3D <1>; + clk-rate-conf-div-min =3D <1>; + clk-rate-conf-div-max =3D <8>; + clk-rate-calc-method =3D <1>; + clk-rate-reg-offset =3D <0x2C>; + clk-rate-reg-mul-value-shift =3D <0>; + clk-rate-reg-mul-value-mask =3D <0>; + clk-rate-reg-div-value-shift =3D <3>; + clk-rate-reg-div-value-mask =3D <0x7>; + clk-rate-reg-write-enable-bit =3D <31>; + + /* gate */ + clk-gate-reg-offset =3D <0x24>; + clk-gate-reg-bit-enable =3D <17>; + clk-gate-reg-bit-reverse =3D <0>; + }; + + uart2_clk: uart2_clk { + #clock-cells =3D <0>; + compatible =3D "canaan,k230-clk-composite"; + clocks =3D <&pll0_div16>; + status =3D "okay"; + read-only =3D <0>; + + /* rate */ + clk-rate-conf-mul-min =3D <1>; + clk-rate-conf-mul-max =3D <1>; + clk-rate-conf-div-min =3D <1>; + clk-rate-conf-div-max =3D <8>; + clk-rate-calc-method =3D <1>; + clk-rate-reg-offset =3D <0x2C>; + clk-rate-reg-mul-value-shift =3D <0>; + clk-rate-reg-mul-value-mask =3D <0>; + clk-rate-reg-div-value-shift =3D <6>; + clk-rate-reg-div-value-mask =3D <0x7>; + clk-rate-reg-write-enable-bit =3D <31>; + + /* gate */ + clk-gate-reg-offset =3D <0x24>; + clk-gate-reg-bit-enable =3D <18>; + clk-gate-reg-bit-reverse =3D <0>; + }; + + uart3_clk: uart3_clk { + #clock-cells =3D <0>; + compatible =3D "canaan,k230-clk-composite"; + clocks =3D <&pll0_div16>; + status =3D "okay"; + read-only =3D <0>; + + /* rate */ + clk-rate-conf-mul-min =3D <1>; + clk-rate-conf-mul-max =3D <1>; + clk-rate-conf-div-min =3D <1>; + clk-rate-conf-div-max =3D <8>; + clk-rate-calc-method =3D <1>; + clk-rate-reg-offset =3D <0x2C>; + clk-rate-reg-mul-value-shift =3D <0>; + clk-rate-reg-mul-value-mask =3D <0>; + clk-rate-reg-div-value-shift =3D <9>; + clk-rate-reg-div-value-mask =3D <0x7>; + clk-rate-reg-write-enable-bit =3D <31>; + + /* gate */ + clk-gate-reg-offset =3D <0x24>; + clk-gate-reg-bit-enable =3D <19>; + clk-gate-reg-bit-reverse =3D <0>; + }; + + uart4_clk: uart4_clk { + #clock-cells =3D <0>; + compatible =3D "canaan,k230-clk-composite"; + clocks =3D <&pll0_div16>; + status =3D "okay"; + read-only =3D <0>; + + /* rate */ + clk-rate-conf-mul-min =3D <1>; + clk-rate-conf-mul-max =3D <1>; + clk-rate-conf-div-min =3D <1>; + clk-rate-conf-div-max =3D <8>; + clk-rate-calc-method =3D <1>; + clk-rate-reg-offset =3D <0x2C>; + clk-rate-reg-mul-value-shift =3D <0>; + clk-rate-reg-mul-value-mask =3D <0>; + clk-rate-reg-div-value-shift =3D <12>; + clk-rate-reg-div-value-mask =3D <0x7>; + clk-rate-reg-write-enable-bit =3D <31>; + + /* gate */ + clk-gate-reg-offset =3D <0x24>; + clk-gate-reg-bit-enable =3D <20>; + clk-gate-reg-bit-reverse =3D <0>; + }; + + jamlinkCO_div: jamlinkCO_div { + #clock-cells =3D <0>; + compatible =3D "canaan,k230-clk-composite"; + clocks =3D <&pll0_div16>; + status =3D "okay"; + read-only =3D <0>; + + /* rate */ + clk-rate-conf-mul-min =3D <1>; + clk-rate-conf-mul-max =3D <1>; + clk-rate-conf-div-min =3D <2>; + clk-rate-conf-div-max =3D <512>; + clk-rate-calc-method =3D <1>; + clk-rate-reg-offset =3D <0x30>; + clk-rate-reg-mul-value-shift =3D <0>; + clk-rate-reg-mul-value-mask =3D <0>; + clk-rate-reg-div-value-shift =3D <23>; + clk-rate-reg-div-value-mask =3D <0xFF>; + clk-rate-reg-write-enable-bit =3D <31>; + }; + jamlink0CO_gate: jamlink0CO_gate { + #clock-cells =3D <0>; + compatible =3D "canaan,k230-clk-composite"; + clocks =3D <&jamlinkCO_div>; + status =3D "okay"; + read-only =3D <0>; + + /* gate */ + clk-gate-reg-offset =3D <0x28>; + clk-gate-reg-bit-enable =3D <0>; + clk-gate-reg-bit-reverse =3D <0>; + }; + jamlink1CO_gate: jamlink1CO_gate { + #clock-cells =3D <0>; + compatible =3D "canaan,k230-clk-composite"; + clocks =3D <&jamlinkCO_div>; + status =3D "okay"; + read-only =3D <0>; + + /* gate */ + clk-gate-reg-offset =3D <0x28>; + clk-gate-reg-bit-enable =3D <1>; + clk-gate-reg-bit-reverse =3D <0>; + }; + jamlink2CO_gate: jamlink2CO_gate { + #clock-cells =3D <0>; + compatible =3D "canaan,k230-clk-composite"; + clocks =3D <&jamlinkCO_div>; + status =3D "okay"; + read-only =3D <0>; + + /* gate */ + clk-gate-reg-offset =3D <0x28>; + clk-gate-reg-bit-enable =3D <2>; + clk-gate-reg-bit-reverse =3D <0>; + }; + jamlink3CO_gate: jamlink3CO_gate { + #clock-cells =3D <0>; + compatible =3D "canaan,k230-clk-composite"; + clocks =3D <&jamlinkCO_div>; + status =3D "okay"; + read-only =3D <0>; + + /* gate */ + clk-gate-reg-offset =3D <0x28>; + clk-gate-reg-bit-enable =3D <3>; + clk-gate-reg-bit-reverse =3D <0>; + }; + + i2c0_clk: i2c0_clk { + #clock-cells =3D <0>; + compatible =3D "canaan,k230-clk-composite"; + clocks =3D <&pll0_div4>; + status =3D "okay"; + read-only =3D <0>; + + /* rate */ + clk-rate-conf-mul-min =3D <1>; + clk-rate-conf-mul-max =3D <1>; + clk-rate-conf-div-min =3D <1>; + clk-rate-conf-div-max =3D <8>; + clk-rate-calc-method =3D <1>; + clk-rate-reg-offset =3D <0x2C>; + clk-rate-reg-mul-value-shift =3D <0>; + clk-rate-reg-mul-value-mask =3D <0>; + clk-rate-reg-div-value-shift =3D <15>; + clk-rate-reg-div-value-mask =3D <0x7>; + clk-rate-reg-write-enable-bit =3D <31>; + + /* gate */ + clk-gate-reg-offset =3D <0x24>; + clk-gate-reg-bit-enable =3D <21>; + clk-gate-reg-bit-reverse =3D <0>; + }; + + i2c1_clk: i2c1_clk { + #clock-cells =3D <0>; + compatible =3D "canaan,k230-clk-composite"; + clocks =3D <&pll0_div4>; + status =3D "okay"; + read-only =3D <0>; + + /* rate */ + clk-rate-conf-mul-min =3D <1>; + clk-rate-conf-mul-max =3D <1>; + clk-rate-conf-div-min =3D <1>; + clk-rate-conf-div-max =3D <8>; + clk-rate-calc-method =3D <1>; + clk-rate-reg-offset =3D <0x2C>; + clk-rate-reg-mul-value-shift =3D <0>; + clk-rate-reg-mul-value-mask =3D <0>; + clk-rate-reg-div-value-shift =3D <18>; + clk-rate-reg-div-value-mask =3D <0x7>; + clk-rate-reg-write-enable-bit =3D <31>; + + /* gate */ + clk-gate-reg-offset =3D <0x24>; + clk-gate-reg-bit-enable =3D <22>; + clk-gate-reg-bit-reverse =3D <0>; + }; + + i2c2_clk: i2c2_clk { + #clock-cells =3D <0>; + compatible =3D "canaan,k230-clk-composite"; + clocks =3D <&pll0_div4>; + status =3D "okay"; + read-only =3D <0>; + + /* rate */ + clk-rate-conf-mul-min =3D <1>; + clk-rate-conf-mul-max =3D <1>; + clk-rate-conf-div-min =3D <1>; + clk-rate-conf-div-max =3D <8>; + clk-rate-calc-method =3D <1>; + clk-rate-reg-offset =3D <0x2C>; + clk-rate-reg-mul-value-shift =3D <0>; + clk-rate-reg-mul-value-mask =3D <0>; + clk-rate-reg-div-value-shift =3D <21>; + clk-rate-reg-div-value-mask =3D <0x7>; + clk-rate-reg-write-enable-bit =3D <31>; + + /* gate */ + clk-gate-reg-offset =3D <0x24>; + clk-gate-reg-bit-enable =3D <23>; + clk-gate-reg-bit-reverse =3D <0>; + }; + + i2c3_clk: i2c3_clk { + #clock-cells =3D <0>; + compatible =3D "canaan,k230-clk-composite"; + clocks =3D <&pll0_div4>; + status =3D "okay"; + read-only =3D <0>; + + /* rate */ + clk-rate-conf-mul-min =3D <1>; + clk-rate-conf-mul-max =3D <1>; + clk-rate-conf-div-min =3D <1>; + clk-rate-conf-div-max =3D <8>; + clk-rate-calc-method =3D <1>; + clk-rate-reg-offset =3D <0x2C>; + clk-rate-reg-mul-value-shift =3D <0>; + clk-rate-reg-mul-value-mask =3D <0>; + clk-rate-reg-div-value-shift =3D <24>; + clk-rate-reg-div-value-mask =3D <0x7>; + clk-rate-reg-write-enable-bit =3D <31>; + + /* gate */ + clk-gate-reg-offset =3D <0x24>; + clk-gate-reg-bit-enable =3D <24>; + clk-gate-reg-bit-reverse =3D <0>; + }; + + i2c4_clk: i2c4_clk { + #clock-cells =3D <0>; + compatible =3D "canaan,k230-clk-composite"; + clocks =3D <&pll0_div4>; + status =3D "okay"; + read-only =3D <0>; + + /* rate */ + clk-rate-conf-mul-min =3D <1>; + clk-rate-conf-mul-max =3D <1>; + clk-rate-conf-div-min =3D <1>; + clk-rate-conf-div-max =3D <8>; + clk-rate-calc-method =3D <1>; + clk-rate-reg-offset =3D <0x2C>; + clk-rate-reg-mul-value-shift =3D <0>; + clk-rate-reg-mul-value-mask =3D <0>; + clk-rate-reg-div-value-shift =3D <27>; + clk-rate-reg-div-value-mask =3D <0x7>; + clk-rate-reg-write-enable-bit =3D <31>; + + /* gate */ + clk-gate-reg-offset =3D <0x24>; + clk-gate-reg-bit-enable =3D <25>; + clk-gate-reg-bit-reverse =3D <0>; + }; + + codec_adc_mclk: codec_adc_mclk { + #clock-cells =3D <0>; + compatible =3D "canaan,k230-clk-composite"; + clocks =3D <&pll0_div4>; + status =3D "okay"; + read-only =3D <0>; + + /* rate */ + clk-rate-conf-mul-min =3D <0x10>; + clk-rate-conf-mul-max =3D <0x1B9>; + clk-rate-conf-div-min =3D <0xC35>; + clk-rate-conf-div-max =3D <0x3D09>; + clk-rate-calc-method =3D <2>; + clk-rate-reg-offset =3D <0x38>; + clk-rate-reg-mul-value-shift =3D <14>; + clk-rate-reg-mul-value-mask =3D <0x1FFF>; + /* multiple field mask. It's valid when clk-rate-calc-method =3D 2*/ + clk-rate-reg-div-value-shift =3D <0>; + clk-rate-reg-div-value-mask =3D <0x3FFF>; + clk-rate-reg-write-enable-bit =3D <31>; + + /* gate */ + clk-gate-reg-offset =3D <0x24>; + clk-gate-reg-bit-enable =3D <29>; + clk-gate-reg-bit-reverse =3D <0>; + }; + + codec_dac_mclk: codec_dac_mclk { + #clock-cells =3D <0>; + compatible =3D "canaan,k230-clk-composite"; + clocks =3D <&pll0_div4>; + status =3D "okay"; + read-only =3D <0>; + + /* rate */ + clk-rate-conf-mul-min =3D <0x10>; + clk-rate-conf-mul-max =3D <0x1B9>; + clk-rate-conf-div-min =3D <0xC35>; + clk-rate-conf-div-max =3D <0x3D09>; + clk-rate-calc-method =3D <2>; + clk-rate-reg-offset =3D <0x3C>; + clk-rate-reg-mul-value-shift =3D <14>; + clk-rate-reg-mul-value-mask =3D <0x1FFF>; + clk-rate-reg-div-value-shift =3D <0>; + clk-rate-reg-div-value-mask =3D <0x3FFF>; + clk-rate-reg-write-enable-bit =3D <31>; + + /* gate */ + clk-gate-reg-offset =3D <0x24>; + clk-gate-reg-bit-enable =3D <30>; + clk-gate-reg-bit-reverse =3D <0>; + }; + + audio_dev_clk: audio_dev_clk { + #clock-cells =3D <0>; + compatible =3D "canaan,k230-clk-composite"; + clocks =3D <&pll0_div4>; + status =3D "okay"; + read-only =3D <0>; + + /* rate */ + clk-rate-conf-mul-min =3D <0x4>; + clk-rate-conf-mul-max =3D <0x1B9>; + clk-rate-conf-div-min =3D <0xC35>; + clk-rate-conf-div-max =3D <0xF424>; + clk-rate-calc-method =3D <2>; + clk-rate-reg-offset =3D <0x34>; + clk-rate-reg-mul-value-shift =3D <16>; + clk-rate-reg-mul-value-mask =3D <0x7FFF>; + clk-rate-reg-div-value-shift =3D <0>; + clk-rate-reg-div-value-mask =3D <0xFFFF>; + clk-rate-reg-write-enable-bit =3D <31>; + + /* gate */ + clk-gate-reg-offset =3D <0x24>; + clk-gate-reg-bit-enable =3D <28>; + clk-gate-reg-bit-reverse =3D <0>; + }; + + pdm_clk: pdm_clk { + #clock-cells =3D <0>; + compatible =3D "canaan,k230-clk-composite"; + clocks =3D <&pll0_div4>; + status =3D "okay"; + read-only =3D <0>; + + /* rate */ + clk-rate-conf-div-min =3D <0xC35>; + clk-rate-conf-div-max =3D <0x1E848>; + clk-rate-reg-offset =3D <0x40>; + clk-rate-reg-div-value-shift =3D <0>; + clk-rate-reg-div-value-mask =3D <0x1FFFF>; + clk-rate-calc-method =3D <2>; + + /* rate1 */ + clk-rate-conf-mul-min_1 =3D <0x2>; + clk-rate-conf-mul-max_1 =3D <0x1B9>; + clk-rate-reg-offset_1 =3D <0x44>; + clk-rate-reg-mul-value-shift_1 =3D <0>; + clk-rate-reg-mul-value-mask_1 =3D <0xFFFF>; + clk-rate-reg-write-enable-bit_1 =3D <31>; + + /* gate */ + clk-gate-reg-offset =3D <0x24>; + clk-gate-reg-bit-enable =3D <31>; + clk-gate-reg-bit-reverse =3D <0>; + }; + + adc_clk: adc_clk { + #clock-cells =3D <0>; + compatible =3D "canaan,k230-clk-composite"; + clocks =3D <&pll0_div4>; + status =3D "okay"; + read-only =3D <0>; + + /* rate */ + clk-rate-conf-mul-min =3D <1>; + clk-rate-conf-mul-max =3D <1>; + clk-rate-conf-div-min =3D <1>; + clk-rate-conf-div-max =3D <1024>; + clk-rate-calc-method =3D <1>; + clk-rate-reg-offset =3D <0x30>; + clk-rate-reg-mul-value-shift =3D <0>; + clk-rate-reg-mul-value-mask =3D <0>; + clk-rate-reg-div-value-shift =3D <3>; + clk-rate-reg-div-value-mask =3D <0x3FF>; + clk-rate-reg-write-enable-bit =3D <31>; + + /* gate */ + clk-gate-reg-offset =3D <0x24>; + clk-gate-reg-bit-enable =3D <26>; + clk-gate-reg-bit-reverse =3D <0>; + }; + + gpio_dbclk: gpio_dbclk { + #clock-cells =3D <0>; + compatible =3D "canaan,k230-clk-composite"; + clocks =3D <&osc24m>; + status =3D "okay"; + read-only =3D <0>; + + /* rate */ + clk-rate-conf-mul-min =3D <1>; + clk-rate-conf-mul-max =3D <1>; + clk-rate-conf-div-min =3D <1>; + clk-rate-conf-div-max =3D <1024>; + clk-rate-calc-method =3D <1>; + clk-rate-reg-offset =3D <0x30>; + clk-rate-reg-mul-value-shift =3D <0>; + clk-rate-reg-mul-value-mask =3D <0>; + clk-rate-reg-div-value-shift =3D <13>; + clk-rate-reg-div-value-mask =3D <0x3FF>; + clk-rate-reg-write-enable-bit =3D <31>; + + /* gate */ + clk-gate-reg-offset =3D <0x24>; + clk-gate-reg-bit-enable =3D <27>; + clk-gate-reg-bit-reverse =3D <0>; + }; + + sysctl_pclk: sysctl_pclk { + #clock-cells =3D <0>; + compatible =3D "fixed-clock"; + clock-frequency =3D <100000000>; + clock-accuracy =3D <0>; + status =3D "okay"; + read-only =3D <0>; + }; + wdt0_pclk_gate: wdt0_pclk_gate { + #clock-cells =3D <0>; + compatible =3D "canaan,k230-clk-composite"; + clocks =3D <&sysctl_pclk>; + status =3D "okay"; + read-only =3D <0>; + + /* gate */ + clk-gate-reg-offset =3D <0x50>; + clk-gate-reg-bit-enable =3D <1>; + clk-gate-reg-bit-reverse =3D <0>; + }; + wdt1_pclk_gate: wdt1_pclk_gate { + #clock-cells =3D <0>; + compatible =3D "canaan,k230-clk-composite"; + clocks =3D <&sysctl_pclk>; + status =3D "okay"; + read-only =3D <0>; + + /* gate */ + clk-gate-reg-offset =3D <0x50>; + clk-gate-reg-bit-enable =3D <2>; + clk-gate-reg-bit-reverse =3D <0>; + }; + timer_pclk_gate: timer_pclk_gate { + #clock-cells =3D <0>; + compatible =3D "canaan,k230-clk-composite"; + clocks =3D <&sysctl_pclk>; + status =3D "okay"; + read-only =3D <0>; + + /* gate */ + clk-gate-reg-offset =3D <0x50>; + clk-gate-reg-bit-enable =3D <3>; + clk-gate-reg-bit-reverse =3D <0>; + }; + iomux_pclk_gate: iomux_pclk_gate { + #clock-cells =3D <0>; + compatible =3D "canaan,k230-clk-composite"; + clocks =3D <&sysctl_pclk>; + status =3D "okay"; + read-only =3D <0>; + + /* gate */ + clk-gate-reg-offset =3D <0x50>; + clk-gate-reg-bit-enable =3D <20>; + clk-gate-reg-bit-reverse =3D <0>; + }; + mailbox_pclk_gate: mailbox_pclk_gate { + #clock-cells =3D <0>; + compatible =3D "canaan,k230-clk-composite"; + clocks =3D <&sysctl_pclk>; + status =3D "okay"; + read-only =3D <0>; + + /* gate */ + clk-gate-reg-offset =3D <0x50>; + clk-gate-reg-bit-enable =3D <4>; + clk-gate-reg-bit-reverse =3D <0>; + }; + + hdi_clk: hdi_clk { + #clock-cells =3D <0>; + compatible =3D "canaan,k230-clk-composite"; + clocks =3D <&pll0_div4>; + status =3D "okay"; + read-only =3D <0>; + + /* rate */ + clk-rate-conf-mul-min =3D <1>; + clk-rate-conf-mul-max =3D <1>; + clk-rate-conf-div-min =3D <1>; + clk-rate-conf-div-max =3D <8>; + clk-rate-calc-method =3D <1>; + clk-rate-reg-offset =3D <0x58>; + clk-rate-reg-mul-value-shift =3D <0>; + clk-rate-reg-mul-value-mask =3D <0>; + clk-rate-reg-div-value-shift =3D <28>; + clk-rate-reg-div-value-mask =3D <0x7>; + clk-rate-reg-write-enable-bit =3D <31>; + + /* gate */ + clk-gate-reg-offset =3D <0x50>; + clk-gate-reg-bit-enable =3D <21>; + clk-gate-reg-bit-reverse =3D <0>; + }; + + stc_clk: stc_clk { + #clock-cells =3D <0>; + compatible =3D "canaan,k230-clk-composite"; + clocks =3D <&pll1_div4>; + status =3D "okay"; + read-only =3D <0>; + + /* rate */ + clk-rate-conf-mul-min =3D <1>; + clk-rate-conf-mul-max =3D <1>; + clk-rate-conf-div-min =3D <1>; + clk-rate-conf-div-max =3D <32>; + clk-rate-calc-method =3D <1>; + clk-rate-reg-offset =3D <0x58>; + clk-rate-reg-mul-value-shift =3D <0>; + clk-rate-reg-mul-value-mask =3D <0>; + clk-rate-reg-div-value-shift =3D <15>; + clk-rate-reg-div-value-mask =3D <0x1F>; + clk-rate-reg-write-enable-bit =3D <31>; + + /* gate */ + clk-gate-reg-offset =3D <0x50>; + clk-gate-reg-bit-enable =3D <19>; + clk-gate-reg-bit-reverse =3D <0>; + }; + + ts_clk: ts_clk { + #clock-cells =3D <0>; + compatible =3D "canaan,k230-clk-composite"; + clocks =3D <&osc24m>; + status =3D "okay"; + read-only =3D <0>; + + /* rate */ + clk-rate-conf-mul-min =3D <1>; + clk-rate-conf-mul-max =3D <1>; + clk-rate-conf-div-min =3D <1>; + clk-rate-conf-div-max =3D <256>; + clk-rate-calc-method =3D <1>; + clk-rate-reg-offset =3D <0x58>; + clk-rate-reg-mul-value-shift =3D <0>; + clk-rate-reg-mul-value-mask =3D <0>; + clk-rate-reg-div-value-shift =3D <20>; + clk-rate-reg-div-value-mask =3D <0xFF>; + clk-rate-reg-write-enable-bit =3D <31>; + }; + + wdt0: wdt0 { + #clock-cells =3D <0>; + compatible =3D "canaan,k230-clk-composite"; + clocks =3D <&osc24m>; + status =3D "okay"; + read-only =3D <0>; + + /* rate */ + clk-rate-conf-mul-min =3D <1>; + clk-rate-conf-mul-max =3D <1>; + clk-rate-conf-div-min =3D <1>; + clk-rate-conf-div-max =3D <64>; + clk-rate-calc-method =3D <1>; + clk-rate-reg-offset =3D <0x58>; + clk-rate-reg-mul-value-shift =3D <0>; + clk-rate-reg-mul-value-mask =3D <0>; + clk-rate-reg-div-value-shift =3D <3>; + clk-rate-reg-div-value-mask =3D <0x3F>; + clk-rate-reg-write-enable-bit =3D <31>; + + /* gate */ + clk-gate-reg-offset =3D <0x50>; + clk-gate-reg-bit-enable =3D <5>; + clk-gate-reg-bit-reverse =3D <0>; + }; + + wdt1: wdt1 { + #clock-cells =3D <0>; + compatible =3D "canaan,k230-clk-composite"; + clocks =3D <&osc24m>; + status =3D "okay"; + read-only =3D <0>; + + /* rate */ + clk-rate-conf-mul-min =3D <1>; + clk-rate-conf-mul-max =3D <1>; + clk-rate-conf-div-min =3D <1>; + clk-rate-conf-div-max =3D <64>; + clk-rate-calc-method =3D <1>; + clk-rate-reg-offset =3D <0x58>; + clk-rate-reg-mul-value-shift =3D <0>; + clk-rate-reg-mul-value-mask =3D <0>; + clk-rate-reg-div-value-shift =3D <9>; + clk-rate-reg-div-value-mask =3D <0x3F>; + clk-rate-reg-write-enable-bit =3D <31>; + + /* gate */ + clk-gate-reg-offset =3D <0x50>; + clk-gate-reg-bit-enable =3D <6>; + clk-gate-reg-bit-reverse =3D <0>; + }; + + timerx_pulse_in: timerx_pulse_in { + #clock-cells =3D <0>; + compatible =3D "fixed-clock"; + clock-frequency =3D <50000000>; + clock-accuracy =3D <0>; + status =3D "okay"; + read-only =3D <0>; + }; + timer0_clk_src: timer0_clk_src { + #clock-cells =3D <0>; + compatible =3D "canaan,k230-clk-composite"; + clocks =3D <&pll0_div16>; + status =3D "okay"; + read-only =3D <0>; + + /* rate */ + clk-rate-conf-mul-min =3D <1>; + clk-rate-conf-mul-max =3D <1>; + clk-rate-conf-div-min =3D <1>; + clk-rate-conf-div-max =3D <8>; + clk-rate-calc-method =3D <1>; + clk-rate-reg-offset =3D <0x54>; + clk-rate-reg-mul-value-shift =3D <0>; + clk-rate-reg-mul-value-mask =3D <0>; + clk-rate-reg-div-value-shift =3D <0>; + clk-rate-reg-div-value-mask =3D <0x7>; + clk-rate-reg-write-enable-bit =3D <31>; + }; + timer0_clk: timer0_clk { + #clock-cells =3D <0>; + compatible =3D "canaan,k230-clk-composite"; + status =3D "okay"; + read-only =3D <0>; + + /* parents */ + clocks =3D <&timer0_clk_src>, <&timerx_pulse_in>; + clk-parent-reg-offset =3D <0x50>; + clk-parent-reg-value-shift =3D <7>; + clk-parent-reg-value-mask =3D <0x1>; + + /* gate */ + clk-gate-reg-offset =3D <0x50>; + clk-gate-reg-bit-enable =3D <13>; + clk-gate-reg-bit-reverse =3D <0>; + }; + + timer1_clk_src: timer1_clk_src { + #clock-cells =3D <0>; + compatible =3D "canaan,k230-clk-composite"; + clocks =3D <&pll0_div16>; + status =3D "okay"; + read-only =3D <0>; + + /* rate */ + clk-rate-conf-mul-min =3D <1>; + clk-rate-conf-mul-max =3D <1>; + clk-rate-conf-div-min =3D <1>; + clk-rate-conf-div-max =3D <8>; + clk-rate-calc-method =3D <1>; + clk-rate-reg-offset =3D <0x54>; + clk-rate-reg-mul-value-shift =3D <0>; + clk-rate-reg-mul-value-mask =3D <0>; + clk-rate-reg-div-value-shift =3D <3>; + clk-rate-reg-div-value-mask =3D <0x7>; + clk-rate-reg-write-enable-bit =3D <31>; + }; + timer1_clk: timer1_clk { + #clock-cells =3D <0>; + compatible =3D "canaan,k230-clk-composite"; + status =3D "okay"; + read-only =3D <0>; + + /* parents */ + clocks =3D <&timer1_clk_src>, <&timerx_pulse_in>; + clk-parent-reg-offset =3D <0x50>; + clk-parent-reg-value-shift =3D <8>; + clk-parent-reg-value-mask =3D <0x1>; + + /* gate */ + clk-gate-reg-offset =3D <0x50>; + clk-gate-reg-bit-enable =3D <14>; + clk-gate-reg-bit-reverse =3D <0>; + }; + + timer2_clk_src: timer2_clk_src { + #clock-cells =3D <0>; + compatible =3D "canaan,k230-clk-composite"; + clocks =3D <&pll0_div16>; + status =3D "okay"; + read-only =3D <0>; + + /* rate */ + clk-rate-conf-mul-min =3D <1>; + clk-rate-conf-mul-max =3D <1>; + clk-rate-conf-div-min =3D <1>; + clk-rate-conf-div-max =3D <8>; + clk-rate-calc-method =3D <1>; + clk-rate-reg-offset =3D <0x54>; + clk-rate-reg-mul-value-shift =3D <0>; + clk-rate-reg-mul-value-mask =3D <0>; + clk-rate-reg-div-value-shift =3D <6>; + clk-rate-reg-div-value-mask =3D <0x7>; + clk-rate-reg-write-enable-bit =3D <31>; + }; + timer2_clk: timer2_clk { + #clock-cells =3D <0>; + compatible =3D "canaan,k230-clk-composite"; + status =3D "okay"; + read-only =3D <0>; + + /* parents */ + clocks =3D <&timer2_clk_src>, <&timerx_pulse_in>; + clk-parent-reg-offset =3D <0x50>; + clk-parent-reg-value-shift =3D <9>; + clk-parent-reg-value-mask =3D <0x1>; + + /* gate */ + clk-gate-reg-offset =3D <0x50>; + clk-gate-reg-bit-enable =3D <15>; + clk-gate-reg-bit-reverse =3D <0>; + }; + + timer3_clk_src: timer3_clk_src { + #clock-cells =3D <0>; + compatible =3D "canaan,k230-clk-composite"; + clocks =3D <&pll0_div16>; + status =3D "okay"; + read-only =3D <0>; + + /* rate */ + clk-rate-conf-mul-min =3D <1>; + clk-rate-conf-mul-max =3D <1>; + clk-rate-conf-div-min =3D <1>; + clk-rate-conf-div-max =3D <8>; + clk-rate-calc-method =3D <1>; + clk-rate-reg-offset =3D <0x54>; + clk-rate-reg-mul-value-shift =3D <0>; + clk-rate-reg-mul-value-mask =3D <0>; + clk-rate-reg-div-value-shift =3D <9>; + clk-rate-reg-div-value-mask =3D <0x7>; + clk-rate-reg-write-enable-bit =3D <31>; + }; + timer3_clk: timer3_clk { + #clock-cells =3D <0>; + compatible =3D "canaan,k230-clk-composite"; + status =3D "okay"; + read-only =3D <0>; + + /* parents */ + clocks =3D <&timer3_clk_src>, <&timerx_pulse_in>; + clk-parent-reg-offset =3D <0x50>; + clk-parent-reg-value-shift =3D <10>; + clk-parent-reg-value-mask =3D <0x1>; + + /* gate */ + clk-gate-reg-offset =3D <0x50>; + clk-gate-reg-bit-enable =3D <16>; + clk-gate-reg-bit-reverse =3D <0>; + }; + + timer4_clk_src: timer4_clk_src { + #clock-cells =3D <0>; + compatible =3D "canaan,k230-clk-composite"; + clocks =3D <&pll0_div16>; + status =3D "okay"; + read-only =3D <0>; + + /* rate */ + clk-rate-conf-mul-min =3D <1>; + clk-rate-conf-mul-max =3D <1>; + clk-rate-conf-div-min =3D <1>; + clk-rate-conf-div-max =3D <8>; + clk-rate-calc-method =3D <1>; + clk-rate-reg-offset =3D <0x54>; + clk-rate-reg-mul-value-shift =3D <0>; + clk-rate-reg-mul-value-mask =3D <0>; + clk-rate-reg-div-value-shift =3D <12>; + clk-rate-reg-div-value-mask =3D <0x7>; + clk-rate-reg-write-enable-bit =3D <31>; + }; + timer4_clk: timer4_clk { + #clock-cells =3D <0>; + compatible =3D "canaan,k230-clk-composite"; + status =3D "okay"; + read-only =3D <0>; + + /* parents */ + clocks =3D <&timer4_clk_src>, <&timerx_pulse_in>; + clk-parent-reg-offset =3D <0x50>; + clk-parent-reg-value-shift =3D <11>; + clk-parent-reg-value-mask =3D <0x1>; + + /* gate */ + clk-gate-reg-offset =3D <0x50>; + clk-gate-reg-bit-enable =3D <17>; + clk-gate-reg-bit-reverse =3D <0>; + }; + + timer5_clk_src: timer5_clk_src { + #clock-cells =3D <0>; + compatible =3D "canaan,k230-clk-composite"; + clocks =3D <&pll0_div16>; + status =3D "okay"; + read-only =3D <0>; + + /* rate */ + clk-rate-conf-mul-min =3D <1>; + clk-rate-conf-mul-max =3D <1>; + clk-rate-conf-div-min =3D <1>; + clk-rate-conf-div-max =3D <8>; + clk-rate-calc-method =3D <1>; + clk-rate-reg-offset =3D <0x54>; + clk-rate-reg-mul-value-shift =3D <0>; + clk-rate-reg-mul-value-mask =3D <0>; + clk-rate-reg-div-value-shift =3D <15>; + clk-rate-reg-div-value-mask =3D <0x7>; + clk-rate-reg-write-enable-bit =3D <31>; + }; + timer5_clk: timer5_clk { + #clock-cells =3D <0>; + compatible =3D "canaan,k230-clk-composite"; + status =3D "okay"; + read-only =3D <0>; + + /* parents */ + clocks =3D <&timer5_clk_src>, <&timerx_pulse_in>; + clk-parent-reg-offset =3D <0x50>; + clk-parent-reg-value-shift =3D <12>; + clk-parent-reg-value-mask =3D <0x1>; + + /* gate */ + clk-gate-reg-offset =3D <0x50>; + clk-gate-reg-bit-enable =3D <18>; + clk-gate-reg-bit-reverse =3D <0>; + }; + + shrm_src: shrm_src { + #clock-cells =3D <0>; + compatible =3D "canaan,k230-clk-composite"; + status =3D "okay"; + read-only =3D <0>; + + /* parents */ + clocks =3D <&pll0_div2>, <&pll3_div2>; + clk-parent-reg-offset =3D <0x5C>; + clk-parent-reg-value-shift =3D <14>; + clk-parent-reg-value-mask =3D <0x1>; + + /* gate */ + clk-gate-reg-offset =3D <0x5C>; + clk-gate-reg-bit-enable =3D <10>; + clk-gate-reg-bit-reverse =3D <0>; + }; + shrm_div2: shrm_div2 { + #clock-cells =3D <0>; + compatible =3D "fixed-factor-clock"; + clocks =3D <&shrm_src>; + clock-div =3D <2>; + clock-mult =3D <1>; + status =3D "okay"; + read-only =3D <0>; + }; + shrm_axis_clk_gate: shrm_axis_clk_gate { + #clock-cells =3D <0>; + compatible =3D "canaan,k230-clk-composite"; + clocks =3D <&shrm_div2>; + status =3D "okay"; + read-only =3D <0>; + + /* gate */ + clk-gate-reg-offset =3D <0x5C>; + clk-gate-reg-bit-enable =3D <11>; + clk-gate-reg-bit-reverse =3D <0>; + }; + decompress_aclk_gate: decompress_aclk_gate { + #clock-cells =3D <0>; + compatible =3D "canaan,k230-clk-composite"; + clocks =3D <&shrm_src>; + status =3D "okay"; + read-only =3D <0>; + + /* gate */ + clk-gate-reg-offset =3D <0x5C>; + clk-gate-reg-bit-enable =3D <7>; + clk-gate-reg-bit-reverse =3D <0>; + }; + + shrm_pclk: shrm_pclk { + #clock-cells =3D <0>; + compatible =3D "canaan,k230-clk-composite"; + clocks =3D <&pll0_div4>; + status =3D "okay"; + read-only =3D <0>; + + /* rate */ + clk-rate-conf-mul-min =3D <1>; + clk-rate-conf-mul-max =3D <1>; + clk-rate-conf-div-min =3D <1>; + clk-rate-conf-div-max =3D <8>; + clk-rate-calc-method =3D <1>; + clk-rate-reg-offset =3D <0x5C>; + clk-rate-reg-mul-value-shift =3D <0>; + clk-rate-reg-mul-value-mask =3D <0>; + clk-rate-reg-div-value-shift =3D <18>; + clk-rate-reg-div-value-mask =3D <0x7>; + clk-rate-reg-write-enable-bit =3D <31>; + + /* gate */ + clk-gate-reg-offset =3D <0x5C>; + clk-gate-reg-bit-enable =3D <0>; + clk-gate-reg-bit-reverse =3D <0>; + }; + + shrm_axim_clk_gate: shrm_axim_clk_gate { + #clock-cells =3D <0>; + compatible =3D "canaan,k230-clk-composite"; + clocks =3D <&pll0_div4>; + status =3D "okay"; + read-only =3D <0>; + + /* gate */ + clk-gate-reg-offset =3D <0x5C>; + clk-gate-reg-bit-enable =3D <12>; + clk-gate-reg-bit-reverse =3D <0>; + }; + + gsdma_aclk_gate: gsdma_aclk_gate { + #clock-cells =3D <0>; + compatible =3D "canaan,k230-clk-composite"; + clocks =3D <&shrm_axim_clk_gate>; + status =3D "okay"; + read-only =3D <0>; + + /* gate */ + clk-gate-reg-offset =3D <0x5C>; + clk-gate-reg-bit-enable =3D <5>; + clk-gate-reg-bit-reverse =3D <0>; + }; + + nonai2d_aclk_gate: nonai2d_aclk_gate { + #clock-cells =3D <0>; + compatible =3D "canaan,k230-clk-composite"; + clocks =3D <&shrm_axim_clk_gate>; + status =3D "okay"; + read-only =3D <0>; + + /* gate */ + clk-gate-reg-offset =3D <0x5C>; + clk-gate-reg-bit-enable =3D <9>; + clk-gate-reg-bit-reverse =3D <0>; + }; + + pdma_aclk_gate: pdma_aclk_gate { + #clock-cells =3D <0>; + compatible =3D "canaan,k230-clk-composite"; + clocks =3D <&shrm_axim_clk_gate>; + status =3D "okay"; + read-only =3D <0>; + + /* gate */ + clk-gate-reg-offset =3D <0x5C>; + clk-gate-reg-bit-enable =3D <3>; + clk-gate-reg-bit-reverse =3D <0>; + }; + + ddrc_core_clk: ddrc_core_clk { + #clock-cells =3D <0>; + compatible =3D "canaan,k230-clk-composite"; + status =3D "okay"; + read-only =3D <0>; + + /* parents */ + clocks =3D <&pll0_div2>, <&pll0_div3>, <&pll2_div4>; + clk-parent-reg-offset =3D <0x60>; + clk-parent-reg-value-shift =3D <0>; + clk-parent-reg-value-mask =3D <0x3>; + + /* rate */ + clk-rate-conf-mul-min =3D <1>; + clk-rate-conf-mul-max =3D <1>; + clk-rate-conf-div-min =3D <1>; + clk-rate-conf-div-max =3D <16>; + clk-rate-calc-method =3D <1>; + clk-rate-reg-offset =3D <0x60>; + clk-rate-reg-mul-value-shift =3D <0>; + clk-rate-reg-mul-value-mask =3D <0>; + clk-rate-reg-div-value-shift =3D <10>; + clk-rate-reg-div-value-mask =3D <0xF>; + clk-rate-reg-write-enable-bit =3D <31>; + + /* gate */ + clk-gate-reg-offset =3D <0x60>; + clk-gate-reg-bit-enable =3D <2>; + clk-gate-reg-bit-reverse =3D <0>; + }; + + ddrc_bypass_gate: ddrc_bypass_gate { + #clock-cells =3D <0>; + compatible =3D "canaan,k230-clk-composite"; + clocks =3D <&pll2_div4>; + status =3D "okay"; + read-only =3D <0>; + + /* gate */ + clk-gate-reg-offset =3D <0x60>; + clk-gate-reg-bit-enable =3D <8>; + clk-gate-reg-bit-reverse =3D <0>; + }; + + ddrc_pclk: ddrc_pclk { + #clock-cells =3D <0>; + compatible =3D "canaan,k230-clk-composite"; + clocks =3D <&pll0_div4>; + status =3D "okay"; + read-only =3D <0>; + + /* rate */ + clk-rate-conf-mul-min =3D <1>; + clk-rate-conf-mul-max =3D <1>; + clk-rate-conf-div-min =3D <1>; + clk-rate-conf-div-max =3D <16>; + clk-rate-calc-method =3D <1>; + clk-rate-reg-offset =3D <0x60>; + clk-rate-reg-mul-value-shift =3D <0>; + clk-rate-reg-mul-value-mask =3D <0>; + clk-rate-reg-div-value-shift =3D <14>; + clk-rate-reg-div-value-mask =3D <0xF>; + clk-rate-reg-write-enable-bit =3D <31>; + + /* gate */ + clk-gate-reg-offset =3D <0x60>; + clk-gate-reg-bit-enable =3D <9>; + clk-gate-reg-bit-reverse =3D <0>; + }; + + disp_hclk: disp_hclk { + #clock-cells =3D <0>; + compatible =3D "canaan,k230-clk-composite"; + clocks =3D <&pll0_div4>; + status =3D "okay"; + read-only =3D <0>; + + /* rate */ + clk-rate-conf-mul-min =3D <1>; + clk-rate-conf-mul-max =3D <1>; + clk-rate-conf-div-min =3D <1>; + clk-rate-conf-div-max =3D <8>; + clk-rate-calc-method =3D <1>; + clk-rate-reg-offset =3D <0x78>; + clk-rate-reg-mul-value-shift =3D <0>; + clk-rate-reg-mul-value-mask =3D <0>; + clk-rate-reg-div-value-shift =3D <0>; + clk-rate-reg-div-value-mask =3D <0x7>; + clk-rate-reg-write-enable-bit =3D <31>; + + /* gate */ + clk-gate-reg-offset =3D <0x74>; + clk-gate-reg-bit-enable =3D <0>; + clk-gate-reg-bit-reverse =3D <0>; + }; + + disp_aclk_gate: disp_aclk_gate { + #clock-cells =3D <0>; + compatible =3D "canaan,k230-clk-composite"; + clocks =3D <&pll0_div4>; + status =3D "okay"; + read-only =3D <0>; + + /* gate */ + clk-gate-reg-offset =3D <0x74>; + clk-gate-reg-bit-enable =3D <1>; + clk-gate-reg-bit-reverse =3D <0>; + }; + + disp_clkext: disp_clkext { + #clock-cells =3D <0>; + compatible =3D "canaan,k230-clk-composite"; + clocks =3D <&pll0_div3>; + status =3D "okay"; + read-only =3D <0>; + + /* rate */ + clk-rate-conf-mul-min =3D <1>; + clk-rate-conf-mul-max =3D <1>; + clk-rate-conf-div-min =3D <1>; + clk-rate-conf-div-max =3D <16>; + clk-rate-calc-method =3D <1>; + clk-rate-reg-offset =3D <0x78>; + clk-rate-reg-mul-value-shift =3D <0>; + clk-rate-reg-mul-value-mask =3D <0>; + clk-rate-reg-div-value-shift =3D <16>; + clk-rate-reg-div-value-mask =3D <0xF>; + clk-rate-reg-write-enable-bit =3D <31>; + + /* gate */ + clk-gate-reg-offset =3D <0x74>; + clk-gate-reg-bit-enable =3D <5>; + clk-gate-reg-bit-reverse =3D <0>; + }; + + disp_gpu: disp_gpu { + #clock-cells =3D <0>; + compatible =3D "canaan,k230-clk-composite"; + clocks =3D <&pll0_div3>; + status =3D "okay"; + read-only =3D <0>; + + /* rate */ + clk-rate-conf-mul-min =3D <1>; + clk-rate-conf-mul-max =3D <1>; + clk-rate-conf-div-min =3D <1>; + clk-rate-conf-div-max =3D <16>; + clk-rate-calc-method =3D <1>; + clk-rate-reg-offset =3D <0x78>; + clk-rate-reg-mul-value-shift =3D <0>; + clk-rate-reg-mul-value-mask =3D <0>; + clk-rate-reg-div-value-shift =3D <20>; + clk-rate-reg-div-value-mask =3D <0xF>; + clk-rate-reg-write-enable-bit =3D <31>; + + /* gate */ + clk-gate-reg-offset =3D <0x74>; + clk-gate-reg-bit-enable =3D <6>; + clk-gate-reg-bit-reverse =3D <0>; + }; + + dpipclk: dpipclk { + #clock-cells =3D <0>; + compatible =3D "canaan,k230-clk-composite"; + clocks =3D <&pll1_div4>; + status =3D "okay"; + read-only =3D <0>; + + /* rate */ + clk-rate-conf-mul-min =3D <1>; + clk-rate-conf-mul-max =3D <1>; + clk-rate-conf-div-min =3D <1>; + clk-rate-conf-div-max =3D <256>; + clk-rate-calc-method =3D <1>; + clk-rate-reg-offset =3D <0x78>; + clk-rate-reg-mul-value-shift =3D <0>; + clk-rate-reg-mul-value-mask =3D <0>; + clk-rate-reg-div-value-shift =3D <3>; + clk-rate-reg-div-value-mask =3D <0xFF>; + clk-rate-reg-write-enable-bit =3D <31>; + + /* gate */ + clk-gate-reg-offset =3D <0x74>; + clk-gate-reg-bit-enable =3D <2>; + clk-gate-reg-bit-reverse =3D <0>; + }; + + disp_cfgclk: disp_cfgclk { + #clock-cells =3D <0>; + compatible =3D "canaan,k230-clk-composite"; + clocks =3D <&pll1_div4>; + status =3D "okay"; + read-only =3D <0>; + + /* rate */ + clk-rate-conf-mul-min =3D <1>; + clk-rate-conf-mul-max =3D <1>; + clk-rate-conf-div-min =3D <1>; + clk-rate-conf-div-max =3D <32>; + clk-rate-calc-method =3D <1>; + clk-rate-reg-offset =3D <0x78>; + clk-rate-reg-mul-value-shift =3D <0>; + clk-rate-reg-mul-value-mask =3D <0>; + clk-rate-reg-div-value-shift =3D <11>; + clk-rate-reg-div-value-mask =3D <0x1F>; + clk-rate-reg-write-enable-bit =3D <31>; + + /* gate */ + clk-gate-reg-offset =3D <0x74>; + clk-gate-reg-bit-enable =3D <4>; + clk-gate-reg-bit-reverse =3D <0>; + }; + + disp_refclk_gate: disp_refclk_gate { + #clock-cells =3D <0>; + compatible =3D "canaan,k230-clk-composite"; + clocks =3D <&osc24m>; + status =3D "okay"; + read-only =3D <0>; + + /* gate */ + clk-gate-reg-offset =3D <0x74>; + clk-gate-reg-bit-enable =3D <3>; + clk-gate-reg-bit-reverse =3D <0>; + }; + + vpu_src: vpu_src { + #clock-cells =3D <0>; + compatible =3D "canaan,k230-clk-composite"; + clocks =3D <&pll0_div2>; + status =3D "okay"; + read-only =3D <0>; + + /* rate */ + clk-rate-conf-mul-min =3D <1>; + clk-rate-conf-mul-max =3D <16>; + clk-rate-conf-div-min =3D <16>; + clk-rate-conf-div-max =3D <16>; + clk-rate-calc-method =3D <0>; + clk-rate-reg-offset =3D <0xC>; + clk-rate-reg-mul-value-shift =3D <0>; + clk-rate-reg-mul-value-mask =3D <0>; + clk-rate-reg-div-value-shift =3D <1>; + clk-rate-reg-div-value-mask =3D <0xF>; + clk-rate-reg-write-enable-bit =3D <31>; + + /* gate */ + clk-gate-reg-offset =3D <0xC>; + clk-gate-reg-bit-enable =3D <0>; + clk-gate-reg-bit-reverse =3D <0>; + }; + + vpu_aclk_src: vpu_aclk_src { + #clock-cells =3D <0>; + compatible =3D "canaan,k230-clk-composite"; + clocks =3D <&vpu_src>; + status =3D "okay"; + read-only =3D <0>; + + /* rate */ + clk-rate-conf-mul-min =3D <1>; + clk-rate-conf-mul-max =3D <1>; + clk-rate-conf-div-min =3D <1>; + clk-rate-conf-div-max =3D <16>; + clk-rate-calc-method =3D <1>; + clk-rate-reg-offset =3D <0xC>; + clk-rate-reg-mul-value-shift =3D <0>; + clk-rate-reg-mul-value-mask =3D <0>; + clk-rate-reg-div-value-shift =3D <6>; + clk-rate-reg-div-value-mask =3D <0xF>; + clk-rate-reg-write-enable-bit =3D <31>; + }; + + vpu_aclk: vpu_aclk { + #clock-cells =3D <0>; + compatible =3D "canaan,k230-clk-composite"; + clocks =3D <&vpu_aclk_src>; + status =3D "okay"; + read-only =3D <0>; + + /* gate */ + clk-gate-reg-offset =3D <0xc>; + clk-gate-reg-bit-enable =3D <5>; + clk-gate-reg-bit-reverse =3D <0>; + }; + + vpu_ddrcp2: vpu_ddrcp2 { + #clock-cells =3D <0>; + compatible =3D "canaan,k230-clk-composite"; + clocks =3D <&vpu_aclk_src>; + status =3D "okay"; + read-only =3D <0>; + + /* gate */ + clk-gate-reg-offset =3D <0x60>; + clk-gate-reg-bit-enable =3D <5>; + clk-gate-reg-bit-reverse =3D <0>; + }; + + vpu_cfg: vpu_cfg { + #clock-cells =3D <0>; + compatible =3D "canaan,k230-clk-composite"; + clocks =3D <&pll0_div4>; + status =3D "okay"; + read-only =3D <0>; + + /* rate */ + clk-rate-conf-mul-min =3D <1>; + clk-rate-conf-mul-max =3D <1>; + clk-rate-conf-div-min =3D <1>; + clk-rate-conf-div-max =3D <16>; + clk-rate-calc-method =3D <1>; + clk-rate-reg-offset =3D <0xC>; + clk-rate-reg-mul-value-shift =3D <0>; + clk-rate-reg-mul-value-mask =3D <0>; + clk-rate-reg-div-value-shift =3D <11>; + clk-rate-reg-div-value-mask =3D <0xF>; + clk-rate-reg-write-enable-bit =3D <31>; + + /* gate */ + clk-gate-reg-offset =3D <0xC>; + clk-gate-reg-bit-enable =3D <10>; + clk-gate-reg-bit-reverse =3D <0>; + }; + + sec_pclk: sec_pclk { + #clock-cells =3D <0>; + compatible =3D "canaan,k230-clk-composite"; + clocks =3D <&pll0_div4>; + status =3D "okay"; + read-only =3D <0>; + + /* rate */ + clk-rate-conf-mul-min =3D <1>; + clk-rate-conf-mul-max =3D <1>; + clk-rate-conf-div-min =3D <1>; + clk-rate-conf-div-max =3D <8>; + clk-rate-calc-method =3D <1>; + clk-rate-reg-offset =3D <0x80>; + clk-rate-reg-mul-value-shift =3D <0>; + clk-rate-reg-mul-value-mask =3D <0>; + clk-rate-reg-div-value-shift =3D <1>; + clk-rate-reg-div-value-mask =3D <0x7>; + clk-rate-reg-write-enable-bit =3D <31>; + + /* gate */ + clk-gate-reg-offset =3D <0x80>; + clk-gate-reg-bit-enable =3D <0>; + clk-gate-reg-bit-reverse =3D <0>; + }; + sec_fixclk: sec_fixclk { + #clock-cells =3D <0>; + compatible =3D "canaan,k230-clk-composite"; + clocks =3D <&pll1_div4>; + status =3D "okay"; + read-only =3D <0>; + + /* rate */ + clk-rate-conf-mul-min =3D <1>; + clk-rate-conf-mul-max =3D <1>; + clk-rate-conf-div-min =3D <1>; + clk-rate-conf-div-max =3D <32>; + clk-rate-calc-method =3D <1>; + clk-rate-reg-offset =3D <0x80>; + clk-rate-reg-mul-value-shift =3D <0>; + clk-rate-reg-mul-value-mask =3D <0>; + clk-rate-reg-div-value-shift =3D <6>; + clk-rate-reg-div-value-mask =3D <0x1F>; + clk-rate-reg-write-enable-bit =3D <31>; + + /* gate */ + clk-gate-reg-offset =3D <0x80>; + clk-gate-reg-bit-enable =3D <5>; + clk-gate-reg-bit-reverse =3D <0>; + }; + + sec_aclk_gate: sec_aclk_gate { + #clock-cells =3D <0>; + compatible =3D "canaan,k230-clk-composite"; + clocks =3D <&pll1_div4>; + status =3D "okay"; + read-only =3D <0>; + + /* rate */ + clk-rate-conf-mul-min =3D <1>; + clk-rate-conf-mul-max =3D <1>; + clk-rate-conf-div-min =3D <1>; + clk-rate-conf-div-max =3D <8>; + clk-rate-calc-method =3D <1>; + clk-rate-reg-offset =3D <0x80>; + clk-rate-reg-mul-value-shift =3D <0>; + clk-rate-reg-mul-value-mask =3D <0>; + clk-rate-reg-div-value-shift =3D <11>; + clk-rate-reg-div-value-mask =3D <0x3>; + clk-rate-reg-write-enable-bit =3D <31>; + + /* gate */ + clk-gate-reg-offset =3D <0x80>; + clk-gate-reg-bit-enable =3D <4>; + clk-gate-reg-bit-reverse =3D <0>; + }; + + usb_clk480: usb_clk480 { + #clock-cells =3D <0>; + compatible =3D "canaan,k230-clk-composite"; + clocks =3D <&pll1>; + status =3D "okay"; + read-only =3D <0>; + + /* rate */ + clk-rate-conf-mul-min =3D <1>; + clk-rate-conf-mul-max =3D <1>; + clk-rate-conf-div-min =3D <1>; + clk-rate-conf-div-max =3D <8>; + clk-rate-calc-method =3D <1>; + clk-rate-reg-offset =3D <0x100>; + clk-rate-reg-mul-value-shift =3D <0>; + clk-rate-reg-mul-value-mask =3D <0>; + clk-rate-reg-div-value-shift =3D <1>; + clk-rate-reg-div-value-mask =3D <0x7>; + clk-rate-reg-write-enable-bit =3D <31>; + + /* gate */ + clk-gate-reg-offset =3D <0x100>; + clk-gate-reg-bit-enable =3D <0>; + clk-gate-reg-bit-reverse =3D <0>; + }; + + usb_clk100: usb_clk100 { + #clock-cells =3D <0>; + compatible =3D "canaan,k230-clk-composite"; + clocks =3D <&pll0_div4>; + status =3D "okay"; + read-only =3D <0>; + + /* rate */ + clk-rate-conf-mul-min =3D <1>; + clk-rate-conf-mul-max =3D <1>; + clk-rate-conf-div-min =3D <1>; + clk-rate-conf-div-max =3D <8>; + clk-rate-calc-method =3D <1>; + clk-rate-reg-offset =3D <0x100>; + clk-rate-reg-mul-value-shift =3D <0>; + clk-rate-reg-mul-value-mask =3D <0>; + clk-rate-reg-div-value-shift =3D <4>; + clk-rate-reg-div-value-mask =3D <0x7>; + clk-rate-reg-write-enable-bit =3D <31>; + + /* gate */ + clk-gate-reg-offset =3D <0x100>; + clk-gate-reg-bit-enable =3D <0>; + clk-gate-reg-bit-reverse =3D <0>; + }; + + dphy_test_clk: dphy_test_clk { + #clock-cells =3D <0>; + compatible =3D "canaan,k230-clk-composite"; + clocks =3D <&pll0>; + status =3D "okay"; + read-only =3D <0>; + + /* rate */ + clk-rate-conf-mul-min =3D <1>; + clk-rate-conf-mul-max =3D <1>; + clk-rate-conf-div-min =3D <1>; + clk-rate-conf-div-max =3D <16>; + clk-rate-calc-method =3D <1>; + clk-rate-reg-offset =3D <0x104>; + clk-rate-reg-mul-value-shift =3D <0>; + clk-rate-reg-mul-value-mask =3D <0>; + clk-rate-reg-div-value-shift =3D <1>; + clk-rate-reg-div-value-mask =3D <0xF>; + clk-rate-reg-write-enable-bit =3D <31>; + + /* gate */ + clk-gate-reg-offset =3D <0x104>; + clk-gate-reg-bit-enable =3D <0>; + clk-gate-reg-bit-reverse =3D <0>; + }; + + spi2axi_aclk: spi2axi_aclk { + #clock-cells =3D <0>; + compatible =3D "canaan,k230-clk-composite"; + clocks =3D <&pll0_div4>; + status =3D "okay"; + read-only =3D <0>; + + /* rate */ + clk-rate-conf-mul-min =3D <1>; + clk-rate-conf-mul-max =3D <1>; + clk-rate-conf-div-min =3D <1>; + clk-rate-conf-div-max =3D <8>; + clk-rate-calc-method =3D <1>; + clk-rate-reg-offset =3D <0x108>; + clk-rate-reg-mul-value-shift =3D <0>; + clk-rate-reg-mul-value-mask =3D <0>; + clk-rate-reg-div-value-shift =3D <1>; + clk-rate-reg-div-value-mask =3D <0x7>; + clk-rate-reg-write-enable-bit =3D <31>; + + /* gate */ + clk-gate-reg-offset =3D <0x108>; + clk-gate-reg-bit-enable =3D <0>; + clk-gate-reg-bit-reverse =3D <0>; + }; +}; --=20 2.52.0