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Signed-off-by: Mrinmay Sarkar --- .../bindings/pci/qcom,pcie-ep-sa8255p.yaml | 114 +++++++++++++++++= ++++ 1 file changed, 114 insertions(+) diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie-ep-sa8255p.yam= l b/Documentation/devicetree/bindings/pci/qcom,pcie-ep-sa8255p.yaml new file mode 100644 index 0000000000000000000000000000000000000000..970f65d46c8e2fa4c44665cb7a3= 46dea1dc9e06a --- /dev/null +++ b/Documentation/devicetree/bindings/pci/qcom,pcie-ep-sa8255p.yaml @@ -0,0 +1,114 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pci/qcom,pcie-ep-sa8255p.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm firmware managed PCIe Endpoint Controller + +description: + Qualcomm SA8255p SoC PCIe endpoint controller is based on the Synopsys + DesignWare PCIe IP which is managed by firmware. + +maintainers: + - Manivannan Sadhasivam + +properties: + compatible: + const: qcom,sa8255p-pcie-ep + + reg: + minItems: 6 + items: + - description: Qualcomm-specific PARF configuration registers + - description: DesignWare PCIe registers + - description: External local bus interface registers + - description: Address Translation Unit (ATU) registers + - description: Memory region used to map remote RC address space + - description: BAR memory region + - description: DMA register space + + reg-names: + minItems: 6 + items: + - const: parf + - const: dbi + - const: elbi + - const: atu + - const: addr_space + - const: mmio + - const: dma + + interrupts: + minItems: 2 + items: + - description: PCIe Global interrupt + - description: PCIe Doorbell interrupt + - description: DMA interrupt + + interrupt-names: + minItems: 2 + items: + - const: global + - const: doorbell + - const: dma + + iommus: + maxItems: 1 + + reset-gpios: + description: GPIO used as PERST# input signal + maxItems: 1 + + wake-gpios: + description: GPIO used as WAKE# output signal + maxItems: 1 + + power-domains: + maxItems: 1 + + dma-coherent: true + + num-lanes: + default: 2 + +required: + - compatible + - reg + - reg-names + - interrupts + - interrupt-names + - reset-gpios + - power-domains + +additionalProperties: false + +examples: + - | + #include + #include + soc { + #address-cells =3D <2>; + #size-cells =3D <2>; + pcie1_ep: pcie-ep@1c10000 { + compatible =3D "qcom,sa8255p-pcie-ep"; + reg =3D <0x0 0x01c10000 0x0 0x3000>, + <0x0 0x60000000 0x0 0xf20>, + <0x0 0x60000f20 0x0 0xa8>, + <0x0 0x60001000 0x0 0x4000>, + <0x0 0x60200000 0x0 0x100000>, + <0x0 0x01c13000 0x0 0x1000>, + <0x0 0x60005000 0x0 0x2000>; + reg-names =3D "parf", "dbi", "elbi", "atu", "addr_space", "mmi= o", "dma"; + interrupts =3D , + , + ; + interrupt-names =3D "global", "doorbell", "dma"; + reset-gpios =3D <&tlmm 4 GPIO_ACTIVE_LOW>; + wake-gpios =3D <&tlmm 5 GPIO_ACTIVE_LOW>; + dma-coherent; + iommus =3D <&pcie_smmu 0x80 0x7f>; + power-domains =3D <&scmi6_pd 1>; + num-lanes =3D <4>; + }; + }; --=20 2.25.1 From nobody Fri Dec 19 21:04:26 2025 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E34022F8BD0 for ; Wed, 3 Dec 2025 13:27:10 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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Wed, 03 Dec 2025 05:27:09 -0800 (PST) X-Google-Smtp-Source: AGHT+IGinZ8Y7e3RuxTljGQgsvfg/7CZa7++tyONDr9TSdQ1s6dL2fTMnrdfeiS7Jpe8xuUSDY0Kbg== X-Received: by 2002:a05:6a00:3d10:b0:7a9:d8a8:992a with SMTP id d2e1a72fcca58-7dd789c5f1emr6693630b3a.13.1764768428730; Wed, 03 Dec 2025 05:27:08 -0800 (PST) Received: from hu-msarkar-hyd.qualcomm.com ([202.46.23.25]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-7d15e6e6e06sm20287524b3a.43.2025.12.03.05.27.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 03 Dec 2025 05:27:08 -0800 (PST) From: Mrinmay Sarkar Date: Wed, 03 Dec 2025 18:56:48 +0530 Subject: [PATCH 2/2] PCI: qcom-ep: Add support for firmware-managed PCIe Endpoint Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251203-firmware_managed_ep-v1-2-295977600fa5@oss.qualcomm.com> References: <20251203-firmware_managed_ep-v1-0-295977600fa5@oss.qualcomm.com> In-Reply-To: <20251203-firmware_managed_ep-v1-0-295977600fa5@oss.qualcomm.com> To: Bjorn Helgaas , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , Manivannan Sadhasivam , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Philipp Zabel Cc: linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, kernel@oss.qualcomm.com, Manivannan Sadhasivam , Krishna Chaitanya Chundru , quic_vbadigan@quicinc.com, quic_shazhuss@quicinc.com, konrad.dybcio@oss.qualcomm.com, Mrinmay sarkar , Rama Krishna , Ayiluri Naga Rashmi , Nitesh Gupta X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; 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In these cases, the Linux driver should not perform resource enable or disable operations directly. Additionally, runtime PM support has been enabled to ensure proper power state transitions. This commit introduces a `firmware_managed` flag in the Endpoint configuration structure. When set, the driver skips resource handling and uses generic runtime PM calls to let firmware do resource management. A new compatible string is added for SA8255P platforms where firmware manages resources. Signed-off-by: Mrinmay Sarkar --- drivers/pci/controller/dwc/pcie-qcom-ep.c | 80 ++++++++++++++++++++++++---= ---- 1 file changed, 64 insertions(+), 16 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-qcom-ep.c b/drivers/pci/contro= ller/dwc/pcie-qcom-ep.c index f1bc0ac81a928b928ab3f8cc7bf82558fc430474..38358c9fa7ab32fd36efcea0a42= c52f1f86a523a 100644 --- a/drivers/pci/controller/dwc/pcie-qcom-ep.c +++ b/drivers/pci/controller/dwc/pcie-qcom-ep.c @@ -168,11 +168,13 @@ enum qcom_pcie_ep_link_status { * @hdma_support: HDMA support on this SoC * @override_no_snoop: Override NO_SNOOP attribute in TLP to enable cache = snooping * @disable_mhi_ram_parity_check: Disable MHI RAM data parity error check + * @firmware_managed: Set if the Endpoint controller is firmware managed */ struct qcom_pcie_ep_cfg { bool hdma_support; bool override_no_snoop; bool disable_mhi_ram_parity_check; + bool firmware_managed; }; =20 /** @@ -377,6 +379,15 @@ static int qcom_pcie_enable_resources(struct qcom_pcie= _ep *pcie_ep) =20 static void qcom_pcie_disable_resources(struct qcom_pcie_ep *pcie_ep) { + struct device *dev =3D pcie_ep->pci.dev; + int ret; + + ret =3D pm_runtime_put_sync(dev); + if (ret < 0) { + dev_err(dev, "Failed to disable endpoint device: %d\n", ret); + return; + } + icc_set_bw(pcie_ep->icc_mem, 0, 0); phy_power_off(pcie_ep->phy); phy_exit(pcie_ep->phy); @@ -390,12 +401,22 @@ static int qcom_pcie_perst_deassert(struct dw_pcie *p= ci) u32 val, offset; int ret; =20 - ret =3D qcom_pcie_enable_resources(pcie_ep); - if (ret) { - dev_err(dev, "Failed to enable resources: %d\n", ret); + ret =3D pm_runtime_get_sync(dev); + if (ret < 0) { + dev_err(dev, "Failed to enable endpoint device: %d\n", ret); return ret; } =20 + /* Enable resources if Endpoint controller is not firmware-managed */ + if (!(pcie_ep->cfg && pcie_ep->cfg->firmware_managed)) { + ret =3D qcom_pcie_enable_resources(pcie_ep); + if (ret) { + dev_err(dev, "Failed to enable resources: %d\n", ret); + pm_runtime_put_sync(dev); + return ret; + } + } + /* Perform cleanup that requires refclk */ pci_epc_deinit_notify(pci->ep.epc); dw_pcie_ep_cleanup(&pci->ep); @@ -630,16 +651,6 @@ static int qcom_pcie_ep_get_resources(struct platform_= device *pdev, return ret; } =20 - pcie_ep->num_clks =3D devm_clk_bulk_get_all(dev, &pcie_ep->clks); - if (pcie_ep->num_clks < 0) { - dev_err(dev, "Failed to get clocks\n"); - return pcie_ep->num_clks; - } - - pcie_ep->core_reset =3D devm_reset_control_get_exclusive(dev, "core"); - if (IS_ERR(pcie_ep->core_reset)) - return PTR_ERR(pcie_ep->core_reset); - pcie_ep->reset =3D devm_gpiod_get(dev, "reset", GPIOD_IN); if (IS_ERR(pcie_ep->reset)) return PTR_ERR(pcie_ep->reset); @@ -652,9 +663,22 @@ static int qcom_pcie_ep_get_resources(struct platform_= device *pdev, if (IS_ERR(pcie_ep->phy)) ret =3D PTR_ERR(pcie_ep->phy); =20 - pcie_ep->icc_mem =3D devm_of_icc_get(dev, "pcie-mem"); - if (IS_ERR(pcie_ep->icc_mem)) - ret =3D PTR_ERR(pcie_ep->icc_mem); + /* Populate resources if Endpoint controller is not firmware-managed */ + if (!(pcie_ep->cfg && pcie_ep->cfg->firmware_managed)) { + pcie_ep->num_clks =3D devm_clk_bulk_get_all(dev, &pcie_ep->clks); + if (pcie_ep->num_clks < 0) { + dev_err(dev, "Failed to get clocks\n"); + return pcie_ep->num_clks; + } + + pcie_ep->core_reset =3D devm_reset_control_get_exclusive(dev, "core"); + if (IS_ERR(pcie_ep->core_reset)) + return PTR_ERR(pcie_ep->core_reset); + + pcie_ep->icc_mem =3D devm_of_icc_get(dev, "pcie-mem"); + if (IS_ERR(pcie_ep->icc_mem)) + ret =3D PTR_ERR(pcie_ep->icc_mem); + } =20 return ret; } @@ -874,6 +898,16 @@ static int qcom_pcie_ep_probe(struct platform_device *= pdev) =20 platform_set_drvdata(pdev, pcie_ep); =20 + pm_runtime_set_active(dev); + ret =3D devm_pm_runtime_enable(dev); + if (ret) + return ret; + ret =3D pm_runtime_get_sync(dev); + if (ret < 0) { + dev_err(dev, "Failed to enable endpoint device: %d\n", ret); + return ret; + } + ret =3D qcom_pcie_ep_get_resources(pdev, pcie_ep); if (ret) return ret; @@ -897,6 +931,12 @@ static int qcom_pcie_ep_probe(struct platform_device *= pdev) pcie_ep->debugfs =3D debugfs_create_dir(name, NULL); qcom_pcie_ep_init_debugfs(pcie_ep); =20 + ret =3D pm_runtime_put_sync(dev); + if (ret < 0) { + dev_err(dev, "Failed to disable endpoint device: %d\n", ret); + goto err_disable_irqs; + } + return 0; =20 err_disable_irqs: @@ -930,7 +970,15 @@ static const struct qcom_pcie_ep_cfg cfg_1_34_0 =3D { .disable_mhi_ram_parity_check =3D true, }; =20 +static const struct qcom_pcie_ep_cfg cfg_1_34_0_fw_managed =3D { + .hdma_support =3D true, + .override_no_snoop =3D true, + .disable_mhi_ram_parity_check =3D true, + .firmware_managed =3D true, +}; + static const struct of_device_id qcom_pcie_ep_match[] =3D { + { .compatible =3D "qcom,sa8255p-pcie-ep", .data =3D &cfg_1_34_0_fw_manage= d}, { .compatible =3D "qcom,sa8775p-pcie-ep", .data =3D &cfg_1_34_0}, { .compatible =3D "qcom,sdx55-pcie-ep", }, { .compatible =3D "qcom,sm8450-pcie-ep", }, --=20 2.25.1