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However, the code incorrectly assigned pp->msg_atu_index =3D i without incrementing i first, causing the MSG TLP region to reuse the last configured outbound window instead of the next available one. This can cause issue with IO transfers as this can over write iATU configured for IO memory. Fix this by incrementing i before assigning it to msg_atu_index so that the MSG TLP region uses a dedicated iATU entry. Fixes: e1a4ec1a9520 ("PCI: dwc: Add generic MSG TLP support for sending PME= _Turn_Off when system suspend") Cc: stable@vger.kernel.org Signed-off-by: Krishna Chaitanya Chundru Reviewed-by: Frank Li Tested-by: Maciej W. Rozycki --- drivers/pci/controller/dwc/pcie-designware-host.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pc= i/controller/dwc/pcie-designware-host.c index e92513c5bda51bde3a7157033ddbd73afa370d78..4fb6331fbc2b322c1a1b6a8e4fe= 08f92e170da19 100644 --- a/drivers/pci/controller/dwc/pcie-designware-host.c +++ b/drivers/pci/controller/dwc/pcie-designware-host.c @@ -942,7 +942,7 @@ static int dw_pcie_iatu_setup(struct dw_pcie_rp *pp) dev_warn(pci->dev, "Ranges exceed outbound iATU size (%d)\n", pci->num_ob_windows); =20 - pp->msg_atu_index =3D i; + pp->msg_atu_index =3D ++i; =20 i =3D 0; resource_list_for_each_entry(entry, &pp->bridge->dma_ranges) { --=20 2.34.1 From nobody Fri Dec 19 20:58:22 2025 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BC120299937 for ; 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This left IO and MEM outbound windows unprogrammed, resulting in broken IO transactions. Additionally, dw_pcie_config_ecam_iatu() was only called during host initialization, so ECAM-related iATU entries were not restored after suspend/resume, leading to failures in configuration space access To resolve these issues, the ECAM iATU configuration is moved into dw_pcie_setup_rc(). At the same time, dw_pcie_iatu_setup() is invoked when ECAM is enabled. Rename msg_atu_index to ob_atu_index to track the next available outbound iATU index for ECAM and MSG TLP windows. Furthermore, an error check is added in dw_pcie_prog_outbound_atu() to avoid programming beyond num_ob_windows. Fixes: f6fd357f7afb ("PCI: dwc: Prepare the driver for enabling ECAM mechan= ism using iATU 'CFG Shift Feature'") Reported-by: Maciej W. Rozycki Closes: https://lore.kernel.org/all/alpine.DEB.2.21.2511280256260.36486@ang= ie.orcam.me.uk/ Signed-off-by: Krishna Chaitanya Chundru Tested-by: Maciej W. Rozycki --- drivers/pci/controller/dwc/pcie-designware-host.c | 37 ++++++++++++++-----= ---- drivers/pci/controller/dwc/pcie-designware.c | 3 ++ drivers/pci/controller/dwc/pcie-designware.h | 2 +- 3 files changed, 26 insertions(+), 16 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pc= i/controller/dwc/pcie-designware-host.c index 4fb6331fbc2b322c1a1b6a8e4fe08f92e170da19..22c6ec7bff8840d935803f0b967= 49413b1c3f905 100644 --- a/drivers/pci/controller/dwc/pcie-designware-host.c +++ b/drivers/pci/controller/dwc/pcie-designware-host.c @@ -433,7 +433,7 @@ static int dw_pcie_config_ecam_iatu(struct dw_pcie_rp *= pp) * Immediate bus under Root Bus, needs type 0 iATU configuration and * remaining buses need type 1 iATU configuration. */ - atu.index =3D 0; + atu.index =3D pp->ob_atu_index; atu.type =3D PCIE_ATU_TYPE_CFG0; atu.parent_bus_addr =3D pp->cfg0_base + SZ_1M; /* 1MiB is to cover 1 (bus) * 32 (devices) * 8 (functions) */ @@ -443,6 +443,8 @@ static int dw_pcie_config_ecam_iatu(struct dw_pcie_rp *= pp) if (ret) return ret; =20 + pp->ob_atu_index++; + bus_range_max =3D resource_size(bus->res); =20 if (bus_range_max < 2) @@ -455,7 +457,11 @@ static int dw_pcie_config_ecam_iatu(struct dw_pcie_rp = *pp) atu.size =3D (SZ_1M * bus_range_max) - SZ_2M; atu.ctrl2 =3D PCIE_ATU_CFG_SHIFT_MODE_ENABLE; =20 - return dw_pcie_prog_outbound_atu(pci, &atu); + ret =3D dw_pcie_prog_outbound_atu(pci, &atu); + if (!ret) + pp->ob_atu_index++; + + return ret; } =20 static int dw_pcie_create_ecam_window(struct dw_pcie_rp *pp, struct resour= ce *res) @@ -630,14 +636,6 @@ int dw_pcie_host_init(struct dw_pcie_rp *pp) if (ret) goto err_free_msi; =20 - if (pp->ecam_enabled) { - ret =3D dw_pcie_config_ecam_iatu(pp); - if (ret) { - dev_err(dev, "Failed to configure iATU in ECAM mode\n"); - goto err_free_msi; - } - } - /* * Allocate the resource for MSG TLP before programming the iATU * outbound window in dw_pcie_setup_rc(). Since the allocation depends @@ -942,7 +940,7 @@ static int dw_pcie_iatu_setup(struct dw_pcie_rp *pp) dev_warn(pci->dev, "Ranges exceed outbound iATU size (%d)\n", pci->num_ob_windows); =20 - pp->msg_atu_index =3D ++i; + pp->ob_atu_index =3D ++i; =20 i =3D 0; resource_list_for_each_entry(entry, &pp->bridge->dma_ranges) { @@ -1084,14 +1082,23 @@ int dw_pcie_setup_rc(struct dw_pcie_rp *pp) /* * If the platform provides its own child bus config accesses, it means * the platform uses its own address translation component rather than - * ATU, so we should not program the ATU here. + * ATU, so we should not program the ATU here. If ECAM is enabled, config + * space access goes through ATU, so setup ATU here. */ - if (pp->bridge->child_ops =3D=3D &dw_child_pcie_ops) { + if (pp->bridge->child_ops =3D=3D &dw_child_pcie_ops || pp->ecam_enabled) { ret =3D dw_pcie_iatu_setup(pp); if (ret) return ret; } =20 + if (pp->ecam_enabled) { + ret =3D dw_pcie_config_ecam_iatu(pp); + if (ret) { + dev_err(pci->dev, "Failed to configure iATU in ECAM mode\n"); + return ret; + } + } + dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_0, 0); =20 /* Program correct class for RC */ @@ -1113,7 +1120,7 @@ static int dw_pcie_pme_turn_off(struct dw_pcie *pci) void __iomem *mem; int ret; =20 - if (pci->num_ob_windows <=3D pci->pp.msg_atu_index) + if (pci->num_ob_windows <=3D pci->pp.ob_atu_index) return -ENOSPC; =20 if (!pci->pp.msg_res) @@ -1123,7 +1130,7 @@ static int dw_pcie_pme_turn_off(struct dw_pcie *pci) atu.routing =3D PCIE_MSG_TYPE_R_BC; atu.type =3D PCIE_ATU_TYPE_MSG; atu.size =3D resource_size(pci->pp.msg_res); - atu.index =3D pci->pp.msg_atu_index; + atu.index =3D pci->pp.ob_atu_index; =20 atu.parent_bus_addr =3D pci->pp.msg_res->start - pci->parent_bus_offset; =20 diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/con= troller/dwc/pcie-designware.c index c644216995f69cbf065e61a0392bf1e5e32cf56e..f9f3c2f3532e0d0e9f8e4f42d8c= 5c9db68d55272 100644 --- a/drivers/pci/controller/dwc/pcie-designware.c +++ b/drivers/pci/controller/dwc/pcie-designware.c @@ -476,6 +476,9 @@ int dw_pcie_prog_outbound_atu(struct dw_pcie *pci, u32 retries, val; u64 limit_addr; =20 + if (atu->index > pci->num_ob_windows) + return -ENOSPC; + limit_addr =3D parent_bus_addr + atu->size - 1; =20 if ((limit_addr & ~pci->region_limit) !=3D (parent_bus_addr & ~pci->regio= n_limit) || diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/con= troller/dwc/pcie-designware.h index e995f692a1ecd10130d3be3358827f801811387f..69d0bd8b3c57353763f98999e5d= 39527861fe1a7 100644 --- a/drivers/pci/controller/dwc/pcie-designware.h +++ b/drivers/pci/controller/dwc/pcie-designware.h @@ -423,8 +423,8 @@ struct dw_pcie_rp { struct pci_host_bridge *bridge; raw_spinlock_t lock; DECLARE_BITMAP(msi_irq_in_use, MAX_MSI_IRQS); + int ob_atu_index; bool use_atu_msg; - int msg_atu_index; struct resource *msg_res; bool use_linkup_irq; struct pci_eq_presets presets; --=20 2.34.1