From nobody Fri Dec 19 21:17:25 2025 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 582902F83C3; Wed, 3 Dec 2025 13:59:40 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.251.105.195 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764770382; cv=none; b=s8r+UMfOqhCiNBBaRIgQllVMMeD2eT3LDi6N2h9Nno4toZCYoBe4vuN2+m6QFw9516Sk6f4FWMhIOm88MGKmYTll4RGiJdcr6BgaYds3PVTXYxhxNdUfuUXljLoaAlbKUXXF2dqsYOcA/JDsMTXGeoTRPHeHWT9O/Ld8SctcZWY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764770382; c=relaxed/simple; bh=Coa8HH2Y80U+8oDJEeTZktMM2J7wD1YAwBHcYUfHBB8=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=fSjnsRdCqJKBghs+W/rAh3kUG6wRMR7rrVfHjJwp3zakvq+/aurtHOfeINkFupbdmorm3vhyUFo63gzxofnlT18qixbE5HCG8LNKSEpMqPHaB7r8keq86I8GTcYCDIE5vsnhP6+T+7+bAW2K13NB8ZBdWEYqsMdOLwvp0WLS8Yg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com; spf=pass smtp.mailfrom=collabora.com; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b=KpmnDXL7; arc=none smtp.client-ip=148.251.105.195 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=collabora.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b="KpmnDXL7" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1764770378; bh=Coa8HH2Y80U+8oDJEeTZktMM2J7wD1YAwBHcYUfHBB8=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=KpmnDXL7Oy0frt5g96fb4XsIU0VNv2JEJk+Mz9zETt3l5ZdyuXGAQFZ8njVdXA8Vs ABRLoMLd4bjzqrukfipOqP96qmy/PIzYJvTt9nBMxJyURTmYtRUV0HSPVgXpVs4zmE 9Mcv61a+Yh0guVw/G8snxj7itv190JRVji/59Ml09pBvbxJfk/Kkz9zBeWgoKsYkzf wlv8fcxvilSF6XLVjwaSdW08H0gCYw55iLF6bsPPqNFRuiDyNHcTOECZtoGwYTrQ74 NvJ6h+Ry/ivq1GvDCgcnOeK7YwTxBoeDauWNvkr88vn6KOnzNzIpFFIQOPHrf0qxGF 5uwKwgFt5Iizg== Received: from yukiji.home (amontpellier-657-1-116-247.w83-113.abo.wanadoo.fr [83.113.51.247]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: laeyraud) by bali.collaboradmins.com (Postfix) with ESMTPSA id CB0E917E0330; Wed, 3 Dec 2025 14:59:37 +0100 (CET) From: Louis-Alexis Eyraud Date: Wed, 03 Dec 2025 14:59:26 +0100 Subject: [PATCH 1/4] dt-bindings: serial: mediatek,uart: Add compatible for MT8189 SoC Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251203-add-mediatek-genio-520-720-evk-v1-1-df794b2a30ae@collabora.com> References: <20251203-add-mediatek-genio-520-720-evk-v1-0-df794b2a30ae@collabora.com> In-Reply-To: <20251203-add-mediatek-genio-520-720-evk-v1-0-df794b2a30ae@collabora.com> To: Greg Kroah-Hartman , Jiri Slaby , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Sean Wang Cc: kernel@collabora.com, linux-kernel@vger.kernel.org, linux-serial@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, Louis-Alexis Eyraud X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1764770376; l=995; i=louisalexis.eyraud@collabora.com; s=20250113; h=from:subject:message-id; bh=Coa8HH2Y80U+8oDJEeTZktMM2J7wD1YAwBHcYUfHBB8=; b=Y5mQykRO/xlACP/ELaAg9N2ySD3XHV5tyS3bTSZsebFcO5XddKxaH5zW6fA+n5tekkPqfDTaq a3LpGtHPgTVAoTnSGq89TU0B58HRMoJmSfz5AhwHH01EiOHcsClyTCi X-Developer-Key: i=louisalexis.eyraud@collabora.com; a=ed25519; pk=CHFBDB2Kqh4EHc6JIqFn69GhxJJAzc0Zr4e8QxtumuM= Add a compatible string for the MT8189 SoC. The UART IPs in this chip are fully compatible with the one found in MT6577 SoC. Signed-off-by: Louis-Alexis Eyraud Acked-by: Krzysztof Kozlowski Reviewed-by Macpaul Lin --- Documentation/devicetree/bindings/serial/mediatek,uart.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/serial/mediatek,uart.yaml b/= Documentation/devicetree/bindings/serial/mediatek,uart.yaml index 5bd8a8853ae0d4ae309d28350fd54b6f9b4e731e..3f0f4aea0a4c0ef11055ddd08ba= 71d045e7fa519 100644 --- a/Documentation/devicetree/bindings/serial/mediatek,uart.yaml +++ b/Documentation/devicetree/bindings/serial/mediatek,uart.yaml @@ -47,6 +47,7 @@ properties: - mediatek,mt8183-uart - mediatek,mt8186-uart - mediatek,mt8188-uart + - mediatek,mt8189-uart - mediatek,mt8192-uart - mediatek,mt8195-uart - mediatek,mt8365-uart --=20 2.52.0 From nobody Fri Dec 19 21:17:25 2025 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E4FC62F8BC5; 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Wed, 3 Dec 2025 14:59:38 +0100 (CET) From: Louis-Alexis Eyraud Date: Wed, 03 Dec 2025 14:59:27 +0100 Subject: [PATCH 2/4] dt-bindings: arm: mediatek: add compatibles for Mediatek Genio 520/720-EVK boards Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251203-add-mediatek-genio-520-720-evk-v1-2-df794b2a30ae@collabora.com> References: <20251203-add-mediatek-genio-520-720-evk-v1-0-df794b2a30ae@collabora.com> In-Reply-To: <20251203-add-mediatek-genio-520-720-evk-v1-0-df794b2a30ae@collabora.com> To: Greg Kroah-Hartman , Jiri Slaby , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Sean Wang Cc: kernel@collabora.com, linux-kernel@vger.kernel.org, linux-serial@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, Louis-Alexis Eyraud X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1764770376; l=1484; i=louisalexis.eyraud@collabora.com; s=20250113; h=from:subject:message-id; bh=7hzRBQrL67XVTnHZ8d374O2SexVHFXVB/Bjw6Nbx9nw=; b=Ls128W34lagmawLiu3VvhhIoqo2YDImPp7hy4hg1vqBrmNCg/1wbpxuamUV8qJKShVKi5k+eO VRzxSWU8J9jDCfZORxpB+Clxft1mE1/I7I3SCDwiAM8AtL9TUsxKVKX X-Developer-Key: i=louisalexis.eyraud@collabora.com; a=ed25519; pk=CHFBDB2Kqh4EHc6JIqFn69GhxJJAzc0Zr4e8QxtumuM= Add compatible strings for the Mediatek Genio 520-EVK (based on MT8371 SoC) and Mediatek Genio 720-EVK (based on MT8391 SoC) boards. MT8391 and MT8371 SoC are less powerful variants of MT8189 SoC, with identical hardware register maps. Signed-off-by: Louis-Alexis Eyraud Acked-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/arm/mediatek.yaml | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/mediatek.yaml b/Document= ation/devicetree/bindings/arm/mediatek.yaml index 718d732174b9e3974b1a1bf827f48a347dae741f..9adb3c461796e2b176561db755d= 7d5131c8951d7 100644 --- a/Documentation/devicetree/bindings/arm/mediatek.yaml +++ b/Documentation/devicetree/bindings/arm/mediatek.yaml @@ -442,12 +442,22 @@ properties: - mediatek,mt8370-evk - const: mediatek,mt8370 - const: mediatek,mt8188 + - items: + - enum: + - mediatek,mt8371-evk + - const: mediatek,mt8371 + - const: mediatek,mt8189 - items: - enum: - grinn,genio-700-sbc - mediatek,mt8390-evk - const: mediatek,mt8390 - const: mediatek,mt8188 + - items: + - enum: + - mediatek,mt8391-evk + - const: mediatek,mt8391 + - const: mediatek,mt8189 - items: - enum: - kontron,3-5-sbc-i1200 --=20 2.52.0 From nobody Fri Dec 19 21:17:25 2025 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C2C4C2FB62A; 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Wed, 3 Dec 2025 14:59:39 +0100 (CET) From: Louis-Alexis Eyraud Date: Wed, 03 Dec 2025 14:59:28 +0100 Subject: [PATCH 3/4] arm64: dts: mediatek: add device-tree for Genio 720-EVK board Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251203-add-mediatek-genio-520-720-evk-v1-3-df794b2a30ae@collabora.com> References: <20251203-add-mediatek-genio-520-720-evk-v1-0-df794b2a30ae@collabora.com> In-Reply-To: <20251203-add-mediatek-genio-520-720-evk-v1-0-df794b2a30ae@collabora.com> To: Greg Kroah-Hartman , Jiri Slaby , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Sean Wang Cc: kernel@collabora.com, linux-kernel@vger.kernel.org, linux-serial@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, Louis-Alexis Eyraud X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1764770376; l=39232; i=louisalexis.eyraud@collabora.com; s=20250113; h=from:subject:message-id; bh=PGG/BBDoir47635rXyN/pOb1/Q58+J3wYynAC4uV1eM=; b=xy1hsraCcjZTSN8m7z7iTJZULgyg1EXKxIsLvPzocgbOs8B+DjpvPOuMH2Z5PsC3b2OknMbrl 8mDmWIpBtsNA7aq+Vayc0yReZ1d/9rv02uIpio04BSvReMMjRRVOARy X-Developer-Key: i=louisalexis.eyraud@collabora.com; a=ed25519; pk=CHFBDB2Kqh4EHc6JIqFn69GhxJJAzc0Zr4e8QxtumuM= Add support for MediaTek MT8189 SoC and its variants, and a device-tree for the basic hardware enablement of the Genio 720-EVK board, based on MT8391 SoC. MT8391 SoC is a variant of MT8189 SoC with a difference for the Arm Cortex-A78 CPU core maximum frequency (2.6 Ghz for MT8391, 3 Ghz for MT8189). MT8391 hardware register maps are identical to MT8189. The Genio 720-EVK board has following features: - MT8391 SoC - MT6365 PMIC - MT6319 Buck IC - MT6375 Charger IC - 8GB LPDDR5 RAM - 64GB eMMC 5.1 - 128GB UFS - 20V DC Jack - USB Type-C Power Adapter - Micro SD card slot - Push Button x 4 (Power, Reset, Download and Home Key) - LED x 3 (System Power, Reset, DC-IN Power) - USB Type-C Connector (USB 3.2) x 2 - USB Type-C Connector (USB 2.0) x 1 - 3.5mm Earphone Jack x 1 (with Microphone Input) - 3.5mm Line Out Audio Jack x 1 - Analog Microphone x 1 - Digital Microphone x 2 - Gigabit Ethernet with RJ45 connector - DP x 1 (Mode over USB Type-C) - LVDS port x 1 - eDP port x 1 - UART x2 with serial-to-usb converters and USB Type-C connectors - UART Port x 2 on Pin Header - M.2 Slot x 2 - I2C Capacitive Touch Pad - 4-Lane DSI x 1 - 4-Data Lane CSI x 2 - I2S Pin header - 40-Pin 2.54mm Pin Header x 1 - CAN Bus x 1 (RS232 Connector) Signed-off-by: Louis-Alexis Eyraud --- arch/arm64/boot/dts/mediatek/Makefile | 1 + arch/arm64/boot/dts/mediatek/mt8189.dtsi | 860 +++++++++++++++++= ++++ .../boot/dts/mediatek/mt8391-genio-720-evk.dts | 15 + .../boot/dts/mediatek/mt8391-genio-common.dtsi | 555 +++++++++++++ 4 files changed, 1431 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/Makefile b/arch/arm64/boot/dts/me= diatek/Makefile index c5fd6191a925ad8fcea401712f7a686e8b0a57c8..e3b63085c0608b86dc8638c9d5e= 0b73441e9ed7b 100644 --- a/arch/arm64/boot/dts/mediatek/Makefile +++ b/arch/arm64/boot/dts/mediatek/Makefile @@ -110,6 +110,7 @@ dtb-$(CONFIG_ARCH_MEDIATEK) +=3D mt8395-genio-1200-evk.= dtb dtb-$(CONFIG_ARCH_MEDIATEK) +=3D mt8395-genio-1200-evk-ufs.dtb dtb-$(CONFIG_ARCH_MEDIATEK) +=3D mt8390-genio-700-evk.dtb dtb-$(CONFIG_ARCH_MEDIATEK) +=3D mt8390-grinn-genio-700-sbc.dtb +dtb-$(CONFIG_ARCH_MEDIATEK) +=3D mt8391-genio-720-evk.dtb dtb-$(CONFIG_ARCH_MEDIATEK) +=3D mt8395-kontron-3-5-sbc-i1200.dtb dtb-$(CONFIG_ARCH_MEDIATEK) +=3D mt8395-radxa-nio-12l.dtb dtb-$(CONFIG_ARCH_MEDIATEK) +=3D mt8395-radxa-nio-12l-8-hd-panel.dtbo diff --git a/arch/arm64/boot/dts/mediatek/mt8189.dtsi b/arch/arm64/boot/dts= /mediatek/mt8189.dtsi new file mode 100644 index 0000000000000000000000000000000000000000..bf8a232bcaf10cdf4c590109aea= 68c9a3e82cc42 --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt8189.dtsi @@ -0,0 +1,860 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (c) 2025 MediaTek Inc. + * + * Copyright (c) 2025 Collabora Ltd. + * Author: Louis-Alexis Eyraud + */ + +#include +#include +#include + +/ { + compatible =3D "mediatek,mt8189"; + interrupt-parent =3D <&gic>; + #address-cells =3D <2>; + #size-cells =3D <2>; + + aliases { + i2c0 =3D &i2c0; + i2c1 =3D &i2c1; + i2c2 =3D &i2c2; + i2c3 =3D &i2c3; + i2c4 =3D &i2c4; + i2c5 =3D &i2c5; + i2c6 =3D &i2c6; + i2c7 =3D &i2c7; + i2c8 =3D &i2c8; + mmc0 =3D &mmc0; + mmc1 =3D &mmc1; + serial0 =3D &uart0; + }; + + clk32k: oscillator-clk32k { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <32000>; + clock-output-names =3D "clk32k"; + }; + + clk13m: oscillator-clk13m { + compatible =3D "fixed-factor-clock"; + #clock-cells =3D <0>; + clocks =3D <&clk26m>; + clock-mult =3D <1>; + clock-div =3D <2>; + clock-output-names =3D "clk13m"; + }; + + clk26m: oscillator-clk26m { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <26000000>; + clock-output-names =3D "clk26m"; + }; + + clk104m: oscillator-clk104m { + compatible =3D "fixed-factor-clock"; + #clock-cells =3D <0>; + clocks =3D <&clk26m>; + clock-mult =3D <4>; + clock-div =3D <1>; + clock-output-names =3D "clk104m"; + }; + + ulposc: oscillator-ulposc { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <520000000>; + clock-output-names =3D "ulposc"; + }; + + ulposc3: oscillator-ulposc3 { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <26000000>; + clock-output-names =3D "ulposc3"; + }; + + vowpll: oscillator-vowpll { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <26000000>; + clock-output-names =3D "vowpll"; + }; + + cpus { + #address-cells =3D <1>; + #size-cells =3D <0>; + + cpu0: cpu@0 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a55"; + reg =3D <0x000>; + enable-method =3D "psci"; + capacity-dmips-mhz =3D <282>; + cpu-idle-states =3D <&cpu_off_l>; + i-cache-size =3D <32768>; + i-cache-line-size =3D <64>; + i-cache-sets =3D <128>; + d-cache-size =3D <32768>; + d-cache-line-size =3D <64>; + d-cache-sets =3D <128>; + next-level-cache =3D <&l2_0>; + performance-domains =3D <&performance 0>; + #cooling-cells =3D <2>; + }; + + cpu1: cpu@100 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a55"; + reg =3D <0x100>; + enable-method =3D "psci"; + capacity-dmips-mhz =3D <282>; + cpu-idle-states =3D <&cpu_off_l>; + i-cache-size =3D <32768>; + i-cache-line-size =3D <64>; + i-cache-sets =3D <128>; + d-cache-size =3D <32768>; + d-cache-line-size =3D <64>; + d-cache-sets =3D <128>; + next-level-cache =3D <&l2_0>; + performance-domains =3D <&performance 0>; + #cooling-cells =3D <2>; + }; + + cpu2: cpu@200 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a55"; + reg =3D <0x200>; + enable-method =3D "psci"; + capacity-dmips-mhz =3D <282>; + cpu-idle-states =3D <&cpu_off_l>; + i-cache-size =3D <32768>; + i-cache-line-size =3D <64>; + i-cache-sets =3D <128>; + d-cache-size =3D <32768>; + d-cache-line-size =3D <64>; + d-cache-sets =3D <128>; + next-level-cache =3D <&l2_0>; + performance-domains =3D <&performance 0>; + #cooling-cells =3D <2>; + }; + + cpu3: cpu@300 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a55"; + reg =3D <0x300>; + enable-method =3D "psci"; + capacity-dmips-mhz =3D <282>; + cpu-idle-states =3D <&cpu_off_l>; + i-cache-size =3D <32768>; + i-cache-line-size =3D <64>; + i-cache-sets =3D <128>; + d-cache-size =3D <32768>; + d-cache-line-size =3D <64>; + d-cache-sets =3D <128>; + next-level-cache =3D <&l2_0>; + performance-domains =3D <&performance 0>; + #cooling-cells =3D <2>; + }; + + cpu4: cpu@400 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a55"; + reg =3D <0x400>; + enable-method =3D "psci"; + capacity-dmips-mhz =3D <282>; + cpu-idle-states =3D <&cpu_off_l>; + i-cache-size =3D <32768>; + i-cache-line-size =3D <64>; + i-cache-sets =3D <128>; + d-cache-size =3D <32768>; + d-cache-line-size =3D <64>; + d-cache-sets =3D <128>; + next-level-cache =3D <&l2_0>; + performance-domains =3D <&performance 0>; + #cooling-cells =3D <2>; + }; + + cpu5: cpu@500 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a55"; + reg =3D <0x500>; + enable-method =3D "psci"; + capacity-dmips-mhz =3D <282>; + cpu-idle-states =3D <&cpu_off_l>; + i-cache-size =3D <32768>; + i-cache-line-size =3D <64>; + i-cache-sets =3D <128>; + d-cache-size =3D <32768>; + d-cache-line-size =3D <64>; + d-cache-sets =3D <128>; + next-level-cache =3D <&l2_0>; + performance-domains =3D <&performance 0>; + #cooling-cells =3D <2>; + }; + + cpu6: cpu@600 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a78"; + reg =3D <0x600>; + enable-method =3D "psci"; + capacity-dmips-mhz =3D <1024>; + cpu-idle-states =3D <&cpu_off_b>; + i-cache-size =3D <65536>; + i-cache-line-size =3D <64>; + i-cache-sets =3D <256>; + d-cache-size =3D <65536>; + d-cache-line-size =3D <64>; + d-cache-sets =3D <256>; + next-level-cache =3D <&l2_1>; + performance-domains =3D <&performance 1>; + #cooling-cells =3D <2>; + }; + + cpu7: cpu@700 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a78"; + reg =3D <0x700>; + enable-method =3D "psci"; + capacity-dmips-mhz =3D <1024>; + cpu-idle-states =3D <&cpu_off_b>; + i-cache-size =3D <65536>; + i-cache-line-size =3D <64>; + i-cache-sets =3D <256>; + d-cache-size =3D <65536>; + d-cache-line-size =3D <64>; + d-cache-sets =3D <256>; + next-level-cache =3D <&l2_1>; + performance-domains =3D <&performance 1>; + #cooling-cells =3D <2>; + }; + + cpu-map { + cluster0 { + core0 { + cpu =3D <&cpu0>; + }; + + core1 { + cpu =3D <&cpu1>; + }; + + core2 { + cpu =3D <&cpu2>; + }; + + core3 { + cpu =3D <&cpu3>; + }; + + core4 { + cpu =3D <&cpu4>; + }; + + core5 { + cpu =3D <&cpu5>; + }; + + core6 { + cpu =3D <&cpu6>; + }; + + core7 { + cpu =3D <&cpu7>; + }; + }; + }; + + idle-states { + entry-method =3D "psci"; + + cpu_off_l: cpu-off-l { + compatible =3D "arm,idle-state"; + arm,psci-suspend-param =3D <0x00010000>; + local-timer-stop; + entry-latency-us =3D <25>; + exit-latency-us =3D <57>; + min-residency-us =3D <5700>; + }; + + cpu_off_b: cpu-off-b { + compatible =3D "arm,idle-state"; + arm,psci-suspend-param =3D <0x00010000>; + local-timer-stop; + entry-latency-us =3D <35>; + exit-latency-us =3D <82>; + min-residency-us =3D <1890>; + }; + }; + + l2_0: l2-cache0 { + compatible =3D "cache"; + cache-level =3D <2>; + cache-size =3D <131072>; + cache-line-size =3D <64>; + cache-sets =3D <512>; + next-level-cache =3D <&l3_0>; + cache-unified; + }; + + l2_1: l2-cache1 { + compatible =3D "cache"; + cache-level =3D <2>; + cache-size =3D <262144>; + cache-line-size =3D <64>; + cache-sets =3D <512>; + next-level-cache =3D <&l3_0>; + cache-unified; + }; + + l3_0: l3-cache { + compatible =3D "cache"; + cache-level =3D <3>; + cache-size =3D <1048576>; + cache-line-size =3D <64>; + cache-sets =3D <2048>; + cache-unified; + }; + }; + + memory: memory@40000000 { + device_type =3D "memory"; + /* This memory size is filled in by the bootloader */ + reg =3D <0 0x40000000 0 0>; + }; + + pmu-a55 { + compatible =3D "arm,cortex-a55-pmu"; + interrupt-parent =3D <&gic>; + interrupts =3D ; + }; + + pmu-a78 { + compatible =3D "arm,cortex-a78-pmu"; + interrupt-parent =3D <&gic>; + interrupts =3D ; + }; + + psci { + compatible =3D "arm,psci-1.0"; + method =3D "smc"; + }; + + soc { + compatible =3D "simple-bus"; + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + dma-ranges =3D <0x0 0x0 0x0 0x0 0x10 0x0>; + + performance: performance-controller@108d78 { + compatible =3D "mediatek,cpufreq-hw"; + reg =3D <0 0x00108d78 0 0x120>, <0 0x00108e98 0 0x120>; + #performance-domain-cells =3D <1>; + }; + + gic: interrupt-controller@c000000 { + compatible =3D "arm,gic-v3"; + reg =3D <0 0xc000000 0 0x40000>, /* distributor */ + <0 0xc040000 0 0x200000>; /* redistributor */ + interrupt-parent =3D <&gic>; + interrupts =3D ; + interrupt-controller; + #interrupt-cells =3D <4>; + #redistributor-regions =3D <1>; + + ppi-partitions { + ppi_cluster0: interrupt-partition-0 { + affinity =3D <&cpu0 &cpu1 &cpu2 &cpu3 &cpu4 &cpu5>; + }; + + ppi_cluster1: interrupt-partition-1 { + affinity =3D <&cpu6 &cpu7>; + }; + }; + }; + + auxadc: adc@11019000 { + compatible =3D "mediatek,mt8189-auxadc", "mediatek,mt8173-auxadc"; + reg =3D <0 0x11019000 0 0x1000>; + clocks =3D <&pericfg_ao_clk CLK_PERAO_AUXADC_26M>; + clock-names =3D "main"; + #io-channel-cells =3D <1>; + status =3D "disabled"; + }; + + clock-controller@1000c000 { + compatible =3D "mediatek,mt8189-apmixedsys", "syscon"; + reg =3D <0 0x1000c000 0 0x1000>; + #clock-cells =3D <1>; + }; + + clock-controller@1a000000 { + compatible =3D "mediatek,mt8189-camsys-main", "syscon"; + reg =3D <0 0x1a000000 0 0x1000>; + #clock-cells =3D <1>; + }; + + clock-controller@1a04f000 { + compatible =3D "mediatek,mt8189-camsys-rawa", "syscon"; + reg =3D <0 0x1a04f000 0 0x1000>; + #clock-cells =3D <1>; + }; + + clock-controller@1a06f000 { + compatible =3D "mediatek,mt8189-camsys-rawb", "syscon"; + reg =3D <0 0x1a06f000 0 0x1000>; + #clock-cells =3D <1>; + }; + + clock-controller@d01a000 { + compatible =3D "mediatek,mt8189-dbg-ao", "syscon"; + reg =3D <0 0xd01a000 0 0x1000>; + #clock-cells =3D <1>; + }; + + clock-controller@d0a0000 { + compatible =3D "mediatek,mt8189-dem", "syscon"; + reg =3D <0 0xd0a0000 0 0x1000>; + #clock-cells =3D <1>; + }; + + clock-controller@14000000 { + compatible =3D "mediatek,mt8189-dispsys", "syscon"; + reg =3D <0 0x14000000 0 0x1000>; + #clock-cells =3D <1>; + }; + + clock-controller@1c00f000 { + compatible =3D "mediatek,mt8189-dvfsrc-top", "syscon"; + reg =3D <0 0x1c00f000 0 0x1000>; + #clock-cells =3D <1>; + }; + + clock-controller@1e980000 { + compatible =3D "mediatek,mt8189-gce-d", "syscon"; + reg =3D <0 0x1e980000 0 0x1000>; + #clock-cells =3D <1>; + }; + + clock-controller@1e990000 { + compatible =3D "mediatek,mt8189-gce-m", "syscon"; + reg =3D <0 0x1e990000 0 0x1000>; + #clock-cells =3D <1>; + }; + + iic_wrap_e_clk: clock-controller@11c22e00 { + compatible =3D "mediatek,mt8189-iic-wrap-e", "syscon"; + reg =3D <0 0x11c22e00 0 0x10>; + #clock-cells =3D <1>; + }; + + iic_wrap_en_clk: clock-controller@11f32e00 { + compatible =3D "mediatek,mt8189-iic-wrap-en", "syscon"; + reg =3D <0 0x11f32e00 0 0x10>; + #clock-cells =3D <1>; + }; + + iic_wrap_s_clk: clock-controller@11d74e00 { + compatible =3D "mediatek,mt8189-iic-wrap-s", "syscon"; + reg =3D <0 0x11d74e00 0 0x10>; + #clock-cells =3D <1>; + }; + + iic_wrap_ws_clk: clock-controller@11b21e00 { + compatible =3D "mediatek,mt8189-iic-wrap-ws", "syscon"; + reg =3D <0 0x11b21e00 0 0x10>; + #clock-cells =3D <1>; + }; + + clock-controller@15020000 { + compatible =3D "mediatek,mt8189-imgsys1", "syscon"; + reg =3D <0 0x15020000 0 0x1000>; + #clock-cells =3D <1>; + }; + + clock-controller@15820000 { + compatible =3D "mediatek,mt8189-imgsys2", "syscon"; + reg =3D <0 0x15820000 0 0x1000>; + #clock-cells =3D <1>; + }; + + clock-controller@10001000 { + compatible =3D "mediatek,mt8189-infra-ao", "syscon"; + reg =3D <0 0x10001000 0 0x1000>; + #clock-cells =3D <1>; + }; + + clock-controller@1b000000 { + compatible =3D "mediatek,mt8189-ipesys", "syscon"; + reg =3D <0 0x1b000000 0 0x1000>; + #clock-cells =3D <1>; + }; + + clock-controller@1f000100 { + compatible =3D "mediatek,mt8189-mdpsys", "syscon"; + reg =3D <0 0x1f000100 0 0x20>; + #clock-cells =3D <1>; + }; + + clock-controller@13fbf000 { + compatible =3D "mediatek,mt8189-mfgcfg", "syscon"; + reg =3D <0 0x13fbf000 0 0x1000>; + #clock-cells =3D <1>; + }; + + clock-controller@1e800000 { + compatible =3D "mediatek,mt8189-mm-infra", "syscon"; + reg =3D <0 0x1e800000 0 0x1000>; + #clock-cells =3D <1>; + }; + + pericfg_ao_clk: clock-controller@11036000 { + compatible =3D "mediatek,mt8189-peri-ao", "syscon"; + reg =3D <0 0x11036000 0 0x1000>; + #clock-cells =3D <1>; + #reset-cells =3D <1>; + }; + + topckgen_clk: clock-controller@10000000 { + compatible =3D "mediatek,mt8189-topckgen", "syscon"; + reg =3D <0 0x10000000 0 0x1000>; + #clock-cells =3D <1>; + }; + + clock-controller@1c80ae10 { + compatible =3D "mediatek,mt8189-scp-i2c-clk", "syscon"; + reg =3D <0 0x1c80ae10 0 0x10>; + #clock-cells =3D <1>; + }; + + clock-controller@1cb21150 { + compatible =3D "mediatek,mt8189-scp-clk", "syscon"; + reg =3D <0 0x1cb21150 0 0x10>; + #clock-cells =3D <1>; + }; + + clock-controller@112b8000 { + compatible =3D "mediatek,mt8189-ufscfg-ao", "syscon"; + reg =3D <0 0x112b8000 0 0x1000>; + #clock-cells =3D <1>; + #reset-cells =3D <1>; + }; + + clock-controller@112bb000 { + compatible =3D "mediatek,mt8189-ufscfg-pdn", "syscon"; + reg =3D <0 0x112bb000 0 0x1000>; + #clock-cells =3D <1>; + #reset-cells =3D <1>; + }; + + clock-controller@1602f000 { + compatible =3D "mediatek,mt8189-vdec-core", "syscon"; + reg =3D <0 0x1602f000 0 0x1000>; + #clock-cells =3D <1>; + }; + + clock-controller@17000000 { + compatible =3D "mediatek,mt8189-venc", "syscon"; + reg =3D <0 0x17000000 0 0x1000>; + #clock-cells =3D <1>; + }; + + clock-controller@1c000800 { + compatible =3D "mediatek,mt8189-vlp-ao", "syscon"; + reg =3D <0 0x1c000800 0 0x10>; + #clock-cells =3D <1>; + }; + + vlpcfg_ao_clk: clock-controller@1c00c000 { + compatible =3D "mediatek,mt8189-vlpcfg-ao", "syscon"; + reg =3D <0 0x1c00c000 0 0x1000>; + #clock-cells =3D <1>; + }; + + vlpckgen_clk: clock-controller@1c012000 { + compatible =3D "mediatek,mt8189-vlpckgen", "syscon"; + reg =3D <0 0x1c012000 0 0x1000>; + #clock-cells =3D <1>; + }; + + efuse@11f10000 { + compatible =3D "mediatek,mt8189-efuse", "mediatek,mt8186-efuse"; + reg =3D <0 0x11f10000 0 0x1000>; + #address-cells =3D <1>; + #size-cells =3D <1>; + + socinfo-data1@7a0 { + reg =3D <0x7a0 0x4>; + }; + + socinfo-data2@7e0 { + reg =3D <0x7e0 0x4>; + }; + }; + + i2c0: i2c@11c20000 { + compatible =3D "mediatek,mt8189-i2c", "mediatek,mt8188-i2c"; + reg =3D <0 0x11c20000 0 0x1000>, + <0 0x11300200 0 0x80>; + clock-div =3D <1>; + #address-cells =3D <1>; + clocks =3D <&iic_wrap_e_clk CLK_IMPE_I2C0>, + <&pericfg_ao_clk CLK_PERAO_DMA_B>; + clock-names =3D "main", "dma"; + interrupts =3D ; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + i2c1: i2c@11c21000 { + compatible =3D "mediatek,mt8189-i2c", "mediatek,mt8188-i2c"; + reg =3D <0 0x11c21000 0 0x1000>, + <0 0x11300300 0 0x80>; + #address-cells =3D <1>; + clock-div =3D <1>; + clocks =3D <&iic_wrap_e_clk CLK_IMPE_I2C1>, + <&pericfg_ao_clk CLK_PERAO_DMA_B>; + clock-names =3D "main", "dma"; + interrupts =3D ; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + i2c2: i2c@11b20000 { + compatible =3D "mediatek,mt8189-i2c", "mediatek,mt8188-i2c"; + reg =3D <0 0x11b20000 0 0x1000>, + <0 0x11300400 0 0x80>; + #address-cells =3D <1>; + clock-div =3D <1>; + clocks =3D <&iic_wrap_ws_clk CLK_IMPWS_I2C2>, + <&pericfg_ao_clk CLK_PERAO_DMA_B>; + clock-names =3D "main", "dma"; + interrupts =3D ; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + i2c3: i2c@11d70000 { + compatible =3D "mediatek,mt8189-i2c", "mediatek,mt8188-i2c"; + reg =3D <0 0x11d70000 0 0x1000>, + <0 0x11300500 0 0x80>; + #address-cells =3D <1>; + clock-div =3D <1>; + clocks =3D <&iic_wrap_s_clk CLK_IMPS_I2C3>, + <&pericfg_ao_clk CLK_PERAO_DMA_B>; + clock-names =3D "main", "dma"; + interrupts =3D ; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + i2c4: i2c@11d71000 { + compatible =3D "mediatek,mt8189-i2c", "mediatek,mt8188-i2c"; + reg =3D <0 0x11d71000 0 0x1000>, + <0 0x11300600 0 0x80>; + #address-cells =3D <1>; + clock-div =3D <1>; + clocks =3D <&iic_wrap_s_clk CLK_IMPS_I2C4>, + <&pericfg_ao_clk CLK_PERAO_DMA_B>; + clock-names =3D "main", "dma"; + interrupts =3D ; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + i2c5: i2c@11d72000 { + compatible =3D "mediatek,mt8189-i2c", "mediatek,mt8188-i2c"; + reg =3D <0 0x11d72000 0 0x1000>, + <0 0x11300700 0 0x80>; + #address-cells =3D <1>; + clock-div =3D <1>; + clocks =3D <&iic_wrap_s_clk CLK_IMPS_I2C5>, + <&pericfg_ao_clk CLK_PERAO_DMA_B>; + clock-names =3D "main", "dma"; + interrupts =3D ; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + i2c6: i2c@11d73000 { + compatible =3D "mediatek,mt8189-i2c", "mediatek,mt8188-i2c"; + reg =3D <0 0x11d73000 0 0x1000>, + <0 0x11300800 0 0x80>; + #address-cells =3D <1>; + clock-div =3D <1>; + clocks =3D <&iic_wrap_s_clk CLK_IMPS_I2C6>, + <&pericfg_ao_clk CLK_PERAO_DMA_B>; + clock-names =3D "main", "dma"; + interrupts =3D ; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + i2c7: i2c@11f30000 { + compatible =3D "mediatek,mt8189-i2c", "mediatek,mt8188-i2c"; + reg =3D <0 0x11f30000 0 0x1000>, + <0 0x11300900 0 0x80>; + #address-cells =3D <1>; + clock-div =3D <1>; + clocks =3D <&iic_wrap_en_clk CLK_IMPEN_I2C7>, + <&pericfg_ao_clk CLK_PERAO_DMA_B>; + clock-names =3D "main", "dma"; + interrupts =3D ; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + i2c8: i2c@11f31000 { + compatible =3D "mediatek,mt8189-i2c", "mediatek,mt8188-i2c"; + reg =3D <0 0x11f31000 0 0x1000>, + <0 0x11300a00 0 0x80>; + #address-cells =3D <1>; + clock-div =3D <1>; + clocks =3D <&iic_wrap_en_clk CLK_IMPEN_I2C8>, + <&pericfg_ao_clk CLK_PERAO_DMA_B>; + clock-names =3D "main", "dma"; + interrupts =3D ; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + mmc0: mmc@11230000 { + compatible =3D "mediatek,mt8189-mmc"; + reg =3D <0 0x11230000 0 0x10000>, + <0 0x11e70000 0 0x1000>; + clocks =3D <&topckgen_clk CLK_TOP_MSDC50_0_SEL>, + <&pericfg_ao_clk CLK_PERAO_MSDC0_H>, + <&pericfg_ao_clk CLK_PERAO_MSDC0>; + clock-names =3D "source", "hclk", "source_cg"; + interrupts =3D ; + status =3D "disabled"; + }; + + mmc1: mmc@11240000 { + compatible =3D "mediatek,mt8189-mmc"; + reg =3D <0 0x11240000 0 0x1000>, + <0 0x11d80000 0 0x1000>; + clocks =3D <&topckgen_clk CLK_TOP_MSDC30_1_SEL>, + <&pericfg_ao_clk CLK_PERAO_MSDC1_H>, + <&pericfg_ao_clk CLK_PERAO_MSDC1>; + clock-names =3D "source", "hclk", "source_cg"; + interrupts =3D ; + status =3D "disabled"; + }; + + pio: pinctrl@10005000 { + compatible =3D "mediatek,mt8189-pinctrl"; + reg =3D <0 0x10005000 0 0x1000>, + <0 0x11b50000 0 0x1000>, + <0 0x11c50000 0 0x1000>, + <0 0x11c60000 0 0x1000>, + <0 0x11d20000 0 0x1000>, + <0 0x11d30000 0 0x1000>, + <0 0x11d40000 0 0x1000>, + <0 0x11e20000 0 0x1000>, + <0 0x11e30000 0 0x1000>, + <0 0x11f20000 0 0x1000>, + <0 0x11ce0000 0 0x1000>, + <0 0x11de0000 0 0x1000>, + <0 0x11e60000 0 0x1000>, + <0 0x1c01e000 0 0x1000>, + <0 0x11f00000 0 0x1000>; + reg-names =3D "base", "lm", "rb0", "rb1", "bm0", "bm1", + "bm2", "lt0", "lt1", "rt", "eint0", "eint1", + "eint2", "eint3", "eint4"; + gpio-controller; + #gpio-cells =3D <2>; + gpio-ranges =3D <&pio 0 0 182>; + interrupt-controller; + interrupts =3D ; + #interrupt-cells =3D <2>; + }; + + pwrap: pwrap@1cc04000 { + compatible =3D "mediatek,mt8189-pwrap", "mediatek,mt8195-pwrap", "sysco= n"; + reg =3D <0 0x1cc04000 0 0x1000>; + reg-names =3D "pwrap"; + assigned-clocks =3D <&vlpckgen_clk CLK_VLP_CK_PWRAP_ULPOSC_SEL>; + assigned-clock-parents =3D <&topckgen_clk CLK_TOP_OSC_D10>; + clocks =3D <&vlpcfg_ao_clk CLK_VLPCFG_REG_PMIF_SPMI_M_SYS>, + <&vlpcfg_ao_clk CLK_VLPCFG_REG_PMIF_SPMI_M_TMR>; + clock-names =3D "spi", "wrap"; + interrupts =3D ; + }; + + spmi: spmi@1cc06000 { + compatible =3D "mediatek,mt8189-spmi", "mediatek,mt8195-spmi"; + reg =3D <0 0x1cc06000 0 0x0008ff>, + <0 0x1cc00000 0 0x000100>; + reg-names =3D "pmif", "spmimst"; + clocks =3D <&vlpcfg_ao_clk CLK_VLPCFG_REG_PMIF_SPMI_P_SYS>, + <&vlpcfg_ao_clk CLK_VLPCFG_REG_PMIF_SPMI_P_TMR>, + <&vlpckgen_clk CLK_VLP_CK_SPMI_P_MST_SEL>; + clock-names =3D "pmif_sys_ck", "pmif_tmr_ck", "spmimst_clk_mux"; + #address-cells =3D <2>; + #size-cells =3D <0>; + }; + + timer@1cc10000 { + compatible =3D "mediatek,mt8189-timer", "mediatek,mt6765-timer"; + reg =3D <0 0x1cc10000 0 0x1000>; + clocks =3D <&clk13m>; + interrupts =3D ; + }; + + uart0: serial@11001000 { + compatible =3D "mediatek,mt8189-uart", "mediatek,mt6577-uart"; + reg =3D <0 0x11001000 0 0x1000>; + interrupts =3D ; + clocks =3D <&clk26m>, <&pericfg_ao_clk CLK_PERAO_UART0>; + clock-names =3D "baud", "bus"; + status =3D "disabled"; + }; + + uart1: serial@11002000 { + compatible =3D "mediatek,mt8189-uart", "mediatek,mt6577-uart"; + reg =3D <0 0x11002000 0 0x1000>; + interrupts =3D ; + clocks =3D <&clk26m>, <&pericfg_ao_clk CLK_PERAO_UART1>; + clock-names =3D "baud", "bus"; + status =3D "disabled"; + }; + + uart2: serial@11003000 { + compatible =3D "mediatek,mt8189-uart", "mediatek,mt6577-uart"; + reg =3D <0 0x11003000 0 0x1000>; + interrupts =3D ; + clocks =3D <&clk26m>, <&pericfg_ao_clk CLK_PERAO_UART2>; + clock-names =3D "baud", "bus"; + status =3D "disabled"; + }; + + uart3: serial@11004000 { + compatible =3D "mediatek,mt8189-uart", "mediatek,mt6577-uart"; + reg =3D <0 0x11004000 0 0x1000>; + interrupts =3D ; + clocks =3D <&clk26m>, <&pericfg_ao_clk CLK_PERAO_UART3>; + clock-names =3D "baud", "bus"; + status =3D "disabled"; + }; + + watchdog@1c00a000 { + compatible =3D "mediatek,mt8189-wdt", "mediatek,mt6589-wdt"; + reg =3D <0 0x1c00a000 0 0x100>; + #reset-cells =3D <1>; + }; + }; + + timer { + compatible =3D "arm,armv8-timer"; + interrupt-parent =3D <&gic>; + interrupts =3D , + , + , + ; + }; +}; diff --git a/arch/arm64/boot/dts/mediatek/mt8391-genio-720-evk.dts b/arch/a= rm64/boot/dts/mediatek/mt8391-genio-720-evk.dts new file mode 100644 index 0000000000000000000000000000000000000000..ddb6cdb95b04b2b732b24588b3e= a2ee023ddf884 --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt8391-genio-720-evk.dts @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (c) 2025 Collabora Ltd. + * Author: Louis-Alexis Eyraud + */ +/dts-v1/; + +#include "mt8189.dtsi" +#include "mt8391-genio-common.dtsi" + +/ { + model =3D "MediaTek Genio 720 EVK"; + compatible =3D "mediatek,mt8391-evk", "mediatek,mt8391", + "mediatek,mt8189"; +}; diff --git a/arch/arm64/boot/dts/mediatek/mt8391-genio-common.dtsi b/arch/a= rm64/boot/dts/mediatek/mt8391-genio-common.dtsi new file mode 100644 index 0000000000000000000000000000000000000000..744641916952111a4b389cf6adb= d27c429b6eff2 --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt8391-genio-common.dtsi @@ -0,0 +1,555 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (c) 2025 Collabora Ltd. + * Author: Louis-Alexis Eyraud + */ + +#include "mt6359.dtsi" + +#include +#include +#include +#include +#include "mt8189-pinfunc.h" + +/ { + aliases { + mmc0 =3D &mmc0; + serial0 =3D &uart0; + }; + + chosen: chosen { + stdout-path =3D "serial0:921600n8"; + }; + + reserved_memory: reserved-memory { + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + + /* 2 MiB reserved for ARM Trusted Firmware (BL31) */ + bl31_secmon_reserved: memory@54600000 { + reg =3D <0 0x54600000 0x0 0x200000>; + no-map; + }; + }; +}; + +&auxadc { + status =3D "okay"; +}; + +&cpu0 { + cpu-supply =3D <&mt6359_vmodem_buck_reg>; +}; + +&cpu1 { + cpu-supply =3D <&mt6359_vmodem_buck_reg>; +}; + +&cpu2 { + cpu-supply =3D <&mt6359_vmodem_buck_reg>; +}; + +&cpu3 { + cpu-supply =3D <&mt6359_vmodem_buck_reg>; +}; + +&cpu4 { + cpu-supply =3D <&mt6359_vmodem_buck_reg>; +}; + +&cpu5 { + cpu-supply =3D <&mt6359_vmodem_buck_reg>; +}; + +&cpu6 { + cpu-supply =3D <&mt6319_vbuck1>; +}; + +&cpu7 { + cpu-supply =3D <&mt6319_vbuck1>; +}; + +&i2c0 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&i2c0_pins>; + status =3D "okay"; +}; + +&i2c1 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&i2c1_pins>; + status =3D "okay"; +}; + +&i2c2 { + clock-frequency =3D <1000000>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&i2c2_pins>; + status =3D "okay"; +}; + +&i2c3 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&i2c3_pins>; + status =3D "disabled"; +}; + +&i2c4 { + clock-frequency =3D <400000>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&i2c4_pins>; + status =3D "okay"; +}; + +&i2c5 { + clock-frequency =3D <400000>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&i2c5_pins>; + status =3D "okay"; +}; + +&i2c6 { + clock-frequency =3D <400000>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&i2c6_pins>; + status =3D "okay"; +}; + +&i2c7 { + clock-frequency =3D <400000>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&i2c7_pins>; + status =3D "okay"; +}; + +&i2c8 { + clock-frequency =3D <400000>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&i2c8_pins>; + status =3D "okay"; +}; + +&mmc0 { + bus-width =3D <8>; + cap-mmc-highspeed; + cap-mmc-hw-reset; + hs400-ds-delay =3D <0x1481b>; + max-frequency =3D <200000000>; + mmc-hs200-1_8v; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; + no-sdio; + no-sd; + non-removable; + supports-cqe; + pinctrl-names =3D "default", "state_uhs"; + pinctrl-0 =3D <&mmc0_default_pins>; + pinctrl-1 =3D <&mmc0_uhs_pins>; + vmmc-supply =3D <&mt6359_vemc_1_ldo_reg>; + vqmmc-supply =3D <&mt6359_vufs_ldo_reg>; + status =3D "okay"; +}; + +&mmc1 { + bus-width =3D <4>; + cap-sd-highspeed; + cd-gpios =3D <&pio 2 GPIO_ACTIVE_HIGH>; + max-frequency =3D <200000000>; + no-mmc; + no-sdio; + sd-uhs-sdr50; + sd-uhs-sdr104; + pinctrl-names =3D "default", "state_uhs"; + pinctrl-0 =3D <&mmc1_default_pins>; + pinctrl-1 =3D <&mmc1_uhs_pins>; + vmmc-supply =3D <&mt6359_vpa_buck_reg>; + vqmmc-supply =3D <&mt6359_vsim1_ldo_reg>; + status =3D "okay"; +}; + +&mt6359_va09_ldo_reg{ + regulator-name =3D "dvdd_sram_vadsp"; + regulator-always-on; +}; + +&mt6359_vaux18_ldo_reg { + regulator-always-on; +}; + +&mt6359_vbbck_ldo_reg { + regulator-always-on; +}; + +&mt6359_vcore_buck_reg { + regulator-name =3D "dvdd_apu"; + regulator-always-on; +}; + +&mt6359_vgpu11_buck_reg { + regulator-name =3D "dvdd_sram_core"; + regulator-always-on; +}; + +&mt6359_vmodem_buck_reg { + regulator-name =3D "dvdd_proc_l"; + regulator-always-on; +}; + +&mt6359_vproc1_buck_reg { + regulator-name =3D "vgpu"; +}; + +&mt6359_vproc2_buck_reg { + regulator-name =3D "dvdd_core"; + regulator-always-on; +}; + +&mt6359_vpu_buck_reg { + regulator-name =3D "avdd075_emi"; + regulator-always-on; +}; + +&mt6359_vrf12_ldo_reg { + regulator-name =3D "va12_abb2"; + regulator-always-on; +}; + +&mt6359_vrfck_ldo_reg { + regulator-always-on; +}; + +&mt6359_vsram_md_ldo_reg { + regulator-name =3D "dvdd_sram_proc_l"; + regulator-always-on; +}; + +&mt6359_vsram_proc1_ldo_reg { + /delete-property/ regulator-always-on; + + regulator-name =3D "vsram_gpu"; +}; + +&mt6359_vsram_proc2_ldo_reg { + regulator-name =3D "dvdd_sram_proc_b"; + regulator-always-on; +}; + +&mt6359_vsram_others_ldo_reg { + regulator-name =3D "dvdd_sram_apu"; + regulator-always-on; +}; + +&mt6359_vufs_ldo_reg { + regulator-always-on; +}; + +&pio { + i2c0_pins: i2c0-pins { + pins { + pinmux =3D , + ; + bias-pull-up; + }; + }; + + i2c1_pins: i2c1-pins { + pins { + pinmux =3D , + ; + bias-pull-up; + }; + }; + + i2c2_pins: i2c2-pins { + pins { + pinmux =3D , + ; + bias-pull-up; + }; + }; + + i2c3_pins: i2c3-pins { + pins { + pinmux =3D , + ; + bias-pull-up; + }; + }; + + i2c4_pins: i2c4-pins { + pins { + pinmux =3D , + ; + bias-pull-up; + }; + }; + i2c5_pins: i2c5-pins { + pins { + pinmux =3D , + ; + bias-pull-up; + }; + }; + + i2c6_pins: i2c6-pins { + pins { + pinmux =3D , + ; + bias-pull-up; + }; + }; + + i2c7_pins: i2c7-pins { + pins { + pinmux =3D , + ; + bias-pull-up; + }; + }; + + i2c8_pins: i2c8-pins { + pins { + pinmux =3D , + ; + bias-pull-up; + }; + }; + + mmc0_default_pins: mmc0-default-pins { + pins-clk { + pinmux =3D ; + drive-strength =3D <6>; + bias-pull-down =3D ; + }; + + pins-cmd-dat { + pinmux =3D , + , + , + , + , + , + , + , + ; + input-enable; + drive-strength =3D <6>; + bias-pull-up =3D ; + }; + + pins-rst { + pinmux =3D ; + drive-strength =3D <6>; + bias-pull-up =3D ; + }; + }; + + mmc0_uhs_pins: mmc0-uhs-pins { + pins-clk { + pinmux =3D ; + drive-strength =3D <8>; + bias-pull-down =3D ; + }; + + pins-cmd-dat { + pinmux =3D , + , + , + , + , + , + , + , + ; + input-enable; + drive-strength =3D <8>; + bias-pull-up =3D ; + }; + + pins-ds { + pinmux =3D ; + drive-strength =3D <8>; + bias-pull-down =3D ; + }; + + pins-rst { + pinmux =3D ; + bias-pull-up =3D ; + }; + }; + + mmc1_default_pins: mmc1-default-pins { + pins-clk { + pinmux =3D ; + drive-strength =3D <6>; + bias-pull-down =3D ; + }; + + pins-cmd-dat { + pinmux =3D , + , + , + , + ; + input-enable; + drive-strength =3D <6>; + bias-pull-up =3D ; + }; + + pins-insert { + pinmux =3D ; + bias-pull-up; + }; + }; + + mmc1_uhs_pins: mmc1-uhs-pins { + pins-clk { + pinmux =3D ; + drive-strength =3D <8>; + bias-pull-down =3D ; + }; + + pins-cmd-dat { + pinmux =3D , + , + , + , + ; + input-enable; + drive-strength =3D <8>; + bias-pull-up =3D ; + }; + }; + + uart0_pins: uart0-pins { + pins { + pinmux =3D , + ; + bias-pull-up; + }; + }; + + uart1_pins: uart1-pins { + pins { + pinmux =3D , + ; + bias-pull-up; + }; + }; + + uart2_pins: uart2-pins { + pins { + pinmux =3D , + ; + bias-pull-up; + }; + + pins-rtscts { + pinmux =3D , + ; + }; + }; + + uart3_pins: uart3-pins { + pins { + pinmux =3D , + ; + bias-pull-up; + }; + + pins-rtscts { + pinmux =3D , + ; + }; + }; +}; + +&pmic { + interrupts-extended =3D <&pio 194 IRQ_TYPE_LEVEL_HIGH>; + + keys { + compatible =3D "mediatek,mt6359-keys"; + mediatek,long-press-mode =3D <1>; + power-off-time-sec =3D <0>; + + power-key { + linux,keycodes =3D ; + wakeup-source; + }; + + home { + linux,keycodes =3D ; + }; + }; +}; + +&spmi { + pmic@7 { + compatible =3D "mediatek,mt6319-regulator", "mediatek,mt6315-regulator"; + reg =3D <0x7 SPMI_USID>; + + regulators { + mt6319_vbuck1: vbuck1 { + regulator-name =3D "dvdd_proc_b"; + regulator-min-microvolt =3D <300000>; + regulator-max-microvolt =3D <1193750>; + regulator-enable-ramp-delay =3D <256>; + regulator-allowed-modes =3D <0 1 2>; + regulator-always-on; + }; + + vbuck2 { + regulator-name =3D "vbuck2"; + regulator-min-microvolt =3D <300000>; + regulator-max-microvolt =3D <1193750>; + regulator-enable-ramp-delay =3D <256>; + regulator-allowed-modes =3D <0 1 2>; + regulator-always-on; + }; + + vbuck3 { + regulator-name =3D "vdd2h_emi"; + regulator-min-microvolt =3D <300000>; + regulator-max-microvolt =3D <1193750>; + regulator-enable-ramp-delay =3D <256>; + regulator-allowed-modes =3D <0 1 2>; + regulator-always-on; + }; + + vbuck4 { + regulator-name =3D "avddq_emi"; + regulator-min-microvolt =3D <300000>; + regulator-max-microvolt =3D <1193750>; + regulator-enable-ramp-delay =3D <256>; + regulator-allowed-modes =3D <0 1 2>; + regulator-always-on; + }; + }; + }; +}; + +&uart0 { + pinctrl-0 =3D <&uart0_pins>; + pinctrl-names =3D "default"; + status =3D "okay"; +}; + +&uart1 { + pinctrl-0 =3D <&uart1_pins>; + pinctrl-names =3D "default"; + status =3D "okay"; +}; + +&uart2 { + pinctrl-0 =3D <&uart2_pins>; + pinctrl-names =3D "default"; + status =3D "okay"; +}; + +&uart3 { + pinctrl-0 =3D <&uart3_pins>; + pinctrl-names =3D "default"; + status =3D "okay"; +}; --=20 2.52.0 From nobody Fri Dec 19 21:17:25 2025 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 605192FBE05; Wed, 3 Dec 2025 13:59:42 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.251.105.195 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764770384; cv=none; b=O5RuHLhHnVt2Jp1SkZZ3SGJpAGUHRnU5fYvPcFWsf8oDmvCjIUP+1p5GJe/o5JdR6cMIw35P+xlbtNd3sf5xLrABr9c69AewL+22u41RfZZohfe0lOIUcHB1fCrBSYonzAp+2WVyXuHhMFkmXx1mPm+5drZPMB87O6GFbMARuiQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251203-add-mediatek-genio-520-720-evk-v1-4-df794b2a30ae@collabora.com> References: <20251203-add-mediatek-genio-520-720-evk-v1-0-df794b2a30ae@collabora.com> In-Reply-To: <20251203-add-mediatek-genio-520-720-evk-v1-0-df794b2a30ae@collabora.com> To: Greg Kroah-Hartman , Jiri Slaby , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Sean Wang Cc: kernel@collabora.com, linux-kernel@vger.kernel.org, linux-serial@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, Louis-Alexis Eyraud X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1764770377; l=3311; i=louisalexis.eyraud@collabora.com; s=20250113; h=from:subject:message-id; bh=5RzIhfynSwf60ufTcSsowDIcBzDbf1yZS7wGFV2NLjQ=; b=wPwMYUZq6iOSoCHWLmsZHVjtkg4yetPn3n4kbFw6/K/Euen42IqOv6aTmYy5MxJn+xXoJzooR RhsfnXX2z/FC3gEeA0WpyvNQz4IR2cyjIS8UeilUdQwB5Xmqowpkeh3 X-Developer-Key: i=louisalexis.eyraud@collabora.com; a=ed25519; pk=CHFBDB2Kqh4EHc6JIqFn69GhxJJAzc0Zr4e8QxtumuM= Add device-tree for the basic hardware enablement of the Genio 520-EVK board, based on MT8371 SoC. MT8371 SoC is a variant of MT8189 SoC with the following differences: - Arm Cortex-A78 CPU core maximum frequency (2.2 Ghz for MT8371, 3 Ghz for MT8189). - Arm Mali G57 MC2 GPU core maximum frequency (880 Mhz for MT8371, 1.1 Ghz for MT8189) - one ISP engine instead of two MT8371 hardware register maps are identical to MT8189. The Genio 520-EVK has following features: - MT8371 SoC - MT6365 PMIC - MT6319 Buck IC - MT6375 Charger IC - 8GB LPDDR5 RAM - 64GB eMMC 5.1 - 128GB UFS - 20V DC Jack - USB Type-C Power Adapter - Micro SD card slot - Push Button x 4 (Power, Reset, Download and Home Key) - LED x 3 (System Power, Reset, DC-IN Power) - USB Type-C Connector (USB 3.2) x 2 - USB Type-C Connector (USB 2.0) x 1 - 3.5mm Earphone Jack x 1 (with Microphone Input) - 3.5mm Line Out Audio Jack x 1 - Analog Microphone x 1 - Digital Microphone x 2 - Gigabit Ethernet with RJ45 connector - DP x 1 (Mode over USB Type-C) - LVDS port x 1 - eDP port x 1 - UART x2 with serial-to-usb converters and USB Type-C connectors - UART Port x 2 on Pin Header - M.2 Slot x 2 - I2C Capacitive Touch Pad - 4-Lane DSI x 1 - 4-Data Lane CSI x 2 - I2S Pin header - 40-Pin 2.54mm Pin Header x 1 - CAN Bus x 1 (RS232 Connector) Signed-off-by: Louis-Alexis Eyraud --- arch/arm64/boot/dts/mediatek/Makefile | 1 + arch/arm64/boot/dts/mediatek/mt8371-genio-520-evk.dts | 19 +++++++++++++++= ++++ 2 files changed, 20 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/Makefile b/arch/arm64/boot/dts/me= diatek/Makefile index e3b63085c0608b86dc8638c9d5e0b73441e9ed7b..e6356733a1c0ad5f3ccf9517f3e= 393ba5f114da8 100644 --- a/arch/arm64/boot/dts/mediatek/Makefile +++ b/arch/arm64/boot/dts/mediatek/Makefile @@ -106,6 +106,7 @@ dtb-$(CONFIG_ARCH_MEDIATEK) +=3D mt8195-evb.dtb dtb-$(CONFIG_ARCH_MEDIATEK) +=3D mt8365-evk.dtb dtb-$(CONFIG_ARCH_MEDIATEK) +=3D mt8370-genio-510-evk.dtb dtb-$(CONFIG_ARCH_MEDIATEK) +=3D mt8370-grinn-genio-510-sbc.dtb +dtb-$(CONFIG_ARCH_MEDIATEK) +=3D mt8371-genio-520-evk.dtb dtb-$(CONFIG_ARCH_MEDIATEK) +=3D mt8395-genio-1200-evk.dtb dtb-$(CONFIG_ARCH_MEDIATEK) +=3D mt8395-genio-1200-evk-ufs.dtb dtb-$(CONFIG_ARCH_MEDIATEK) +=3D mt8390-genio-700-evk.dtb diff --git a/arch/arm64/boot/dts/mediatek/mt8371-genio-520-evk.dts b/arch/a= rm64/boot/dts/mediatek/mt8371-genio-520-evk.dts new file mode 100644 index 0000000000000000000000000000000000000000..b259fc6c01a13bb84c1ed8b4433= a799241a28a6b --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt8371-genio-520-evk.dts @@ -0,0 +1,19 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (c) 2025 Collabora Ltd. + * Author: Louis-Alexis Eyraud + */ +/dts-v1/; +#include "mt8189.dtsi" +#include "mt8391-genio-common.dtsi" + +/* + * MT8371 SoC is a variant of the MT8189 with only one ISP engine + * and lower maximum frequency on the big cores and on the Mali GPU. + */ + +/ { + model =3D "MediaTek Genio 520 EVK"; + compatible =3D "mediatek,mt8371-evk", "mediatek,mt8371", + "mediatek,mt8189"; +}; --=20 2.52.0