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As events may be missing a TryEvent function will give None if an event is missing. To workaround missing JSON events for cortex-a53, sysfs encodings are used. Signed-off-by: Ian Rogers --- An earlier review of this patch by Leo Yan is here: https://lore.kernel.org/lkml/8168c713-005c-4fd9-a928-66763dab746a@arm.com/ Hopefully all corrections were made. --- tools/perf/pmu-events/arm64_metrics.py | 145 ++++++++++++++++++++++++- 1 file changed, 142 insertions(+), 3 deletions(-) diff --git a/tools/perf/pmu-events/arm64_metrics.py b/tools/perf/pmu-events= /arm64_metrics.py index ac717ca3513a..9678253e2e0e 100755 --- a/tools/perf/pmu-events/arm64_metrics.py +++ b/tools/perf/pmu-events/arm64_metrics.py @@ -2,13 +2,150 @@ # SPDX-License-Identifier: (LGPL-2.1 OR BSD-2-Clause) import argparse import os -from metric import (JsonEncodeMetric, JsonEncodeMetricGroupDescriptions, L= oadEvents, - MetricGroup) +from typing import Optional +from metric import (d_ratio, Event, JsonEncodeMetric, JsonEncodeMetricGrou= pDescriptions, + LoadEvents, Metric, MetricGroup) =20 # Global command line arguments. _args =3D None =20 =20 +def Arm64Topdown() -> MetricGroup: + """Returns a MetricGroup representing ARM64 topdown like metrics.""" + def TryEvent(name: str) -> Optional[Event]: + # Skip an event if not in the json files. + try: + return Event(name) + except: + return None + # ARM models like a53 lack JSON for INST_RETIRED but have the + # architetural standard event in sysfs. Use the PMU name to identify + # the sysfs event. + pmu_name =3D f'armv8_{_args.model.replace("-", "_")}' + ins =3D Event("instructions") + ins_ret =3D Event("INST_RETIRED", f"{pmu_name}/inst_retired/") + cycles =3D Event("cpu\\-cycles") + stall_fe =3D TryEvent("STALL_FRONTEND") + stall_be =3D TryEvent("STALL_BACKEND") + br_ret =3D TryEvent("BR_RETIRED") + br_mp_ret =3D TryEvent("BR_MIS_PRED_RETIRED") + dtlb_walk =3D TryEvent("DTLB_WALK") + itlb_walk =3D TryEvent("ITLB_WALK") + l1d_tlb =3D TryEvent("L1D_TLB") + l1i_tlb =3D TryEvent("L1I_TLB") + l1d_refill =3D Event("L1D_CACHE_REFILL", f"{pmu_name}/l1d_cache_refill= /") + l2d_refill =3D Event("L2D_CACHE_REFILL", f"{pmu_name}/l2d_cache_refill= /") + l1i_refill =3D Event("L1I_CACHE_REFILL", f"{pmu_name}/l1i_cache_refill= /") + l1d_access =3D Event("L1D_CACHE", f"{pmu_name}/l1d_cache/") + l2d_access =3D Event("L2D_CACHE", f"{pmu_name}/l2d_cache/") + llc_access =3D TryEvent("LL_CACHE_RD") + l1i_access =3D Event("L1I_CACHE", f"{pmu_name}/l1i_cache/") + llc_miss_rd =3D TryEvent("LL_CACHE_MISS_RD") + ase_spec =3D TryEvent("ASE_SPEC") + ld_spec =3D TryEvent("LD_SPEC") + st_spec =3D TryEvent("ST_SPEC") + vfp_spec =3D TryEvent("VFP_SPEC") + dp_spec =3D TryEvent("DP_SPEC") + br_immed_spec =3D TryEvent("BR_IMMED_SPEC") + br_indirect_spec =3D TryEvent("BR_INDIRECT_SPEC") + br_ret_spec =3D TryEvent("BR_RETURN_SPEC") + crypto_spec =3D TryEvent("CRYPTO_SPEC") + inst_spec =3D TryEvent("INST_SPEC") + return MetricGroup("lpm_topdown", [ + MetricGroup("lpm_topdown_tl", [ + Metric("lpm_topdown_tl_ipc", "Instructions per cycle", d_ratio( + ins, cycles), "insn/cycle"), + Metric("lpm_topdown_tl_stall_fe_rate", "Frontend stalls to all= cycles", + d_ratio(stall_fe, cycles), "100%") if stall_fe else Non= e, + Metric("lpm_topdown_tl_stall_be_rate", "Backend stalls to all = cycles", + d_ratio(stall_be, cycles), "100%") if stall_be else Non= e, + ]), + MetricGroup("lpm_topdown_fe_bound", [ + MetricGroup("lpm_topdown_fe_br", [ + Metric("lpm_topdown_fe_br_mp_per_insn", + "Branch mispredicts per instruction retired", + d_ratio(br_mp_ret, ins_ret), "br/insn") if br_mp_re= t else None, + Metric("lpm_topdown_fe_br_ins_rate", + "Branches per instruction retired", d_ratio( + br_ret, ins_ret), "100%") if br_ret else None, + Metric("lpm_topdown_fe_br_mispredict", + "Branch mispredicts per branch instruction", + d_ratio(br_mp_ret, br_ret), "100%") if (br_mp_ret a= nd br_ret) else None, + ]), + MetricGroup("lpm_topdown_fe_itlb", [ + Metric("lpm_topdown_fe_itlb_walks", "Itlb walks per insn", + d_ratio(itlb_walk, ins_ret), "walk/insn"), + Metric("lpm_topdown_fe_itlb_walk_rate", "Itlb walks per L1= I TLB access", + d_ratio(itlb_walk, l1i_tlb) if l1i_tlb else None, "= 100%"), + ]) if itlb_walk else None, + MetricGroup("lpm_topdown_fe_icache", [ + Metric("lpm_topdown_fe_icache_l1i_per_insn", + "L1I cache refills per instruction", + d_ratio(l1i_refill, ins_ret), "l1i/insn"), + Metric("lpm_topdown_fe_icache_l1i_miss_rate", + "L1I cache refills per L1I cache access", + d_ratio(l1i_refill, l1i_access), "100%"), + ]), + ]), + MetricGroup("lpm_topdown_be_bound", [ + MetricGroup("lpm_topdown_be_dtlb", [ + Metric("lpm_topdown_be_dtlb_walks", "Dtlb walks per instru= ction", + d_ratio(dtlb_walk, ins_ret), "walk/insn"), + Metric("lpm_topdown_be_dtlb_walk_rate", "Dtlb walks per L1= D TLB access", + d_ratio(dtlb_walk, l1d_tlb) if l1d_tlb else None, "= 100%"), + ]) if dtlb_walk else None, + MetricGroup("lpm_topdown_be_mix", [ + Metric("lpm_topdown_be_mix_ld", "Percentage of load instru= ctions", + d_ratio(ld_spec, inst_spec), "100%") if ld_spec els= e None, + Metric("lpm_topdown_be_mix_st", "Percentage of store instr= uctions", + d_ratio(st_spec, inst_spec), "100%") if st_spec els= e None, + Metric("lpm_topdown_be_mix_simd", "Percentage of SIMD inst= ructions", + d_ratio(ase_spec, inst_spec), "100%") if ase_spec e= lse None, + Metric("lpm_topdown_be_mix_fp", + "Percentage of floating point instructions", + d_ratio(vfp_spec, inst_spec), "100%") if vfp_spec e= lse None, + Metric("lpm_topdown_be_mix_dp", + "Percentage of data processing instructions", + d_ratio(dp_spec, inst_spec), "100%") if dp_spec els= e None, + Metric("lpm_topdown_be_mix_crypto", + "Percentage of data processing instructions", + d_ratio(crypto_spec, inst_spec), "100%") if crypto_= spec else None, + Metric( + "lpm_topdown_be_mix_br", "Percentage of branch instruc= tions", + d_ratio(br_immed_spec + br_indirect_spec + br_ret_spec, + inst_spec), "100%") if br_immed_spec and br_in= direct_spec and br_ret_spec else None, + ], description=3D"Breakdown of instructions by type. Counts in= clude both useful and wasted speculative instructions" + ) if inst_spec else None, + MetricGroup("lpm_topdown_be_dcache", [ + MetricGroup("lpm_topdown_be_dcache_l1", [ + Metric("lpm_topdown_be_dcache_l1_per_insn", + "L1D cache refills per instruction", + d_ratio(l1d_refill, ins_ret), "refills/insn"), + Metric("lpm_topdown_be_dcache_l1_miss_rate", + "L1D cache refills per L1D cache access", + d_ratio(l1d_refill, l1d_access), "100%") + ]), + MetricGroup("lpm_topdown_be_dcache_l2", [ + Metric("lpm_topdown_be_dcache_l2_per_insn", + "L2D cache refills per instruction", + d_ratio(l2d_refill, ins_ret), "refills/insn"), + Metric("lpm_topdown_be_dcache_l2_miss_rate", + "L2D cache refills per L2D cache access", + d_ratio(l2d_refill, l2d_access), "100%") + ]), + MetricGroup("lpm_topdown_be_dcache_llc", [ + Metric("lpm_topdown_be_dcache_llc_per_insn", + "Last level cache misses per instruction", + d_ratio(llc_miss_rd, ins_ret), "miss/insn"), + Metric("lpm_topdown_be_dcache_llc_miss_rate", + "Last level cache misses per last level cache a= ccess", + d_ratio(llc_miss_rd, llc_access), "100%") + ]) if llc_miss_rd and llc_access else None, + ]), + ]), + ]) + + def main() -> None: global _args =20 @@ -34,7 +171,9 @@ def main() -> None: directory =3D f"{_args.events_path}/arm64/{_args.vendor}/{_args.model}= /" LoadEvents(directory) =20 - all_metrics =3D MetricGroup("", []) + all_metrics =3D MetricGroup("", [ + Arm64Topdown(), + ]) =20 if _args.metricgroups: print(JsonEncodeMetricGroupDescriptions(all_metrics)) --=20 2.52.0.158.g65b55ccf14-goog