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Signed-off-by: Ian Rogers Tested-by: Thomas Falcon --- tools/perf/pmu-events/intel_metrics.py | 97 ++++++++++++++++++++++++++ 1 file changed, 97 insertions(+) diff --git a/tools/perf/pmu-events/intel_metrics.py b/tools/perf/pmu-events= /intel_metrics.py index 9cf4bd8ac769..77b8e10194db 100755 --- a/tools/perf/pmu-events/intel_metrics.py +++ b/tools/perf/pmu-events/intel_metrics.py @@ -320,6 +320,102 @@ def IntelCtxSw() -> MetricGroup: "retired & core cycles between context= switches")) =20 =20 +def IntelFpu() -> Optional[MetricGroup]: + cyc =3D Event("cycles") + try: + s_64 =3D Event("FP_ARITH_INST_RETIRED.SCALAR_SINGLE", + "SIMD_INST_RETIRED.SCALAR_SINGLE") + except: + return None + d_64 =3D Event("FP_ARITH_INST_RETIRED.SCALAR_DOUBLE", + "SIMD_INST_RETIRED.SCALAR_DOUBLE") + s_128 =3D Event("FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE", + "SIMD_INST_RETIRED.PACKED_SINGLE") + + flop =3D s_64 + d_64 + 4 * s_128 + + d_128 =3D None + s_256 =3D None + d_256 =3D None + s_512 =3D None + d_512 =3D None + try: + d_128 =3D Event("FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE") + flop +=3D 2 * d_128 + s_256 =3D Event("FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE") + flop +=3D 8 * s_256 + d_256 =3D Event("FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE") + flop +=3D 4 * d_256 + s_512 =3D Event("FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE") + flop +=3D 16 * s_512 + d_512 =3D Event("FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE") + flop +=3D 8 * d_512 + except: + pass + + f_assist =3D Event("ASSISTS.FP", "FP_ASSIST.ANY", "FP_ASSIST.S") + if f_assist in [ + "ASSISTS.FP", + "FP_ASSIST.S", + ]: + f_assist +=3D "/cmask=3D1/" + + flop_r =3D d_ratio(flop, interval_sec) + flop_c =3D d_ratio(flop, cyc) + nmi_constraint =3D MetricConstraint.GROUPED_EVENTS + if f_assist.name =3D=3D "ASSISTS.FP": # Icelake+ + nmi_constraint =3D MetricConstraint.NO_GROUP_EVENTS_NMI + + def FpuMetrics(group: str, fl: Optional[Event], mult: int, desc: str) = -> Optional[MetricGroup]: + if not fl: + return None + + f =3D fl * mult + fl_r =3D d_ratio(f, interval_sec) + r_s =3D d_ratio(fl, interval_sec) + return MetricGroup(group, [ + Metric(f"{group}_of_total", desc + " floating point operations= per second", + d_ratio(f, flop), "100%"), + Metric(f"{group}_flops", desc + " floating point operations pe= r second", + fl_r, "flops/s"), + Metric(f"{group}_ops", desc + " operations per second", + r_s, "ops/s"), + ]) + + return MetricGroup("lpm_fpu", [ + MetricGroup("lpm_fpu_total", [ + Metric("lpm_fpu_total_flops", "Floating point operations per s= econd", + flop_r, "flops/s"), + Metric("lpm_fpu_total_flopc", "Floating point operations per c= ycle", + flop_c, "flops/cycle", constraint=3Dnmi_constraint), + ]), + MetricGroup("lpm_fpu_64", [ + FpuMetrics("lpm_fpu_64_single", s_64, 1, "64-bit single"), + FpuMetrics("lpm_fpu_64_double", d_64, 1, "64-bit double"), + ]), + MetricGroup("lpm_fpu_128", [ + FpuMetrics("lpm_fpu_128_single", s_128, + 4, "128-bit packed single"), + FpuMetrics("lpm_fpu_128_double", d_128, + 2, "128-bit packed double"), + ]), + MetricGroup("lpm_fpu_256", [ + FpuMetrics("lpm_fpu_256_single", s_256, + 8, "128-bit packed single"), + FpuMetrics("lpm_fpu_256_double", d_256, + 4, "128-bit packed double"), + ]), + MetricGroup("lpm_fpu_512", [ + FpuMetrics("lpm_fpu_512_single", s_512, + 16, "128-bit packed single"), + FpuMetrics("lpm_fpu_512_double", d_512, + 8, "128-bit packed double"), + ]), + Metric("lpm_fpu_assists", "FP assists as a percentage of cycles", + d_ratio(f_assist, cyc), "100%"), + ]) + + def IntelIlp() -> MetricGroup: tsc =3D Event("msr/tsc/") c0 =3D Event("msr/mperf/") @@ -736,6 +832,7 @@ def main() -> None: Tsx(), IntelBr(), IntelCtxSw(), + IntelFpu(), IntelIlp(), IntelL2(), IntelLdSt(), --=20 2.52.0.158.g65b55ccf14-goog