From nobody Mon Feb 9 21:19:52 2026 Received: from mail.0la.ch (mail.0la.ch [78.47.82.197]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6AA84312829 for ; Tue, 2 Dec 2025 11:03:18 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=78.47.82.197 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764673400; cv=none; b=t1v0CJQSedvy15qJr7Iw8zDVDLnnJ4i1oS8EHuIP6BnDVMqido58riIr+je7YW/9/KRdOurZKKn/obkl9Hg1LlbNfHn48YxRFrl3bRC2/CKr7jTKkW5eS05LZ9wMvAMMI0GMW4z0DFnrVOGzkAhWeBzU3SfeRPax1N0O7c4gbvo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764673400; c=relaxed/simple; bh=DTsxQ9g9bO+m08KN6zR1reSukEBwk+9TBI1ofxB4tig=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=Qyt01iqYExnXNr8w8CQ/sCkXk6/bDnmTmwRdJan6TgJfzBRJtRtCmAXq/uC80jKNPhmuPUE3vuPbiVrYvtV1HQDYrmniP6f6qE/WV/7bAu5WpPBytXu5vYOfXu+frd/Mlzmx8h0XGu+YfeFsqlO4fe9JiMJaN7tQxgstn/Hmcl0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=lach.pw; spf=pass smtp.mailfrom=lach.pw; dkim=pass (2048-bit key) header.d=lach.pw header.i=@lach.pw header.b=DQWPYgod; dkim=permerror (0-bit key) header.d=lach.pw header.i=@lach.pw header.b=4a1II04o; arc=none smtp.client-ip=78.47.82.197 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=lach.pw Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=lach.pw Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=lach.pw header.i=@lach.pw header.b="DQWPYgod"; dkim=permerror (0-bit key) header.d=lach.pw header.i=@lach.pw header.b="4a1II04o" DKIM-Signature: v=1; a=rsa-sha256; s=202502r; d=lach.pw; c=relaxed/relaxed; h=Message-ID:Date:Subject:To:From; t=1764673366; bh=96Xx6pEA6IrK7KXRzHy93Ni ixWaJOWO8cK1KcI4cmBA=; b=DQWPYgodW9ZDxXKDNQ2kyOBxLem+Mg69hTqahxpofEZwaJq8w3 KoV45fdTwGzeIx4mK2ZoyjQIvthQh1HI5OsajT3ZwUsmCDQXtJ45hs0KnRN9gKp/oBL9Bb6TafY l9BhRizdm+Dri/hGCYNQVUsvAeM5R7GUYbjONswbj3rmkGgKo5Hviw+aCt4+bs0GmcI+J64c4u6 SkQ7r91MSyoDwKy4uB8zG+beqgYcV+L3pkEjCUf3qDBjD0kWyBUcTGWJtjcutf4FMfGZSSlHO+6 g4nldV2y8br1uYjBJRJJReUk5QhyhcmWEk0TxBl8H1x+9lDrZEebsimDInb8Jm+IapQ==; DKIM-Signature: v=1; a=ed25519-sha256; s=202502e; d=lach.pw; c=relaxed/relaxed; h=Message-ID:Date:Subject:To:From; t=1764673366; bh=96Xx6pEA6IrK7KXRzHy93Ni ixWaJOWO8cK1KcI4cmBA=; b=4a1II04oNIArJk4JPmVJHLVcoB7LyMpwoIt0MLygDJaJA0HZnf QvYH6OQ9XWj338Ok4FtR6RjO9Xb/laUfKHDw==; From: Yaroslav Bolyukin To: =?UTF-8?q?Ville=20Syrj=C3=A4l=C3=A4?= , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Jani Nikula Cc: Harry Wentland , Leo Li , Rodrigo Siqueira , Alex Deucher , =?UTF-8?q?Christian=20K=C3=B6nig?= , Wayne Lin , amd-gfx@lists.freedesktop.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, Yaroslav Bolyukin Subject: [PATCH v7 6/7] drm/edid: parse DRM VESA dsc bpp target Date: Tue, 2 Dec 2025 12:02:17 +0100 Message-ID: <20251202110218.9212-7-iam@lach.pw> X-Mailer: git-send-email 2.51.2 In-Reply-To: <20251202110218.9212-1-iam@lach.pw> References: <20251202110218.9212-1-iam@lach.pw> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" As per DisplayID v2.1a spec "DSC pass-through timing support", VESA vendor-specific data block may contain target DSC bits per pixel fields, that should be always used for the VII modes that declare they only support working with this value (Pass-through Timing Support for Target DSC Bits per Pixel). Signed-off-by: Yaroslav Bolyukin fixup parse DRM vesa dsc bpp target Reviewed-by: Jani Nikula --- drivers/gpu/drm/drm_displayid_internal.h | 4 ++++ drivers/gpu/drm/drm_edid.c | 17 +++++++++++++++++ include/drm/drm_connector.h | 6 ++++++ 3 files changed, 27 insertions(+) diff --git a/drivers/gpu/drm/drm_displayid_internal.h b/drivers/gpu/drm/drm= _displayid_internal.h index 55f972d32847..8f1a2f33ca1a 100644 --- a/drivers/gpu/drm/drm_displayid_internal.h +++ b/drivers/gpu/drm/drm_displayid_internal.h @@ -148,6 +148,8 @@ struct displayid_formula_timing_block { #define DISPLAYID_VESA_DP_TYPE GENMASK(2, 0) #define DISPLAYID_VESA_MSO_OVERLAP GENMASK(3, 0) #define DISPLAYID_VESA_MSO_MODE GENMASK(6, 5) +#define DISPLAYID_VESA_DSC_BPP_INT GENMASK(5, 0) +#define DISPLAYID_VESA_DSC_BPP_FRACT GENMASK(3, 0) =20 #define DISPLAYID_VESA_DP_TYPE_EDP 0 #define DISPLAYID_VESA_DP_TYPE_DP 1 @@ -157,6 +159,8 @@ struct displayid_vesa_vendor_specific_block { u8 oui[3]; u8 data_structure_type; u8 mso; + u8 dsc_bpp_int; + u8 dsc_bpp_fract; } __packed; =20 /* diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c index be8715632b91..8273920f5ba4 100644 --- a/drivers/gpu/drm/drm_edid.c +++ b/drivers/gpu/drm/drm_edid.c @@ -45,6 +45,7 @@ #include #include #include +#include #include =20 #include "drm_crtc_internal.h" @@ -6593,6 +6594,21 @@ static void drm_parse_vesa_specific_block(struct drm= _connector *connector, } else { info->mso_pixel_overlap =3D 0; } + + if (block->num_bytes < 7) { + /* DSC bpp is optional */ + return; + } + + info->dp_dsc_bpp_x16 =3D FIELD_GET(DISPLAYID_VESA_DSC_BPP_INT, vesa->dsc_= bpp_int) << 4 | + FIELD_GET(DISPLAYID_VESA_DSC_BPP_FRACT, vesa->dsc_bpp_fract); + + if (info->dp_dsc_bpp_x16 > 0) { + drm_dbg_kms(connector->dev, + "[CONNECTOR:%d:%s] DSC bits per pixel " FXP_Q4_FMT "\n", + connector->base.id, connector->name, + FXP_Q4_ARGS(info->dp_dsc_bpp_x16)); + } } =20 static void drm_update_vesa_specific_block(struct drm_connector *connector, @@ -6641,6 +6657,7 @@ static void drm_reset_display_info(struct drm_connect= or *connector) info->mso_stream_count =3D 0; info->mso_pixel_overlap =3D 0; info->max_dsc_bpp =3D 0; + info->dp_dsc_bpp_x16 =3D 0; =20 kfree(info->vics); info->vics =3D NULL; diff --git a/include/drm/drm_connector.h b/include/drm/drm_connector.h index 8f34f4b8183d..7decfc288aa3 100644 --- a/include/drm/drm_connector.h +++ b/include/drm/drm_connector.h @@ -837,6 +837,12 @@ struct drm_display_info { */ u32 max_dsc_bpp; =20 + /** + * @dp_dsc_bpp: DP Display-Stream-Compression (DSC) timing's target + * DSC bits per pixel in 6.4 fixed point format. 0 means undefined. + */ + u16 dp_dsc_bpp_x16; + /** * @vics: Array of vics_len VICs. Internal to EDID parsing. */ --=20 2.51.2