From nobody Mon Feb 9 21:36:53 2026 Received: from mail.0la.ch (mail.0la.ch [78.47.82.197]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 558B930F93B for ; Tue, 2 Dec 2025 11:03:11 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=78.47.82.197 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764673394; cv=none; b=HSC1EKCUSy8AsywOSRDsBAdZPFzLmPNuYIGzHDRkqbajVq6t2rMK/E3hWgUiUwdT+WbeIDIyys0WOFymlwibmmPqTLRDQf/2i9lKee4P3275sTqVjrSbIO+Nop1Vv9mCK/2sCi3xhps4+0gP9AWR7obUSu9qlh8yvFOZwEljDVc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764673394; c=relaxed/simple; bh=rzIaL7hyJMvG1+NX3dofFpY0BHqE/VMaSyooOUcBkgg=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=OSEp3UxVYZ7ulnVrkNu6yun8FwOlEBdMV5YZOSKj+BUsw7PIAt8pxQXsrW7hVuVIhH/yABUOTcZ1e2bxJAlxtfJ56C2qSyuWQlOnqoxRYvNxv/EPVcFFYyhwGvrDnrahdcZjGMwmqwcf7YrBfDDQg4rrcmaYNdI3/WSR7Kl9lBw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=lach.pw; spf=pass smtp.mailfrom=lach.pw; dkim=pass (2048-bit key) header.d=lach.pw header.i=@lach.pw header.b=p9eKqXCB; dkim=permerror (0-bit key) header.d=lach.pw header.i=@lach.pw header.b=1xMvkWRb; arc=none smtp.client-ip=78.47.82.197 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=lach.pw Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=lach.pw Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=lach.pw header.i=@lach.pw header.b="p9eKqXCB"; dkim=permerror (0-bit key) header.d=lach.pw header.i=@lach.pw header.b="1xMvkWRb" DKIM-Signature: v=1; a=rsa-sha256; s=202502r; d=lach.pw; c=relaxed/relaxed; h=Message-ID:Date:Subject:To:From; t=1764673365; bh=Gl9kuiz7jbxKaBYB2iofJTz 80qNWbCqFnBqucqQQ3oc=; b=p9eKqXCBJc4TANG3Ay+sRDTt3j0rIlasGtCAPJAFkjnkr/4pYS EFagbjxiWkhD9UzGiCHnUynw5AdaYweHA5nn119a5TGxFJNmJDHn5tZDOL4YIV9AoIM/dvRV6aY iMNi002C6KZpVyWWxJnoFNCOThN4ILLqG8Tz4SA3JBcz2yg/HDhUaOs12YfP68oltIpb/khygoj QccvZvDsPLxCE4quenBwuYMxqSXOIfAY9CWr2lu9/IAL45iGhVcIeb6qxABxf1pk+7zhpVWk61L omqnsTvcjrKfxpP8zF0VOWXZOFcZ9toHan17Oqp9RCUryUHVN96wejv4SCJPWIlg+wQ==; DKIM-Signature: v=1; a=ed25519-sha256; s=202502e; d=lach.pw; c=relaxed/relaxed; h=Message-ID:Date:Subject:To:From; t=1764673365; bh=Gl9kuiz7jbxKaBYB2iofJTz 80qNWbCqFnBqucqQQ3oc=; b=1xMvkWRbxqaqQQld0IyIfuKxKgmHfuECJiowHvMbJjW7tizC7T 1bA6a606A3AJGFKFHRhxpJVkavtrgV++clCg==; From: Yaroslav Bolyukin To: =?UTF-8?q?Ville=20Syrj=C3=A4l=C3=A4?= , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Jani Nikula Cc: Harry Wentland , Leo Li , Rodrigo Siqueira , Alex Deucher , =?UTF-8?q?Christian=20K=C3=B6nig?= , Wayne Lin , amd-gfx@lists.freedesktop.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, Yaroslav Bolyukin Subject: [PATCH v7 4/7] drm/edid: parse DSC DPP passthru support flag for mode VII timings Date: Tue, 2 Dec 2025 12:02:15 +0100 Message-ID: <20251202110218.9212-5-iam@lach.pw> X-Mailer: git-send-email 2.51.2 In-Reply-To: <20251202110218.9212-1-iam@lach.pw> References: <20251202110218.9212-1-iam@lach.pw> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" For timings v7 block revision >=3D1, revision field also contains a bit that indicates that the mode timings should only be used with fixed bits per pixel value specified in vesa vendor-specific block. Signed-off-by: Yaroslav Bolyukin Reviewed-by: Jani Nikula --- drivers/gpu/drm/drm_displayid_internal.h | 2 ++ drivers/gpu/drm/drm_edid.c | 12 ++++++++---- include/drm/drm_modes.h | 10 ++++++++++ 3 files changed, 20 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/drm_displayid_internal.h b/drivers/gpu/drm/drm= _displayid_internal.h index 72f107ae832f..724174b429f2 100644 --- a/drivers/gpu/drm/drm_displayid_internal.h +++ b/drivers/gpu/drm/drm_displayid_internal.h @@ -97,6 +97,7 @@ struct displayid_header { u8 ext_count; } __packed; =20 +#define DISPLAYID_BLOCK_REV GENMASK(2, 0) struct displayid_block { u8 tag; u8 rev; @@ -125,6 +126,7 @@ struct displayid_detailed_timings_1 { __le16 vsw; } __packed; =20 +#define DISPLAYID_BLOCK_PASSTHROUGH_TIMINGS_SUPPORT BIT(3) struct displayid_detailed_timing_block { struct displayid_block base; struct displayid_detailed_timings_1 timings[]; diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c index 380a9dda275f..b28ff4bafb1d 100644 --- a/drivers/gpu/drm/drm_edid.c +++ b/drivers/gpu/drm/drm_edid.c @@ -6794,8 +6794,8 @@ static void update_display_info(struct drm_connector = *connector, } =20 static struct drm_display_mode *drm_mode_displayid_detailed(struct drm_dev= ice *dev, - const struct displayid_detailed_timings_1 *timings, - bool type_7) + const struct displayid_block *block, + const struct displayid_detailed_timings_1 *timings) { struct drm_display_mode *mode; unsigned int pixel_clock =3D (timings->pixel_clock[0] | @@ -6811,11 +6811,16 @@ static struct drm_display_mode *drm_mode_displayid_= detailed(struct drm_device *d unsigned int vsync_width =3D le16_to_cpu(timings->vsw) + 1; bool hsync_positive =3D le16_to_cpu(timings->hsync) & (1 << 15); bool vsync_positive =3D le16_to_cpu(timings->vsync) & (1 << 15); + bool type_7 =3D block->tag =3D=3D DATA_BLOCK_2_TYPE_7_DETAILED_TIMING; =20 mode =3D drm_mode_create(dev); if (!mode) return NULL; =20 + if (type_7 && FIELD_GET(DISPLAYID_BLOCK_REV, block->rev) >=3D 1) + mode->dsc_passthrough_timings_support =3D + block->rev & DISPLAYID_BLOCK_PASSTHROUGH_TIMINGS_SUPPORT; + /* resolution is kHz for type VII, and 10 kHz for type I */ mode->clock =3D type_7 ? pixel_clock : pixel_clock * 10; mode->hdisplay =3D hactive; @@ -6848,7 +6853,6 @@ static int add_displayid_detailed_1_modes(struct drm_= connector *connector, int num_timings; struct drm_display_mode *newmode; int num_modes =3D 0; - bool type_7 =3D block->tag =3D=3D DATA_BLOCK_2_TYPE_7_DETAILED_TIMING; /* blocks must be multiple of 20 bytes length */ if (block->num_bytes % 20) return 0; @@ -6857,7 +6861,7 @@ static int add_displayid_detailed_1_modes(struct drm_= connector *connector, for (i =3D 0; i < num_timings; i++) { struct displayid_detailed_timings_1 *timings =3D &det->timings[i]; =20 - newmode =3D drm_mode_displayid_detailed(connector->dev, timings, type_7); + newmode =3D drm_mode_displayid_detailed(connector->dev, block, timings); if (!newmode) continue; =20 diff --git a/include/drm/drm_modes.h b/include/drm/drm_modes.h index b9bb92e4b029..312e5c03af9a 100644 --- a/include/drm/drm_modes.h +++ b/include/drm/drm_modes.h @@ -417,6 +417,16 @@ struct drm_display_mode { */ enum hdmi_picture_aspect picture_aspect_ratio; =20 + /** + * @dsc_passthrough_timing_support: + * + * Indicates whether this mode timing descriptor is supported + * with specific target DSC bits per pixel only. + * + * VESA vendor-specific data block shall exist with the relevant + * DSC bits per pixel declaration when this flag is set to true. + */ + bool dsc_passthrough_timings_support; }; =20 /** --=20 2.51.2