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X-OriginatorOrg: ti.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 02 Dec 2025 10:22:30.2559 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 584088a1-32ad-4798-948c-08de318cb320 X-MS-Exchange-CrossTenant-Id: e5b49634-450b-4709-8abb-1e2b19b982b7 X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=e5b49634-450b-4709-8abb-1e2b19b982b7;Ip=[198.47.21.195];Helo=[flwvzet201.ext.ti.com] X-MS-Exchange-CrossTenant-AuthSource: BL02EPF0001A105.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY8PR10MB7217 Content-Type: text/plain; charset="utf-8" The current bindings duplicate the port definitions for each FPD-Link RX and CSI-2 TX ports. This results in a large amount of repeated schema blocks and makes it harder to extend the bindings for new devices. Refactor the bindings by introducing shared deftinitions for FPD-Link input ports and CSI-2 output ports. No functional change intended. Signed-off-by: Yemike Abhilash Chandra --- .../bindings/media/i2c/ti,ds90ub960.yaml | 120 +++++++----------- 1 file changed, 44 insertions(+), 76 deletions(-) diff --git a/Documentation/devicetree/bindings/media/i2c/ti,ds90ub960.yaml = b/Documentation/devicetree/bindings/media/i2c/ti,ds90ub960.yaml index 0539d52de422..6a78288aebaa 100644 --- a/Documentation/devicetree/bindings/media/i2c/ti,ds90ub960.yaml +++ b/Documentation/devicetree/bindings/media/i2c/ti,ds90ub960.yaml @@ -125,102 +125,35 @@ properties: =20 ports: $ref: /schemas/graph.yaml#/properties/ports + description: | + Ports represent FPD-Link inputs to the deserializer and CSI TX outpu= ts from the deserializer. + Their number is model-dependent. =20 properties: port@0: - $ref: /schemas/graph.yaml#/$defs/port-base - unevaluatedProperties: false + $ref: '#/$defs/FPDLink-input-port' description: FPD-Link input 0 =20 - properties: - endpoint: - $ref: /schemas/media/video-interfaces.yaml# - unevaluatedProperties: false - description: - Endpoint for FPD-Link port. If the RX mode for this port is = RAW, - hsync-active and vsync-active must be defined. - port@1: - $ref: /schemas/graph.yaml#/$defs/port-base - unevaluatedProperties: false + $ref: '#/$defs/FPDLink-input-port' description: FPD-Link input 1 =20 - properties: - endpoint: - $ref: /schemas/media/video-interfaces.yaml# - unevaluatedProperties: false - description: - Endpoint for FPD-Link port. If the RX mode for this port is = RAW, - hsync-active and vsync-active must be defined. - port@2: - $ref: /schemas/graph.yaml#/$defs/port-base - unevaluatedProperties: false + $ref: '#/$defs/FPDLink-input-port' description: FPD-Link input 2 =20 - properties: - endpoint: - $ref: /schemas/media/video-interfaces.yaml# - unevaluatedProperties: false - description: - Endpoint for FPD-Link port. If the RX mode for this port is = RAW, - hsync-active and vsync-active must be defined. - port@3: - $ref: /schemas/graph.yaml#/$defs/port-base - unevaluatedProperties: false + $ref: '#/$defs/FPDLink-input-port' description: FPD-Link input 3 =20 - properties: - endpoint: - $ref: /schemas/media/video-interfaces.yaml# - unevaluatedProperties: false - description: - Endpoint for FPD-Link port. If the RX mode for this port is = RAW, - hsync-active and vsync-active must be defined. - port@4: - $ref: /schemas/graph.yaml#/$defs/port-base - unevaluatedProperties: false + $ref: '#/$defs/CSI2-output-port' description: CSI-2 Output 0 =20 - properties: - endpoint: - $ref: /schemas/media/video-interfaces.yaml# - unevaluatedProperties: false - - properties: - data-lanes: - minItems: 1 - maxItems: 4 - link-frequencies: - maxItems: 1 - - required: - - data-lanes - - link-frequencies - port@5: - $ref: /schemas/graph.yaml#/$defs/port-base - unevaluatedProperties: false + $ref: '#/$defs/CSI2-output-port' description: CSI-2 Output 1 =20 - properties: - endpoint: - $ref: /schemas/media/video-interfaces.yaml# - unevaluatedProperties: false - - properties: - data-lanes: - minItems: 1 - maxItems: 4 - link-frequencies: - maxItems: 1 - - required: - - data-lanes - - link-frequencies - required: - port@0 - port@1 @@ -236,6 +169,41 @@ required: - clock-names - ports =20 +$defs: + FPDLink-input-port: + $ref: /schemas/graph.yaml#/$defs/port-base + unevaluatedProperties: false + description: FPD-Link input + + properties: + endpoint: + $ref: /schemas/media/video-interfaces.yaml# + unevaluatedProperties: false + description: + Endpoint for FPD-Link port. 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X-OriginatorOrg: ti.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 02 Dec 2025 10:22:34.2436 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: bcbb52ae-195c-4c60-d997-08de318cb577 X-MS-Exchange-CrossTenant-Id: e5b49634-450b-4709-8abb-1e2b19b982b7 X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=e5b49634-450b-4709-8abb-1e2b19b982b7;Ip=[198.47.23.195];Helo=[lewvzet201.ext.ti.com] X-MS-Exchange-CrossTenant-AuthSource: CH3PEPF0000000D.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN0PR10MB5062 Content-Type: text/plain; charset="utf-8" Replace chip-specific boolean flags with chip_type and chip_family enums. This simplifies the process of adding support for newer devices and also improves code readability. Signed-off-by: Yemike Abhilash Chandra --- drivers/media/i2c/ds90ub960.c | 56 ++++++++++++++++++++++++----------- 1 file changed, 38 insertions(+), 18 deletions(-) diff --git a/drivers/media/i2c/ds90ub960.c b/drivers/media/i2c/ds90ub960.c index 5a83218e64ab..45494fcaf095 100644 --- a/drivers/media/i2c/ds90ub960.c +++ b/drivers/media/i2c/ds90ub960.c @@ -454,12 +454,21 @@ #define UB960_MAX_EQ_LEVEL 14 #define UB960_NUM_EQ_LEVELS (UB960_MAX_EQ_LEVEL - UB960_MIN_EQ_LEVEL + 1) =20 +enum chip_type { + UB960, + UB9702, +}; + +enum chip_family { + FAMILY_FPD3, + FAMILY_FPD4, +}; + struct ub960_hw_data { - const char *model; + enum chip_type chip_type; + enum chip_family chip_family; u8 num_rxports; u8 num_txports; - bool is_ub9702; - bool is_fpdlink4; }; =20 enum ub960_rxport_mode { @@ -1933,7 +1942,7 @@ static int ub960_rxport_wait_locks(struct ub960_data = *priv, if (ret) return ret; =20 - if (priv->hw_data->is_ub9702) { + if (priv->hw_data->chip_type =3D=3D UB9702) { dev_dbg(dev, "\trx%u: locked, freq %llu Hz\n", nport, ((u64)v * HZ_PER_MHZ) >> 8); } else { @@ -2195,7 +2204,7 @@ static int ub960_rxport_add_serializer(struct ub960_d= ata *priv, u8 nport) =20 ser_pdata->port =3D nport; ser_pdata->atr =3D priv->atr; - if (priv->hw_data->is_ub9702) + if (priv->hw_data->chip_type =3D=3D UB9702) ser_pdata->bc_rate =3D ub960_calc_bc_clk_rate_ub9702(priv, rxport); else ser_pdata->bc_rate =3D ub960_calc_bc_clk_rate_ub960(priv, rxport); @@ -2361,7 +2370,7 @@ static int ub960_init_tx_ports(struct ub960_data *pri= v) { int ret; =20 - if (priv->hw_data->is_ub9702) + if (priv->hw_data->chip_type =3D=3D UB9702) ret =3D ub960_init_tx_ports_ub9702(priv); else ret =3D ub960_init_tx_ports_ub960(priv); @@ -3633,7 +3642,7 @@ static int ub960_configure_ports_for_streaming(struct= ub960_data *priv, =20 case RXPORT_MODE_CSI2_SYNC: case RXPORT_MODE_CSI2_NONSYNC: - if (!priv->hw_data->is_ub9702) { + if (priv->hw_data->chip_type !=3D UB9702) { /* Map all VCs from this port to the same VC */ ub960_rxport_write(priv, nport, UB960_RR_CSI_VC_MAP, (vc << UB960_RR_CSI_VC_MAP_SHIFT(3)) | @@ -4259,7 +4268,7 @@ static int ub960_log_status(struct v4l2_subdev *sd) =20 dev_info(dev, "\tcsi_err_counter %u\n", v); =20 - if (!priv->hw_data->is_ub9702) { + if (priv->hw_data->chip_type !=3D UB9702) { ret =3D ub960_log_status_ub960_sp_eq(priv, nport); if (ret) return ret; @@ -4417,7 +4426,7 @@ ub960_parse_dt_rxport_link_properties(struct ub960_da= ta *priv, return -EINVAL; } =20 - if (!priv->hw_data->is_fpdlink4 && cdr_mode =3D=3D RXPORT_CDR_FPD4) { + if (priv->hw_data->chip_family !=3D FAMILY_FPD4 && cdr_mode =3D=3D RXPORT= _CDR_FPD4) { dev_err(dev, "rx%u: FPD-Link 4 CDR not supported\n", nport); return -EINVAL; } @@ -4976,6 +4985,7 @@ static int ub960_get_hw_resources(struct ub960_data *= priv) static int ub960_enable_core_hw(struct ub960_data *priv) { struct device *dev =3D &priv->client->dev; + const char *model; u8 rev_mask; int ret; u8 dev_sts; @@ -5012,14 +5022,24 @@ static int ub960_enable_core_hw(struct ub960_data *= priv) goto err_pd_gpio; } =20 - dev_dbg(dev, "Found %s (rev/mask %#04x)\n", priv->hw_data->model, - rev_mask); + switch (priv->hw_data->chip_type) { + case UB960: + model =3D "UB960"; + break; + case UB9702: + model =3D "Ub9702"; + break; + default: + model =3D "Unknown"; + break; + } + dev_dbg(dev, "Found %s (rev/mask %#04x)\n", model, rev_mask); =20 ret =3D ub960_read(priv, UB960_SR_DEVICE_STS, &dev_sts, NULL); if (ret) goto err_pd_gpio; =20 - if (priv->hw_data->is_ub9702) + if (priv->hw_data->chip_type =3D=3D UB9702) ret =3D ub960_read(priv, UB9702_SR_REFCLK_FREQ, &refclk_freq, NULL); else @@ -5038,7 +5058,7 @@ static int ub960_enable_core_hw(struct ub960_data *pr= iv) goto err_pd_gpio; =20 /* release GPIO lock */ - if (priv->hw_data->is_ub9702) { + if (priv->hw_data->chip_type =3D=3D UB9702) { ret =3D ub960_update_bits(priv, UB960_SR_RESET, UB960_SR_RESET_GPIO_LOCK_RELEASE, UB960_SR_RESET_GPIO_LOCK_RELEASE, @@ -5111,7 +5131,7 @@ static int ub960_probe(struct i2c_client *client) if (ret) goto err_free_ports; =20 - if (priv->hw_data->is_ub9702) + if (priv->hw_data->chip_type =3D=3D UB9702) ret =3D ub960_init_rx_ports_ub9702(priv); else ret =3D ub960_init_rx_ports_ub960(priv); @@ -5179,17 +5199,17 @@ static void ub960_remove(struct i2c_client *client) } =20 static const struct ub960_hw_data ds90ub960_hw =3D { - .model =3D "ub960", + .chip_type =3D UB960, + .chip_family =3D FAMILY_FPD3, .num_rxports =3D 4, .num_txports =3D 2, }; =20 static const struct ub960_hw_data ds90ub9702_hw =3D { - .model =3D "ub9702", + .chip_type =3D UB9702, + .chip_family =3D FAMILY_FPD4, .num_rxports =3D 4, .num_txports =3D 2, - .is_ub9702 =3D true, - .is_fpdlink4 =3D true, }; =20 static const struct i2c_device_id ub960_id[] =3D { --=20 2.34.1 From nobody Sun Dec 14 12:17:29 2025 Received: from MW6PR02CU001.outbound.protection.outlook.com (mail-westus2azon11012016.outbound.protection.outlook.com [52.101.48.16]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 202F830BF52; Tue, 2 Dec 2025 10:22:46 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=52.101.48.16 ARC-Seal: i=2; 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X-OriginatorOrg: ti.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 02 Dec 2025 10:22:43.3398 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 41dbfcfd-75e9-4484-70e3-08de318cbaef X-MS-Exchange-CrossTenant-Id: e5b49634-450b-4709-8abb-1e2b19b982b7 X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=e5b49634-450b-4709-8abb-1e2b19b982b7;Ip=[198.47.21.194];Helo=[flwvzet200.ext.ti.com] X-MS-Exchange-CrossTenant-AuthSource: CO1PEPF000075EE.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MW4PR10MB6322 Content-Type: text/plain; charset="utf-8" DS90UB954-Q1 is an FPDLink-III deserializer that is mostly register compatible with DS90UB960-Q1. The main difference is that it supports half of the RX and TX ports, i.e. 2x FPDLink RX ports and 1x CSI TX port. Therefore, add support for DS90UB954 within the existing bindings. Link: https://www.ti.com/lit/gpn/ds90ub954-q1 Signed-off-by: Yemike Abhilash Chandra --- .../bindings/media/i2c/ti,ds90ub960.yaml | 300 +++++++++++++++--- 1 file changed, 264 insertions(+), 36 deletions(-) diff --git a/Documentation/devicetree/bindings/media/i2c/ti,ds90ub960.yaml = b/Documentation/devicetree/bindings/media/i2c/ti,ds90ub960.yaml index 6a78288aebaa..1ef977c2e479 100644 --- a/Documentation/devicetree/bindings/media/i2c/ti,ds90ub960.yaml +++ b/Documentation/devicetree/bindings/media/i2c/ti,ds90ub960.yaml @@ -13,12 +13,10 @@ description: The TI DS90UB9XX devices are FPD-Link video deserializers with I2C and G= PIO forwarding. =20 -allOf: - - $ref: /schemas/i2c/i2c-atr.yaml# - properties: compatible: enum: + - ti,ds90ub954-q1 - ti,ds90ub960-q1 - ti,ds90ub9702-q1 =20 @@ -129,39 +127,6 @@ properties: Ports represent FPD-Link inputs to the deserializer and CSI TX outpu= ts from the deserializer. Their number is model-dependent. =20 - properties: - port@0: - $ref: '#/$defs/FPDLink-input-port' - description: FPD-Link input 0 - - port@1: - $ref: '#/$defs/FPDLink-input-port' - description: FPD-Link input 1 - - port@2: - $ref: '#/$defs/FPDLink-input-port' - description: FPD-Link input 2 - - port@3: - $ref: '#/$defs/FPDLink-input-port' - description: FPD-Link input 3 - - port@4: - $ref: '#/$defs/CSI2-output-port' - description: CSI-2 Output 0 - - port@5: - $ref: '#/$defs/CSI2-output-port' - description: CSI-2 Output 1 - - required: - - port@0 - - port@1 - - port@2 - - port@3 - - port@4 - - port@5 - required: - compatible - reg @@ -204,9 +169,86 @@ $defs: - data-lanes - link-frequencies =20 +allOf: + - $ref: /schemas/i2c/i2c-atr.yaml# + - if: + properties: + compatible: + contains: + enum: + - ti,ds90ub960-q1 + - ti,ds90ub9702-q1 + then: + properties: + ports: + properties: + port@0: + $ref: '#/$defs/FPDLink-input-port' + description: FPD-Link input 0 + + port@1: + $ref: '#/$defs/FPDLink-input-port' + description: FPD-Link input 1 + + port@2: + $ref: '#/$defs/FPDLink-input-port' + description: FPD-Link input 2 + + port@3: + $ref: '#/$defs/FPDLink-input-port' + description: FPD-Link input 3 + + port@4: + $ref: '#/$defs/CSI2-output-port' + description: CSI-2 Output 0 + + port@5: + $ref: '#/$defs/CSI2-output-port' + description: CSI-2 Output 1 + + required: + - port@0 + - port@1 + - port@2 + - port@3 + - port@4 + - port@5 + + - if: + properties: + compatible: + contains: + const: ti,ds90ub954-q1 + then: + properties: + ports: + properties: + port@0: + $ref: '#/$defs/FPDLink-input-port' + description: FPD-Link input 0 + + port@1: + $ref: '#/$defs/FPDLink-input-port' + description: FPD-Link input 1 + + port@2: + $ref: '#/$defs/CSI2-output-port' + description: CSI-2 Output 0 + + required: + - port@0 + - port@1 + - port@2 + + links: + properties: + link@2: false + link@3: false + unevaluatedProperties: false =20 examples: + # Example with ds90ub960 Deserializer - | #include =20 @@ -406,4 +448,190 @@ examples: }; }; }; + + # Example with ds90ub954 Deserializer + - | + #include + + i2c { + clock-frequency =3D <400000>; + #address-cells =3D <1>; + #size-cells =3D <0>; + + deser@3d { + compatible =3D "ti,ds90ub954-q1"; + reg =3D <0x3d>; + + clock-names =3D "refclk"; + clocks =3D <&fixed_clock>; + + powerdown-gpios =3D <&pca9555 7 GPIO_ACTIVE_LOW>; + + i2c-alias-pool =3D <0x4a 0x4b 0x4c>; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + /* Port 0, Camera 0 */ + port@0 { + reg =3D <0>; + + ub954_fpd3_1_in: endpoint { + remote-endpoint =3D <&ub953_2_out>; + }; + }; + + /* Port 1, Camera 1 */ + port@1 { + reg =3D <1>; + + ub954_fpd3_2_in: endpoint { + remote-endpoint =3D <&ub913_3_out>; + hsync-active =3D <0>; + vsync-active =3D <1>; + }; + }; + + /* Port 2, CSI-2 TX */ + port@2 { + reg =3D <2>; + ds90ub954_0_csi_out: endpoint { + data-lanes =3D <1 2 3 4>; + link-frequencies =3D /bits/ 64 <800000000>; + remote-endpoint =3D <&csi2_phy0>; + }; + }; + }; + + links { + #address-cells =3D <1>; + #size-cells =3D <0>; + + /* Link 0 has DS90UB953 serializer and IMX274 sensor */ + + link@0 { + #address-cells =3D <1>; + #size-cells =3D <0>; + + reg =3D <0>; + i2c-alias =3D <0x44>; + + ti,rx-mode =3D <3>; + + serializer3: serializer@30 { + compatible =3D "ti,ds90ub953-q1"; + reg =3D <0x30>; + + gpio-controller; + #gpio-cells =3D <2>; + + #clock-cells =3D <0>; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + ub953_2_in: endpoint { + data-lanes =3D <1 2 3 4>; + remote-endpoint =3D <&sensor_3_out>; + }; + }; + + port@1 { + reg =3D <1>; + + ub953_2_out: endpoint { + remote-endpoint =3D <&ub954_fpd3_1_in>; + }; + }; + }; + + i2c { + #address-cells =3D <1>; + #size-cells =3D <0>; + + sensor@1a { + compatible =3D "sony,imx274"; + reg =3D <0x1a>; + + clocks =3D <&serializer>; + clock-names =3D "inck"; + + reset-gpios =3D <&serializer3 0 GPIO_ACTIVE_LOW>; + + port { + sensor_3_out: endpoint { + remote-endpoint =3D <&ub953_2_in>; + }; + }; + }; + }; + }; + }; /* End of link@0 */ + + /* Link 1 has DS90UB913 serializer and MT9V111 sensor */ + + link@1 { + reg =3D <1>; + i2c-alias =3D <0x45>; + + ti,rx-mode =3D <0>; + + serializer4: serializer { + compatible =3D "ti,ds90ub913a-q1"; + + gpio-controller; + #gpio-cells =3D <2>; + + clocks =3D <&clk_cam_48M>; + clock-names =3D "clkin"; + + #clock-cells =3D <0>; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + ub913_3_in: endpoint { + remote-endpoint =3D <&sensor_4_out>; + pclk-sample =3D <1>; + }; + }; + + port@1 { + reg =3D <1>; + + ub913_3_out: endpoint { + remote-endpoint =3D <&ub954_fpd3_2_in>; + }; + }; + }; + + i2c { + #address-cells =3D <1>; + #size-cells =3D <0>; + + sensor@48 { + compatible =3D "aptina,mt9v111"; + reg =3D <0x48>; + + clocks =3D <&serializer4>; + + port { + sensor_4_out: endpoint { + remote-endpoint =3D <&ub913_3_in>; + }; + }; + }; + }; + }; + }; /* End of link@1 */ + }; + }; + }; ... --=20 2.34.1 From nobody Sun Dec 14 12:17:29 2025 Received: from DM5PR21CU001.outbound.protection.outlook.com (mail-centralusazon11011071.outbound.protection.outlook.com [52.101.62.71]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 992FA3115A5; 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X-OriginatorOrg: ti.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 02 Dec 2025 10:22:50.2292 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 164b6365-1b57-4d55-aa71-08de318cbf0a X-MS-Exchange-CrossTenant-Id: e5b49634-450b-4709-8abb-1e2b19b982b7 X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=e5b49634-450b-4709-8abb-1e2b19b982b7;Ip=[198.47.21.194];Helo=[flwvzet200.ext.ti.com] X-MS-Exchange-CrossTenant-AuthSource: CO1PEPF000075F4.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN0PR10MB5189 Content-Type: text/plain; charset="utf-8" DS90UB954-Q1 is an FPDLink-III deserializer that is mostly register compatible with DS90UB960-Q1. The main difference is that it supports half of the RX and TX ports, i.e. 2x FPDLink RX ports and 1x CSI TX port. A couple of differences are between the status registers and the strobe setting registers. Hence accommodate these differences in the UB960 driver so that we can reuse a large part of the existing code. Link: https://www.ti.com/lit/gpn/ds90ub954-q1 Signed-off-by: Yemike Abhilash Chandra --- Refer table 5.2.1 STROBE_SET Register in [1] for DS90UB954 strobe setting register. [1]: https://www.ti.com/lit/an/snla301/snla301.pdf drivers/media/i2c/Kconfig | 4 +- drivers/media/i2c/ds90ub960.c | 165 +++++++++++++++++++++++++--------- 2 files changed, 125 insertions(+), 44 deletions(-) diff --git a/drivers/media/i2c/Kconfig b/drivers/media/i2c/Kconfig index 745819c625d6..52104f76e371 100644 --- a/drivers/media/i2c/Kconfig +++ b/drivers/media/i2c/Kconfig @@ -1703,8 +1703,8 @@ config VIDEO_DS90UB960 select V4L2_FWNODE select VIDEO_V4L2_SUBDEV_API help - Device driver for the Texas Instruments DS90UB960 - FPD-Link III Deserializer and DS90UB9702 FPD-Link IV Deserializer. + Device driver for the Texas Instruments DS90UB954, DS90UB960 + FPD-Link III Deserializers and DS90UB9702 FPD-Link IV Deserializer. =20 config VIDEO_MAX96714 tristate "Maxim MAX96714 GMSL2 deserializer" diff --git a/drivers/media/i2c/ds90ub960.c b/drivers/media/i2c/ds90ub960.c index 45494fcaf095..7d3e5a87bb17 100644 --- a/drivers/media/i2c/ds90ub960.c +++ b/drivers/media/i2c/ds90ub960.c @@ -396,6 +396,12 @@ #define UB960_IR_RX_ANA_STROBE_SET_DATA_NO_EXTRA_DELAY BIT(3) #define UB960_IR_RX_ANA_STROBE_SET_DATA_DELAY_MASK GENMASK(2, 0) =20 +#define UB954_IR_RX_ANA_STROBE_SET_CLK_DATA 0x08 +#define UB954_IR_RX_ANA_STROBE_SET_CLK_NO_EXTRA_DELAY BIT(3) +#define UB954_IR_RX_ANA_STROBE_SET_DATA_NO_EXTRA_DELAY BIT(7) +#define UB954_IR_RX_ANA_STROBE_SET_CLK_DELAY_MASK GENMASK(2, 0) +#define UB954_IR_RX_ANA_STROBE_SET_DATA_DELAY_MASK GENMASK(4, 6) + /* UB9702 Registers */ =20 #define UB9702_SR_CSI_EXCLUSIVE_FWD2 0x3c @@ -455,6 +461,7 @@ #define UB960_NUM_EQ_LEVELS (UB960_MAX_EQ_LEVEL - UB960_MIN_EQ_LEVEL + 1) =20 enum chip_type { + UB954, UB960, UB9702, }; @@ -1000,6 +1007,10 @@ static int ub960_txport_select(struct ub960_data *pr= iv, u8 nport) =20 lockdep_assert_held(&priv->reg_lock); =20 + /* UB954 has only 1 CSI TX. Hence, no need to select */ + if (priv->hw_data->chip_type =3D=3D UB954) + return 0; + if (priv->reg_current.txport =3D=3D nport) return 0; =20 @@ -1424,10 +1435,11 @@ static int ub960_parse_dt_txport(struct ub960_data = *priv, priv->tx_link_freq[0] =3D vep.link_frequencies[0]; priv->tx_data_rate =3D priv->tx_link_freq[0] * 2; =20 - if (priv->tx_data_rate !=3D MHZ(1600) && - priv->tx_data_rate !=3D MHZ(1200) && - priv->tx_data_rate !=3D MHZ(800) && - priv->tx_data_rate !=3D MHZ(400)) { + if ((priv->tx_data_rate !=3D MHZ(1600) && + priv->tx_data_rate !=3D MHZ(1200) && + priv->tx_data_rate !=3D MHZ(800) && + priv->tx_data_rate !=3D MHZ(400)) || + (priv->hw_data->chip_type =3D=3D UB954 && priv->tx_data_rate =3D=3D = MHZ(1200))) { dev_err(dev, "tx%u: invalid 'link-frequencies' value\n", nport); ret =3D -EINVAL; goto err_free_vep; @@ -1551,22 +1563,44 @@ static int ub960_rxport_get_strobe_pos(struct ub960= _data *priv, u8 clk_delay, data_delay; int ret; =20 - ret =3D ub960_read_ind(priv, UB960_IND_TARGET_RX_ANA(nport), - UB960_IR_RX_ANA_STROBE_SET_CLK, &v, NULL); - if (ret) - return ret; + /* + * DS90UB960 has two separate registers for clk and data delay whereas + * DS90UB954 has a single combined register. Hence read accordingly + */ + if (priv->hw_data->chip_type =3D=3D UB954) { + ret =3D ub960_read_ind(priv, UB960_IND_TARGET_RX_ANA(nport), + UB954_IR_RX_ANA_STROBE_SET_CLK_DATA, &v, NULL); + if (ret) + return ret; =20 - clk_delay =3D (v & UB960_IR_RX_ANA_STROBE_SET_CLK_NO_EXTRA_DELAY) ? - 0 : UB960_MANUAL_STROBE_EXTRA_DELAY; + clk_delay =3D (v & UB954_IR_RX_ANA_STROBE_SET_CLK_NO_EXTRA_DELAY) ? + 0 : UB960_MANUAL_STROBE_EXTRA_DELAY; =20 - ret =3D ub960_read_ind(priv, UB960_IND_TARGET_RX_ANA(nport), - UB960_IR_RX_ANA_STROBE_SET_DATA, &v, NULL); - if (ret) - return ret; + ret =3D ub960_read_ind(priv, UB960_IND_TARGET_RX_ANA(nport), + UB954_IR_RX_ANA_STROBE_SET_CLK_DATA, &v, NULL); + if (ret) + return ret; + + data_delay =3D (v & UB954_IR_RX_ANA_STROBE_SET_DATA_NO_EXTRA_DELAY) ? + 0 : UB960_MANUAL_STROBE_EXTRA_DELAY; + } else { + ret =3D ub960_read_ind(priv, UB960_IND_TARGET_RX_ANA(nport), + UB960_IR_RX_ANA_STROBE_SET_CLK, &v, NULL); + if (ret) + return ret; =20 - data_delay =3D (v & UB960_IR_RX_ANA_STROBE_SET_DATA_NO_EXTRA_DELAY) ? + clk_delay =3D (v & UB960_IR_RX_ANA_STROBE_SET_CLK_NO_EXTRA_DELAY) ? 0 : UB960_MANUAL_STROBE_EXTRA_DELAY; =20 + ret =3D ub960_read_ind(priv, UB960_IND_TARGET_RX_ANA(nport), + UB960_IR_RX_ANA_STROBE_SET_DATA, &v, NULL); + if (ret) + return ret; + + data_delay =3D (v & UB960_IR_RX_ANA_STROBE_SET_DATA_NO_EXTRA_DELAY) ? + 0 : UB960_MANUAL_STROBE_EXTRA_DELAY; + } + ret =3D ub960_rxport_read(priv, nport, UB960_RR_SFILTER_STS_0, &v, NULL); if (ret) return ret; @@ -1590,8 +1624,17 @@ static int ub960_rxport_set_strobe_pos(struct ub960_= data *priv, u8 clk_delay, data_delay; int ret =3D 0; =20 - clk_delay =3D UB960_IR_RX_ANA_STROBE_SET_CLK_NO_EXTRA_DELAY; - data_delay =3D UB960_IR_RX_ANA_STROBE_SET_DATA_NO_EXTRA_DELAY; + /* + * DS90UB960 has two separate registers for clk and data delay whereas + * DS90UB954 has a single combined register. Hence assign accordingly. + */ + if (priv->hw_data->chip_type =3D=3D UB954) { + clk_delay =3D UB954_IR_RX_ANA_STROBE_SET_CLK_NO_EXTRA_DELAY; + data_delay =3D UB954_IR_RX_ANA_STROBE_SET_DATA_NO_EXTRA_DELAY; + } else { + clk_delay =3D UB960_IR_RX_ANA_STROBE_SET_CLK_NO_EXTRA_DELAY; + data_delay =3D UB960_IR_RX_ANA_STROBE_SET_DATA_NO_EXTRA_DELAY; + } =20 if (strobe_pos < UB960_MIN_AEQ_STROBE_POS) clk_delay =3D abs(strobe_pos) - UB960_MANUAL_STROBE_EXTRA_DELAY; @@ -1602,11 +1645,25 @@ static int ub960_rxport_set_strobe_pos(struct ub960= _data *priv, else if (strobe_pos > 0) data_delay =3D strobe_pos | UB960_IR_RX_ANA_STROBE_SET_DATA_NO_EXTRA_DEL= AY; =20 - ub960_write_ind(priv, UB960_IND_TARGET_RX_ANA(nport), - UB960_IR_RX_ANA_STROBE_SET_CLK, clk_delay, &ret); - - ub960_write_ind(priv, UB960_IND_TARGET_RX_ANA(nport), - UB960_IR_RX_ANA_STROBE_SET_DATA, data_delay, &ret); + /* + * DS90UB960 has two separate registers for clk and data delay whereas + * DS90UB954 has a single combined register. Hence write the registers ac= cordingly. + */ + if (priv->hw_data->chip_type =3D=3D UB954) { + ub960_ind_update_bits(priv, UB960_IND_TARGET_RX_ANA(nport), + UB954_IR_RX_ANA_STROBE_SET_CLK_DATA, + UB954_IR_RX_ANA_STROBE_SET_CLK_NO_EXTRA_DELAY, + clk_delay, &ret); + ub960_ind_update_bits(priv, UB960_IND_TARGET_RX_ANA(nport), + UB954_IR_RX_ANA_STROBE_SET_CLK_DATA, + UB954_IR_RX_ANA_STROBE_SET_DATA_NO_EXTRA_DELAY, + data_delay, &ret); + } else { + ub960_write_ind(priv, UB960_IND_TARGET_RX_ANA(nport), + UB960_IR_RX_ANA_STROBE_SET_CLK, clk_delay, &ret); + ub960_write_ind(priv, UB960_IND_TARGET_RX_ANA(nport), + UB960_IR_RX_ANA_STROBE_SET_DATA, data_delay, &ret); + } =20 return ret; } @@ -4176,33 +4233,40 @@ static int ub960_log_status(struct v4l2_subdev *sd) dev_info(dev, "\tsync %u, pass %u\n", v & (u8)BIT(1), v & (u8)BIT(0)); =20 - ret =3D ub960_read16(priv, UB960_SR_CSI_FRAME_COUNT_HI(nport), - &v16, NULL); - if (ret) - return ret; + /* + * Frame counter, frame error counter, line counter and line error count= er + * registers are marked as reserved in the UB954 datasheet. Hence restri= ct + * the following register reads only for UB960 and UB9702. + */ + if (priv->hw_data->chip_type !=3D UB954) { + ret =3D ub960_read16(priv, UB960_SR_CSI_FRAME_COUNT_HI(nport), + &v16, NULL); + if (ret) + return ret; =20 - dev_info(dev, "\tframe counter %u\n", v16); + dev_info(dev, "\tframe counter %u\n", v16); =20 - ret =3D ub960_read16(priv, UB960_SR_CSI_FRAME_ERR_COUNT_HI(nport), - &v16, NULL); - if (ret) - return ret; + ret =3D ub960_read16(priv, UB960_SR_CSI_FRAME_ERR_COUNT_HI(nport), + &v16, NULL); + if (ret) + return ret; =20 - dev_info(dev, "\tframe error counter %u\n", v16); + dev_info(dev, "\tframe error counter %u\n", v16); =20 - ret =3D ub960_read16(priv, UB960_SR_CSI_LINE_COUNT_HI(nport), - &v16, NULL); - if (ret) - return ret; + ret =3D ub960_read16(priv, UB960_SR_CSI_LINE_COUNT_HI(nport), + &v16, NULL); + if (ret) + return ret; =20 - dev_info(dev, "\tline counter %u\n", v16); + dev_info(dev, "\tline counter %u\n", v16); =20 - ret =3D ub960_read16(priv, UB960_SR_CSI_LINE_ERR_COUNT_HI(nport), - &v16, NULL); - if (ret) - return ret; + ret =3D ub960_read16(priv, UB960_SR_CSI_LINE_ERR_COUNT_HI(nport), + &v16, NULL); + if (ret) + return ret; =20 - dev_info(dev, "\tline error counter %u\n", v16); + dev_info(dev, "\tline error counter %u\n", v16); + } } =20 for_each_rxport(priv, it) { @@ -5023,6 +5087,9 @@ static int ub960_enable_core_hw(struct ub960_data *pr= iv) } =20 switch (priv->hw_data->chip_type) { + case UB954: + model =3D "UB954"; + break; case UB960: model =3D "UB960"; break; @@ -5039,6 +5106,11 @@ static int ub960_enable_core_hw(struct ub960_data *p= riv) if (ret) goto err_pd_gpio; =20 + /* + * UB954 REFCLK_FREQ is not synchronized, so multiple reads are recommend= ed + * by the datasheet. However, we use the same logic as UB960 (single read= ), + * as practical testing showed this is sufficient and stable for UB954 as= well. + */ if (priv->hw_data->chip_type =3D=3D UB9702) ret =3D ub960_read(priv, UB9702_SR_REFCLK_FREQ, &refclk_freq, NULL); @@ -5198,6 +5270,13 @@ static void ub960_remove(struct i2c_client *client) mutex_destroy(&priv->reg_lock); } =20 +static const struct ub960_hw_data ds90ub954_hw =3D { + .chip_type =3D UB954, + .chip_family =3D FAMILY_FPD3, + .num_rxports =3D 2, + .num_txports =3D 1, +}; + static const struct ub960_hw_data ds90ub960_hw =3D { .chip_type =3D UB960, .chip_family =3D FAMILY_FPD3, @@ -5213,6 +5292,7 @@ static const struct ub960_hw_data ds90ub9702_hw =3D { }; =20 static const struct i2c_device_id ub960_id[] =3D { + { "ds90ub954-q1", (kernel_ulong_t)&ds90ub954_hw }, { "ds90ub960-q1", (kernel_ulong_t)&ds90ub960_hw }, { "ds90ub9702-q1", (kernel_ulong_t)&ds90ub9702_hw }, {} @@ -5220,6 +5300,7 @@ static const struct i2c_device_id ub960_id[] =3D { MODULE_DEVICE_TABLE(i2c, ub960_id); =20 static const struct of_device_id ub960_dt_ids[] =3D { + { .compatible =3D "ti,ds90ub954-q1", .data =3D &ds90ub954_hw }, { .compatible =3D "ti,ds90ub960-q1", .data =3D &ds90ub960_hw }, { .compatible =3D "ti,ds90ub9702-q1", .data =3D &ds90ub9702_hw }, {} --=20 2.34.1