From nobody Tue Dec 16 01:57:06 2025 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 797EC312801; Tue, 2 Dec 2025 09:48:19 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=60.244.123.138 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764668902; cv=none; b=Oz3UtaeZhU9HhzeQ6rdL3gzyUXx9Cvqazanpvs0MieI+6kXTu3bDmQWewsFp/NCXA7RM2mbafLUOqNIG/CDeAd7lP74czbiV19c7oTAT96eHOV0bvToITfI0EJWUeMVLoHSq2xucEhWg7qqH6JxQeh0pJ3lb287VZaKhFT9N+LQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764668902; c=relaxed/simple; bh=wUr2HpwIJuST4uB++UPSkdMlaO8+9jx9c+ZnYzBf2io=; h=From:To:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=Um4coff7mHsc6dHT2qruW+PzZ0fg35Y30/BUwCy0DqN3mULs806c9R91zmofRqLC5MC9px9kK1s85kPzO4UgtX4IMzljD8KbC6qPz6tPxQaAz4+10uDXW3SMsjkHtCLkBiT0Xy2S7PFlWjuy3KkxzJ19VuvHaIAdrfTyJlVhAxw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mediatek.com; spf=pass smtp.mailfrom=mediatek.com; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b=tNfOMlSe; arc=none smtp.client-ip=60.244.123.138 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mediatek.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=mediatek.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="tNfOMlSe" X-UUID: 05152310cf6411f0b2bf0b349165d6e0-20251202 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:Content-Transfer-Encoding:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:To:From; bh=IuxrjQGkPURWMxOhrzqIZDhazzA4UeBlX38l8eJK1zg=; b=tNfOMlSeuoBxFpg9aFDwM4uu9OVLPVqWy63MLZRWWGSE4Y7GtS3uK4Dal/o36xx5Mx6AQ4LXesxq6yeuzXwDlHsxjGRXe4p6TOIG2zwZW+N1SIi2gwrN8AmIMTiQ3F56Y9dFsVWvKKyfvzkEN1psfVHP6H2aIG1YkfugW58kIfg=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.3.6,REQID:07600075-f341-4cc8-a7e9-3caf11a67b59,IP:0,UR L:0,TC:0,Content:0,EDM:-20,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTION :release,TS:-20 X-CID-META: VersionHash:a9d874c,CLOUDID:7c455002-1fa9-44eb-b231-4afc61466396,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:81|82|102|836|888|898,TC:-5,Content: 0|15|50,EDM:1,IP:nil,URL:0,File:130,RT:0,Bulk:nil,QS:nil,BEC:nil,COL:0,OSI :0,OSA:0,AV:0,LES:1,SPR:NO,DKR:0,DKP:0,BRR:0,BRE:0,ARC:0 X-CID-BVR: 2,SSN|SDN X-CID-BAS: 2,SSN|SDN,0,_ X-CID-FACTOR: TF_CID_SPAM_SNR X-CID-RHF: D41D8CD98F00B204E9800998ECF8427E X-UUID: 05152310cf6411f0b2bf0b349165d6e0-20251202 Received: from mtkmbs14n1.mediatek.inc [(172.21.101.75)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 88952954; Tue, 02 Dec 2025 17:48:13 +0800 Received: from mtkmbs13n2.mediatek.inc (172.21.101.108) by mtkmbs10n2.mediatek.inc (172.21.101.183) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.26; Tue, 2 Dec 2025 17:48:12 +0800 Received: from mhfsdcap04.gcn.mediatek.inc (10.17.3.154) by mtkmbs13n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1748.26 via Frontend Transport; Tue, 2 Dec 2025 17:48:11 +0800 From: Kyrie Wu To: Hans Verkuil , Mauro Carvalho Chehab , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Kyrie Wu , , , , , Subject: [PATCH v11 12/12] media: mediatek: jpeg: add jpeg smmu sid setting Date: Tue, 2 Dec 2025 17:48:00 +0800 Message-ID: <20251202094800.6140-13-kyrie.wu@mediatek.com> X-Mailer: git-send-email 2.46.0 In-Reply-To: <20251202094800.6140-1-kyrie.wu@mediatek.com> References: <20251202094800.6140-1-kyrie.wu@mediatek.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-MTK: N Content-Type: text/plain; charset="utf-8" Add a configuration to set jpeg dec & enc smmu sid Signed-off-by: Kyrie Wu --- .../platform/mediatek/jpeg/mtk_jpeg_core.c | 37 +++++++++++++++++++ .../platform/mediatek/jpeg/mtk_jpeg_core.h | 15 ++++++++ .../platform/mediatek/jpeg/mtk_jpeg_dec_hw.c | 23 ++++++++++++ .../platform/mediatek/jpeg/mtk_jpeg_enc_hw.c | 23 ++++++++++++ 4 files changed, 98 insertions(+) diff --git a/drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.c b/drivers= /media/platform/mediatek/jpeg/mtk_jpeg_core.c index 10a588b92e76..625dfa8468e1 100644 --- a/drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.c +++ b/drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.c @@ -15,6 +15,7 @@ #include #include #include +#include #include #include #include @@ -1613,6 +1614,20 @@ static irqreturn_t mtk_jpeg_enc_done(struct mtk_jpeg= _dev *jpeg) return IRQ_HANDLED; } =20 +static void mtk_jpeg_enc_set_smmu_sid(struct mtk_jpegenc_comp_dev *jpeg) +{ + struct mtk_jpeg_dev *mjpeg =3D jpeg->master_dev; + + if (!mjpeg->variant->support_smmu || !jpeg->smmu_regmap) + return; + + regmap_update_bits(jpeg->smmu_regmap, JPEG_ENC_SMMU_SID, + JPG_REG_GUSER_ID_MASK << + JPG_REG_ENC_GUSER_ID_SHIFT, + JPG_REG_GUSER_ID_ENC_SID << + JPG_REG_ENC_GUSER_ID_SHIFT); +} + static void mtk_jpegenc_worker(struct work_struct *work) { struct mtk_jpegenc_comp_dev *comp_jpeg[MTK_JPEGENC_HW_MAX]; @@ -1674,6 +1689,9 @@ static void mtk_jpegenc_worker(struct work_struct *wo= rk) jpeg_dst_buf->frame_num =3D ctx->total_frame_num; ctx->total_frame_num++; mtk_jpeg_enc_reset(comp_jpeg[hw_id]->reg_base); + + mtk_jpeg_enc_set_smmu_sid(comp_jpeg[hw_id]); + mtk_jpeg_set_enc_dst(ctx, comp_jpeg[hw_id]->reg_base, &dst_buf->vb2_buf); @@ -1701,6 +1719,20 @@ static void mtk_jpegenc_worker(struct work_struct *w= ork) v4l2_m2m_job_finish(jpeg->m2m_dev, ctx->fh.m2m_ctx); } =20 +static void mtk_jpeg_dec_set_smmu_sid(struct mtk_jpegdec_comp_dev *jpeg) +{ + struct mtk_jpeg_dev *mjpeg =3D jpeg->master_dev; + + if (!mjpeg->variant->support_smmu || !jpeg->smmu_regmap) + return; + + regmap_update_bits(jpeg->smmu_regmap, JPEG_DEC_SMMU_SID, + JPG_REG_GUSER_ID_MASK << + JPG_REG_DEC_GUSER_ID_SHIFT, + JPG_REG_GUSER_ID_DEC_SID << + JPG_REG_DEC_GUSER_ID_SHIFT); +} + static void mtk_jpegdec_worker(struct work_struct *work) { struct mtk_jpeg_ctx *ctx =3D container_of(work, struct mtk_jpeg_ctx, @@ -1784,6 +1816,9 @@ static void mtk_jpegdec_worker(struct work_struct *wo= rk) jpeg_dst_buf->frame_num =3D ctx->total_frame_num; ctx->total_frame_num++; mtk_jpeg_dec_reset(comp_jpeg[hw_id]->reg_base); + + mtk_jpeg_dec_set_smmu_sid(comp_jpeg[hw_id]); + mtk_jpeg_dec_set_config(comp_jpeg[hw_id]->reg_base, jpeg->variant->support_34bit, &jpeg_src_buf->dec_param, @@ -1943,6 +1978,7 @@ static struct mtk_jpeg_variant mtk8196_jpegenc_drvdat= a =3D { .cap_q_default_fourcc =3D V4L2_PIX_FMT_JPEG, .multi_core =3D true, .jpeg_worker =3D mtk_jpegenc_worker, + .support_smmu =3D true, }; =20 static const struct mtk_jpeg_variant mtk8195_jpegdec_drvdata =3D { @@ -1969,6 +2005,7 @@ static const struct mtk_jpeg_variant mtk8196_jpegdec_= drvdata =3D { .cap_q_default_fourcc =3D V4L2_PIX_FMT_YUV420M, .multi_core =3D true, .jpeg_worker =3D mtk_jpegdec_worker, + .support_smmu =3D true, }; =20 static const struct of_device_id mtk_jpeg_match[] =3D { diff --git a/drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.h b/drivers= /media/platform/mediatek/jpeg/mtk_jpeg_core.h index 33f7fbc4ca5e..6e8304680393 100644 --- a/drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.h +++ b/drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.h @@ -11,6 +11,7 @@ =20 #include #include +#include #include #include #include @@ -34,6 +35,14 @@ =20 #define MTK_JPEG_MAX_EXIF_SIZE (64 * 1024) =20 +#define JPEG_DEC_SMMU_SID 0 +#define JPEG_ENC_SMMU_SID 0 +#define JPG_REG_GUSER_ID_MASK 0x7 +#define JPG_REG_GUSER_ID_DEC_SID 0x4 +#define JPG_REG_GUSER_ID_ENC_SID 0x5 +#define JPG_REG_DEC_GUSER_ID_SHIFT 8 +#define JPG_REG_ENC_GUSER_ID_SHIFT 4 + #define MTK_JPEG_ADDR_MASK GENMASK(1, 0) =20 /** @@ -65,6 +74,7 @@ enum mtk_jpeg_ctx_state { * @multi_core: mark jpeg hw is multi_core or not * @jpeg_worker: jpeg dec or enc worker * @support_34bit: flag to check support for 34-bit DMA address + * @support_smmu: flag to check if support smmu */ struct mtk_jpeg_variant { struct clk_bulk_data *clks; @@ -82,6 +92,7 @@ struct mtk_jpeg_variant { bool multi_core; void (*jpeg_worker)(struct work_struct *work); bool support_34bit; + bool support_smmu; }; =20 struct mtk_jpeg_src_buf { @@ -150,6 +161,7 @@ struct mtk_jpegdec_clk { * @hw_param: jpeg encode hw parameters * @hw_state: record hw state * @hw_lock: spinlock protecting the hw device resource + * @smmu_regmap: SMMU registers mapping */ struct mtk_jpegenc_comp_dev { struct device *dev; @@ -163,6 +175,7 @@ struct mtk_jpegenc_comp_dev { enum mtk_jpeg_hw_state hw_state; /* spinlock protecting the hw device resource */ spinlock_t hw_lock; + struct regmap *smmu_regmap; }; =20 /** @@ -177,6 +190,7 @@ struct mtk_jpegenc_comp_dev { * @hw_param: jpeg decode hw parameters * @hw_state: record hw state * @hw_lock: spinlock protecting hw + * @smmu_regmap: SMMU registers mapping */ struct mtk_jpegdec_comp_dev { struct device *dev; @@ -190,6 +204,7 @@ struct mtk_jpegdec_comp_dev { enum mtk_jpeg_hw_state hw_state; /* spinlock protecting the hw device resource */ spinlock_t hw_lock; + struct regmap *smmu_regmap; }; =20 /** diff --git a/drivers/media/platform/mediatek/jpeg/mtk_jpeg_dec_hw.c b/drive= rs/media/platform/mediatek/jpeg/mtk_jpeg_dec_hw.c index e453a1634f33..da753a636eaa 100644 --- a/drivers/media/platform/mediatek/jpeg/mtk_jpeg_dec_hw.c +++ b/drivers/media/platform/mediatek/jpeg/mtk_jpeg_dec_hw.c @@ -624,6 +624,25 @@ static int mtk_jpegdec_hw_init_irq(struct mtk_jpegdec_= comp_dev *dev) return 0; } =20 +static int mtk_jpegdec_smmu_init(struct mtk_jpegdec_comp_dev *dev) +{ + struct mtk_jpeg_dev *master_dev =3D dev->master_dev; + + if (!master_dev->variant->support_smmu) + return 0; + + dev->smmu_regmap =3D + syscon_regmap_lookup_by_phandle(dev->plat_dev->dev.of_node, + "mediatek,smmu-config"); + if (IS_ERR(dev->smmu_regmap)) { + return dev_err_probe(dev->dev, PTR_ERR(dev->smmu_regmap), + "mmap smmu_base failed(%ld)\n", + PTR_ERR(dev->smmu_regmap)); + } + + return 0; +} + static int mtk_jpegdec_hw_probe(struct platform_device *pdev) { struct mtk_jpegdec_clk *jpegdec_clk; @@ -677,6 +696,10 @@ static int mtk_jpegdec_hw_probe(struct platform_device= *pdev) dev->master_dev =3D master_dev; master_dev->max_hw_count++; =20 + ret =3D mtk_jpegdec_smmu_init(dev); + if (ret) + return ret; + platform_set_drvdata(pdev, dev); pm_runtime_enable(&pdev->dev); ret =3D devm_clk_bulk_get(dev->dev, diff --git a/drivers/media/platform/mediatek/jpeg/mtk_jpeg_enc_hw.c b/drive= rs/media/platform/mediatek/jpeg/mtk_jpeg_enc_hw.c index b30c728c3712..8a61d5537315 100644 --- a/drivers/media/platform/mediatek/jpeg/mtk_jpeg_enc_hw.c +++ b/drivers/media/platform/mediatek/jpeg/mtk_jpeg_enc_hw.c @@ -348,6 +348,25 @@ static int mtk_jpegenc_hw_init_irq(struct mtk_jpegenc_= comp_dev *dev) return 0; } =20 +static int mtk_jpegenc_smmu_init(struct mtk_jpegenc_comp_dev *dev) +{ + struct mtk_jpeg_dev *master_dev =3D dev->master_dev; + + if (!master_dev->variant->support_smmu) + return 0; + + dev->smmu_regmap =3D + syscon_regmap_lookup_by_phandle(dev->plat_dev->dev.of_node, + "mediatek,smmu-config"); + if (IS_ERR(dev->smmu_regmap)) { + return dev_err_probe(dev->dev, PTR_ERR(dev->smmu_regmap), + "mmap smmu_base failed(%ld)\n", + PTR_ERR(dev->smmu_regmap)); + } + + return 0; +} + static int mtk_jpegenc_hw_probe(struct platform_device *pdev) { struct mtk_jpegenc_clk *jpegenc_clk; @@ -399,6 +418,10 @@ static int mtk_jpegenc_hw_probe(struct platform_device= *pdev) dev->master_dev =3D master_dev; master_dev->max_hw_count++; =20 + ret =3D mtk_jpegenc_smmu_init(dev); + if (ret) + return ret; + platform_set_drvdata(pdev, dev); pm_runtime_enable(&pdev->dev); ret =3D devm_clk_bulk_get(dev->dev, --=20 2.45.2