From nobody Mon Dec 15 21:59:57 2025 Received: from azure-sdnproxy.icoremail.net (azure-sdnproxy.icoremail.net [4.193.249.245]) by smtp.subspace.kernel.org (Postfix) with ESMTP id D22AE307AC3; Tue, 2 Dec 2025 09:04:01 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=4.193.249.245 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764666245; cv=none; b=ClyApSaqvKRBfkMPiqRigRvPAyalq2zWRABFR0UzTy9xqwFrxOxEt0m0fe2McE/tvgRnbVP8tAiRTZt5mW/h/1XDxauO90SsI3ZmzKbjNaqDYNusTklXtyxo4ot01AloE9LXScwVMdfi2EoWIPKB4Rce9OcRMGh6jbVYiNOu09M= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764666245; c=relaxed/simple; bh=Pbcq19isPFypswc9lypP49kdkmbWbx9SJexhiFp73zc=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=aMTH38AKAhD2oU31v38xzuCYQw2bqD6QkAeGfj7UJWa9hJo7bClVgvqu/CumttNP8N8vVQTL+tJvmG+lbnqE2IVI/08s2xp17sMecfrfp+B3jiV3FC7rz6ttaScKvFdEa31VlXWT2Gl6J4F4v+T9HuPseMQ/T7qDfjjrOd77Jas= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=eswincomputing.com; spf=pass smtp.mailfrom=eswincomputing.com; arc=none smtp.client-ip=4.193.249.245 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=eswincomputing.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=eswincomputing.com Received: from E0004758DT.eswin.cn (unknown [10.12.96.83]) by app2 (Coremail) with SMTP id TQJkCgBHi65qqy5pt5iAAA--.58919S2; Tue, 02 Dec 2025 17:03:39 +0800 (CST) From: zhangsenchuan@eswincomputing.com To: bhelgaas@google.com, mani@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, lpieralisi@kernel.org, kwilczynski@kernel.org, robh@kernel.org, p.zabel@pengutronix.de, jingoohan1@gmail.com, gustavo.pimentel@synopsys.com, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, christian.bruel@foss.st.com, mayank.rana@oss.qualcomm.com, shradha.t@samsung.com, krishna.chundru@oss.qualcomm.com, thippeswamy.havalige@amd.com, inochiama@gmail.com, Frank.li@nxp.com Cc: ningyu@eswincomputing.com, linmin@eswincomputing.com, pinkesh.vaghela@einfochips.com, ouyanghui@eswincomputing.com, Senchuan Zhang Subject: [PATCH v7 1/3] dt-bindings: PCI: eic7700: Add Eswin PCIe host controller Date: Tue, 2 Dec 2025 17:03:34 +0800 Message-ID: <20251202090334.1619-1-zhangsenchuan@eswincomputing.com> X-Mailer: git-send-email 2.49.0.windows.1 In-Reply-To: <20251202090225.1602-1-zhangsenchuan@eswincomputing.com> References: <20251202090225.1602-1-zhangsenchuan@eswincomputing.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: TQJkCgBHi65qqy5pt5iAAA--.58919S2 X-Coremail-Antispam: 1UD129KBjvJXoWxZw4UKr1kCFW5Gr4fGrWfKrg_yoWrArW5pF ZrCFW8Wr48Xr1fAw4UJF1jkF13Ja1vkFnYyr1xW3W3t3s5ta4qqr43KF13J345Gr4jq34Y gFnIv34xtw17A3DanT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnRJUUUBv14x267AKxVW5JVWrJwAFc2x0x2IEx4CE42xK8VAvwI8IcIk0 rVWrJVCq3wAFIxvE14AKwVWUJVWUGwA2ocxC64kIII0Yj41l84x0c7CEw4AK67xGY2AK02 1l84ACjcxK6xIIjxv20xvE14v26w1j6s0DM28EF7xvwVC0I7IYx2IY6xkF7I0E14v26r4U JVWxJr1l84ACjcxK6I8E87Iv67AKxVW0oVCq3wA2z4x0Y4vEx4A2jsIEc7CjxVAFwI0_Gc CE3s1le2I262IYc4CY6c8Ij28IcVAaY2xG8wAqx4xG64xvF2IEw4CE5I8CrVC2j2WlYx0E 2Ix0cI8IcVAFwI0_JrI_JrylYx0Ex4A2jsIE14v26r1j6r4UMcvjeVCFs4IE7xkEbVWUJV W8JwACjcxG0xvY0x0EwIxGrwACjI8F5VA0II8E6IAqYI8I648v4I1lFIxGxcIEc7CjxVA2 Y2ka0xkIwI1lw4CEc2x0rVAKj4xxMxkF7I0En4kS14v26r4a6rW5MxkIecxEwVCm-wCF04 k20xvY0x0EwIxGrwCFx2IqxVCFs4IE7xkEbVWUJVW8JwC20s026c02F40E14v26r1j6r18 MI8I3I0E7480Y4vE14v26r106r1rMI8E67AF67kF1VAFwI0_GFv_WrylIxkGc2Ij64vIr4 1lIxAIcVC0I7IYx2IY67AKxVWUJVWUCwCI42IY6xIIjxv20xvEc7CjxVAFwI0_Gr0_Cr1l IxAIcVCF04k26cxKx2IYs7xG6r1j6r1xMIIF0xvEx4A2jsIE14v26r1j6r4UMIIF0xvEx4 A2jsIEc7CjxVAFwI0_Gr0_Gr1UYxBIdaVFxhVjvjDU0xZFpf9x0pRuHqcUUUUU= X-CM-SenderInfo: x2kd0wpvhquxxxdqqvxvzl0uprps33xlqjhudrp/ Content-Type: text/plain; charset="utf-8" From: Senchuan Zhang Add Device Tree binding documentation for the Eswin EIC7700 PCIe controller module, the PCIe controller enables the core to correctly initialize and manage the PCIe bus and connected devices. Signed-off-by: Yu Ning Signed-off-by: Yanghui Ou Signed-off-by: Senchuan Zhang Reviewed-by: Rob Herring (Arm) --- .../bindings/pci/eswin,eic7700-pcie.yaml | 167 ++++++++++++++++++ 1 file changed, 167 insertions(+) create mode 100644 Documentation/devicetree/bindings/pci/eswin,eic7700-pci= e.yaml diff --git a/Documentation/devicetree/bindings/pci/eswin,eic7700-pcie.yaml = b/Documentation/devicetree/bindings/pci/eswin,eic7700-pcie.yaml new file mode 100644 index 000000000000..9c0150834e6d --- /dev/null +++ b/Documentation/devicetree/bindings/pci/eswin,eic7700-pcie.yaml @@ -0,0 +1,167 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pci/eswin,eic7700-pcie.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Eswin EIC7700 PCIe host controller + +maintainers: + - Yu Ning + - Senchuan Zhang + - Yanghui Ou + +description: + Eswin EIC7700 SoC PCIe root complex controller is based on the Synopsys + DesignWare PCIe IP. + +properties: + compatible: + const: eswin,eic7700-pcie + + reg: + maxItems: 3 + + reg-names: + items: + - const: dbi + - const: config + - const: elbi + + ranges: + maxItems: 3 + + '#interrupt-cells': + const: 1 + + interrupt-names: + items: + - const: msi + - const: inta + - const: intb + - const: intc + - const: intd + + interrupt-map: + maxItems: 4 + + interrupt-map-mask: + items: + - const: 0 + - const: 0 + - const: 0 + - const: 7 + + clocks: + maxItems: 4 + + clock-names: + items: + - const: mstr + - const: dbi + - const: phy_reg + - const: aux + + resets: + maxItems: 2 + + reset-names: + items: + - const: dbi + - const: pwr + +patternProperties: + "^pcie@": + type: object + $ref: /schemas/pci/pci-pci-bridge.yaml# + + properties: + reg: + maxItems: 1 + + num-lanes: + maximum: 4 + + resets: + maxItems: 1 + + reset-names: + items: + - const: perst + + required: + - reg + - ranges + - num-lanes + - resets + - reset-names + + unevaluatedProperties: false + +required: + - compatible + - reg + - ranges + - interrupts + - interrupt-names + - interrupt-map-mask + - interrupt-map + - '#interrupt-cells' + - clocks + - clock-names + - resets + - reset-names + +allOf: + - $ref: /schemas/pci/snps,dw-pcie.yaml# + +unevaluatedProperties: false + +examples: + - | + soc { + #address-cells =3D <2>; + #size-cells =3D <2>; + + pcie@54000000 { + compatible =3D "eswin,eic7700-pcie"; + reg =3D <0x0 0x54000000 0x0 0x4000000>, + <0x0 0x40000000 0x0 0x800000>, + <0x0 0x50000000 0x0 0x100000>; + reg-names =3D "dbi", "config", "elbi"; + #address-cells =3D <3>; + #size-cells =3D <2>; + #interrupt-cells =3D <1>; + ranges =3D <0x01000000 0x0 0x40800000 0x0 0x40800000 0x0 0x800= 000>, + <0x02000000 0x0 0x41000000 0x0 0x41000000 0x0 0xf0000= 00>, + <0x43000000 0x80 0x00000000 0x80 0x00000000 0x2 0x000= 00000>; + bus-range =3D <0x00 0xff>; + clocks =3D <&clock 144>, + <&clock 145>, + <&clock 146>, + <&clock 147>; + clock-names =3D "mstr", "dbi", "phy_reg", "aux"; + resets =3D <&reset 97>, + <&reset 98>; + reset-names =3D "dbi", "pwr"; + interrupts =3D <220>, <179>, <180>, <181>, <182>, <183>, <184>= , <185>, <186>; + interrupt-names =3D "msi", "inta", "intb", "intc", "intd"; + interrupt-parent =3D <&plic>; + interrupt-map-mask =3D <0x0 0x0 0x0 0x7>; + interrupt-map =3D <0x0 0x0 0x0 0x1 &plic 179>, + <0x0 0x0 0x0 0x2 &plic 180>, + <0x0 0x0 0x0 0x3 &plic 181>, + <0x0 0x0 0x0 0x4 &plic 182>; + device_type =3D "pci"; + pcie@0 { + reg =3D <0x0 0x0 0x0 0x0 0x0>; + #address-cells =3D <3>; + #size-cells =3D <2>; + ranges; + device_type =3D "pci"; + num-lanes =3D <4>; + resets =3D <&reset 99>; + reset-names =3D "perst"; + }; + }; + }; --=20 2.25.1 From nobody Mon Dec 15 21:59:57 2025 Received: from zg8tmja2lje4os4yms4ymjma.icoremail.net (zg8tmja2lje4os4yms4ymjma.icoremail.net [206.189.21.223]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 56C623081C5; Tue, 2 Dec 2025 09:04:25 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=206.189.21.223 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764666269; cv=none; b=M0IJqdyDd2YU5Y43E3H6Oa1tUmvwiBScswbBOjcfPVF5FVvVG11eOv7GmibEdy1zqASRPq4bQcgwuqx1BznTMNMxiQX0K/7W4cTweaiq3Bin/guTPQaVa2D8tW0kkZWE2timjBHwuH9Ug4RyKUB21F95dLqMCvIon63qMyd6BBg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764666269; c=relaxed/simple; bh=xFhTlcePwXMhCsPzBMSaPqSSWv00X9gVpykK2B9VAF4=; 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charset="utf-8" From: Senchuan Zhang Add driver for the Eswin EIC7700 PCIe host controller, which is based on the DesignWare PCIe core, IP revision 5.96a. The PCIe Gen.3 controller supports a data rate of 8 GT/s and 4 channels, support INTx and MSI interrupts. Signed-off-by: Yu Ning Signed-off-by: Yanghui Ou Signed-off-by: Senchuan Zhang --- drivers/pci/controller/dwc/Kconfig | 11 + drivers/pci/controller/dwc/Makefile | 1 + drivers/pci/controller/dwc/pcie-eic7700.c | 378 ++++++++++++++++++++++ 3 files changed, 390 insertions(+) create mode 100644 drivers/pci/controller/dwc/pcie-eic7700.c diff --git a/drivers/pci/controller/dwc/Kconfig b/drivers/pci/controller/dw= c/Kconfig index 519b59422b47..c837cb5947b6 100644 --- a/drivers/pci/controller/dwc/Kconfig +++ b/drivers/pci/controller/dwc/Kconfig @@ -93,6 +93,17 @@ config PCIE_BT1 Enables support for the PCIe controller in the Baikal-T1 SoC to work in host mode. It's based on the Synopsys DWC PCIe v4.60a IP-core. =20 +config PCIE_EIC7700 + tristate "Eswin EIC7700 PCIe controller" + depends on ARCH_ESWIN || COMPILE_TEST + depends on PCI_MSI + select PCIE_DW_HOST + help + Say Y here if you want PCIe controller support for the Eswin EIC7700. + The PCIe controller on EIC7700 is based on DesignWare hardware, + enables support for the PCIe controller in the EIC7700 SoC to work in + host mode. + config PCI_IMX6 bool =20 diff --git a/drivers/pci/controller/dwc/Makefile b/drivers/pci/controller/d= wc/Makefile index 67ba59c02038..7c5a5186ea83 100644 --- a/drivers/pci/controller/dwc/Makefile +++ b/drivers/pci/controller/dwc/Makefile @@ -6,6 +6,7 @@ obj-$(CONFIG_PCIE_DW_EP) +=3D pcie-designware-ep.o obj-$(CONFIG_PCIE_DW_PLAT) +=3D pcie-designware-plat.o obj-$(CONFIG_PCIE_AMD_MDB) +=3D pcie-amd-mdb.o obj-$(CONFIG_PCIE_BT1) +=3D pcie-bt1.o +obj-$(CONFIG_PCIE_EIC7700) +=3D pcie-eic7700.o obj-$(CONFIG_PCI_DRA7XX) +=3D pci-dra7xx.o obj-$(CONFIG_PCI_EXYNOS) +=3D pci-exynos.o obj-$(CONFIG_PCIE_FU740) +=3D pcie-fu740.o diff --git a/drivers/pci/controller/dwc/pcie-eic7700.c b/drivers/pci/contro= ller/dwc/pcie-eic7700.c new file mode 100644 index 000000000000..cb7cdea6a94b --- /dev/null +++ b/drivers/pci/controller/dwc/pcie-eic7700.c @@ -0,0 +1,378 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * ESWIN EIC7700 PCIe root complex driver + * + * Copyright 2025, Beijing ESWIN Computing Technology Co., Ltd. + * + * Authors: Yu Ning + * Senchuan Zhang + * Yanghui Ou + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "pcie-designware.h" + +/* ELBI registers */ +#define PCIEELBI_CTRL0_OFFSET 0x0 +#define PCIEELBI_STATUS0_OFFSET 0x100 + +/* LTSSM register fields */ +#define PCIEELBI_APP_LTSSM_ENABLE BIT(5) + +/* APP_HOLD_PHY_RST register fields */ +#define PCIEELBI_APP_HOLD_PHY_RST BIT(6) + +/* PM_SEL_AUX_CLK register fields */ +#define PCIEELBI_PM_SEL_AUX_CLK BIT(16) + +/* DEV_TYPE register fields */ +#define PCIEELBI_CTRL0_DEV_TYPE GENMASK(3, 0) + +/* Vendor and device ID value */ +#define PCI_VENDOR_ID_ESWIN 0x1fe1 +#define PCI_DEVICE_ID_ESWIN 0x2030 + +#define EIC7700_NUM_RSTS ARRAY_SIZE(eic7700_pcie_rsts) + +static const char * const eic7700_pcie_rsts[] =3D { + "pwr", + "dbi", +}; + +struct eic7700_pcie_data { + bool no_pme_handshake; +}; + +struct eic7700_pcie_port { + struct list_head list; + struct reset_control *perst; + int num_lanes; +}; + +struct eic7700_pcie { + struct dw_pcie pci; + struct clk_bulk_data *clks; + struct reset_control_bulk_data resets[EIC7700_NUM_RSTS]; + struct list_head ports; + const struct eic7700_pcie_data *data; + int num_clks; +}; + +#define to_eic7700_pcie(x) dev_get_drvdata((x)->dev) + +static int eic7700_pcie_start_link(struct dw_pcie *pci) +{ + u32 val; + + /* Enable LTSSM */ + val =3D readl_relaxed(pci->elbi_base + PCIEELBI_CTRL0_OFFSET); + val |=3D PCIEELBI_APP_LTSSM_ENABLE; + writel_relaxed(val, pci->elbi_base + PCIEELBI_CTRL0_OFFSET); + + return 0; +} + +static bool eic7700_pcie_link_up(struct dw_pcie *pci) +{ + u16 offset =3D dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); + u16 val =3D dw_pcie_readw_dbi(pci, offset + PCI_EXP_LNKSTA); + + return val & PCI_EXP_LNKSTA_DLLLA; +} + +static int eic7700_pcie_perst_reset(struct eic7700_pcie_port *port, + struct eic7700_pcie *pcie) +{ + int ret; + + ret =3D reset_control_assert(port->perst); + if (ret) { + dev_err(pcie->pci.dev, "Failed to assert PERST#\n"); + return ret; + } + + /* Ensure that PERST# has been asserted for at least 100 ms */ + msleep(PCIE_T_PVPERL_MS); + + ret =3D reset_control_deassert(port->perst); + if (ret) { + dev_err(pcie->pci.dev, "Failed to deassert PERST#\n"); + return ret; + } + + return 0; +} + +static int eic7700_pcie_parse_port(struct eic7700_pcie *pcie, + struct device_node *node) +{ + struct device *dev =3D pcie->pci.dev; + struct eic7700_pcie_port *port; + + port =3D devm_kzalloc(dev, sizeof(*port), GFP_KERNEL); + if (!port) + return -ENOMEM; + + port->perst =3D of_reset_control_get_exclusive(node, "perst"); + if (IS_ERR(port->perst)) { + dev_err(dev, "Failed to get PERST# reset\n"); + return PTR_ERR(port->perst); + } + + /* + * TODO: Since the Root Port node is separated out by pcie devicetree, + * the DWC core initialization code can't parse the num-lanes attribute + * in the Root Port. Before entering the DWC core initialization code, + * the platform driver code parses the Root Port node. The EIC7700 only + * supports one Root Port node, and the num-lanes attribute is suitable + * for the case of one Root Rort. + */ + if (!of_property_read_u32(node, "num-lanes", &port->num_lanes)) + pcie->pci.num_lanes =3D port->num_lanes; + + INIT_LIST_HEAD(&port->list); + list_add_tail(&port->list, &pcie->ports); + + return 0; +} + +static int eic7700_pcie_parse_ports(struct eic7700_pcie *pcie) +{ + struct eic7700_pcie_port *port, *tmp; + struct device *dev =3D pcie->pci.dev; + int ret; + + for_each_available_child_of_node_scoped(dev->of_node, of_port) { + ret =3D eic7700_pcie_parse_port(pcie, of_port); + if (ret) + goto err_port; + } + + return 0; + +err_port: + list_for_each_entry_safe(port, tmp, &pcie->ports, list) + list_del(&port->list); + + return ret; +} + +static int eic7700_pcie_host_init(struct dw_pcie_rp *pp) +{ + struct dw_pcie *pci =3D to_dw_pcie_from_pp(pp); + struct eic7700_pcie *pcie =3D to_eic7700_pcie(pci); + struct eic7700_pcie_port *port; + u32 val; + int ret; + + pcie->num_clks =3D devm_clk_bulk_get_all_enabled(pci->dev, &pcie->clks); + if (pcie->num_clks < 0) + return dev_err_probe(pci->dev, pcie->num_clks, + "Failed to get pcie clocks\n"); + + /* + * The PWR and DBI Reset signals are respectively used to reset the + * PCIe controller and the DBI registers. + * The PERST# signal is a reset signal that simultaneously controls the + * PCIe controller, PHY, and Endpoint. + * Before configuring the PHY, the PERST# signal must first be + * deasserted. + * The external reference clock is supplied simultaneously to the PHY + * and EP. When the PHY is configurable, the entire chip already has + * stable power and reference clock. + * The PHY will be ready within 20ms after writing app_hold_phy_rst + * register of ELBI register space. + */ + ret =3D reset_control_bulk_deassert(EIC7700_NUM_RSTS, pcie->resets); + if (ret) { + dev_err(pcie->pci.dev, "Failed to deassert resets\n"); + return ret; + } + + /* Configure Root Port type */ + val =3D readl_relaxed(pci->elbi_base + PCIEELBI_CTRL0_OFFSET); + val &=3D ~PCIEELBI_CTRL0_DEV_TYPE; + val |=3D FIELD_PREP(PCIEELBI_CTRL0_DEV_TYPE, PCI_EXP_TYPE_ROOT_PORT); + writel_relaxed(val, pci->elbi_base + PCIEELBI_CTRL0_OFFSET); + + list_for_each_entry(port, &pcie->ports, list) { + ret =3D eic7700_pcie_perst_reset(port, pcie); + if (ret) + goto err_perst; + } + + /* Configure app_hold_phy_rst */ + val =3D readl_relaxed(pci->elbi_base + PCIEELBI_CTRL0_OFFSET); + val &=3D ~PCIEELBI_APP_HOLD_PHY_RST; + writel_relaxed(val, pci->elbi_base + PCIEELBI_CTRL0_OFFSET); + + /* The maximum waiting time for the clock switch lock is 20ms */ + ret =3D readl_poll_timeout(pci->elbi_base + PCIEELBI_STATUS0_OFFSET, + val, !(val & PCIEELBI_PM_SEL_AUX_CLK), 1000, + 20000); + if (ret) { + dev_err(pci->dev, "Timeout waiting for PM_SEL_AUX_CLK ready\n"); + goto err_phy_init; + } + + /* + * Configure ESWIN VID:DID for Root Port as the default values are + * invalid. + */ + dw_pcie_writew_dbi(pci, PCI_VENDOR_ID, PCI_VENDOR_ID_ESWIN); + dw_pcie_writew_dbi(pci, PCI_DEVICE_ID, PCI_DEVICE_ID_ESWIN); + + return 0; + +err_phy_init: + list_for_each_entry(port, &pcie->ports, list) + reset_control_assert(port->perst); +err_perst: + reset_control_bulk_assert(EIC7700_NUM_RSTS, pcie->resets); + + return ret; +} + +static void eic7700_pcie_host_deinit(struct dw_pcie_rp *pp) +{ + struct dw_pcie *pci =3D to_dw_pcie_from_pp(pp); + struct eic7700_pcie *pcie =3D to_eic7700_pcie(pci); + struct eic7700_pcie_port *port; + + list_for_each_entry(port, &pcie->ports, list) + reset_control_assert(port->perst); + reset_control_bulk_assert(EIC7700_NUM_RSTS, pcie->resets); + clk_bulk_disable_unprepare(pcie->num_clks, pcie->clks); +} + +static const struct dw_pcie_host_ops eic7700_pcie_host_ops =3D { + .init =3D eic7700_pcie_host_init, + .deinit =3D eic7700_pcie_host_deinit, +}; + +static const struct dw_pcie_ops dw_pcie_ops =3D { + .start_link =3D eic7700_pcie_start_link, + .link_up =3D eic7700_pcie_link_up, +}; + +static int eic7700_pcie_probe(struct platform_device *pdev) +{ + const struct eic7700_pcie_data *data; + struct eic7700_pcie_port *port, *tmp; + struct device *dev =3D &pdev->dev; + struct eic7700_pcie *pcie; + struct dw_pcie *pci; + int ret, i; + + data =3D of_device_get_match_data(dev); + if (!data) + return dev_err_probe(dev, -ENODATA, "OF data missing\n"); + + pcie =3D devm_kzalloc(dev, sizeof(*pcie), GFP_KERNEL); + if (!pcie) + return -ENOMEM; + + INIT_LIST_HEAD(&pcie->ports); + + pci =3D &pcie->pci; + pci->dev =3D dev; + pci->ops =3D &dw_pcie_ops; + pci->pp.ops =3D &eic7700_pcie_host_ops; + pcie->data =3D data; + pci->no_pme_handshake =3D pcie->data->no_pme_handshake; + + for (i =3D 0; i < EIC7700_NUM_RSTS; i++) + pcie->resets[i].id =3D eic7700_pcie_rsts[i]; + + ret =3D devm_reset_control_bulk_get_exclusive(dev, EIC7700_NUM_RSTS, + pcie->resets); + if (ret) + return dev_err_probe(dev, ret, "Failed to get resets\n"); + + ret =3D eic7700_pcie_parse_ports(pcie); + if (ret) + return dev_err_probe(dev, ret, + "Failed to parse Root Port: %d\n", ret); + + platform_set_drvdata(pdev, pcie); + + pm_runtime_no_callbacks(dev); + devm_pm_runtime_enable(dev); + ret =3D pm_runtime_get_sync(dev); + if (ret < 0) + goto err_pm_runtime_put; + + ret =3D dw_pcie_host_init(&pci->pp); + if (ret) { + dev_err(dev, "Failed to initialize host\n"); + goto err_init; + } + + return 0; + +err_init: + list_for_each_entry_safe(port, tmp, &pcie->ports, list) { + list_del(&port->list); + reset_control_put(port->perst); + } +err_pm_runtime_put: + pm_runtime_put(dev); + + return ret; +} + +static int eic7700_pcie_suspend_noirq(struct device *dev) +{ + struct eic7700_pcie *pcie =3D dev_get_drvdata(dev); + + return dw_pcie_suspend_noirq(&pcie->pci); +} + +static int eic7700_pcie_resume_noirq(struct device *dev) +{ + struct eic7700_pcie *pcie =3D dev_get_drvdata(dev); + + return dw_pcie_resume_noirq(&pcie->pci); +} + +static const struct dev_pm_ops eic7700_pcie_pm_ops =3D { + NOIRQ_SYSTEM_SLEEP_PM_OPS(eic7700_pcie_suspend_noirq, + eic7700_pcie_resume_noirq) +}; + +static const struct eic7700_pcie_data eic7700_data =3D { + .no_pme_handshake =3D true, +}; + +static const struct of_device_id eic7700_pcie_of_match[] =3D { + { .compatible =3D "eswin,eic7700-pcie", .data =3D &eic7700_data }, + {}, +}; + +static struct platform_driver eic7700_pcie_driver =3D { + .probe =3D eic7700_pcie_probe, + .driver =3D { + .name =3D "eic7700-pcie", + .of_match_table =3D eic7700_pcie_of_match, + .suppress_bind_attrs =3D true, + .pm =3D &eic7700_pcie_pm_ops, + .probe_type =3D PROBE_PREFER_ASYNCHRONOUS, + }, +}; +builtin_platform_driver(eic7700_pcie_driver); + +MODULE_DESCRIPTION("Eswin EIC7700 PCIe host controller driver"); +MODULE_AUTHOR("Yu Ning "); +MODULE_AUTHOR("Senchuan Zhang "); +MODULE_AUTHOR("Yanghui Ou "); +MODULE_LICENSE("GPL"); --=20 2.25.1 From nobody Mon Dec 15 21:59:57 2025 Received: from azure-sdnproxy.icoremail.net (azure-sdnproxy.icoremail.net [4.193.249.245]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 22BEF3081DF; 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dmarc=none (p=none dis=none) header.from=eswincomputing.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=eswincomputing.com Received: from E0004758DT.eswin.cn (unknown [10.12.96.83]) by app1 (Coremail) with SMTP id TAJkCgAHAWmlqy5pPqiAAA--.37439S2; Tue, 02 Dec 2025 17:04:38 +0800 (CST) From: zhangsenchuan@eswincomputing.com To: bhelgaas@google.com, mani@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, lpieralisi@kernel.org, kwilczynski@kernel.org, robh@kernel.org, p.zabel@pengutronix.de, jingoohan1@gmail.com, gustavo.pimentel@synopsys.com, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, christian.bruel@foss.st.com, mayank.rana@oss.qualcomm.com, shradha.t@samsung.com, krishna.chundru@oss.qualcomm.com, thippeswamy.havalige@amd.com, inochiama@gmail.com, Frank.li@nxp.com Cc: ningyu@eswincomputing.com, linmin@eswincomputing.com, pinkesh.vaghela@einfochips.com, ouyanghui@eswincomputing.com, Senchuan Zhang Subject: [PATCH v7 3/3] PCI: dwc: Add no_pme_handshake flag and skip PME_Turn_Off broadcast Date: Tue, 2 Dec 2025 17:04:34 +0800 Message-ID: <20251202090434.1653-1-zhangsenchuan@eswincomputing.com> X-Mailer: git-send-email 2.49.0.windows.1 In-Reply-To: <20251202090225.1602-1-zhangsenchuan@eswincomputing.com> References: <20251202090225.1602-1-zhangsenchuan@eswincomputing.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: TAJkCgAHAWmlqy5pPqiAAA--.37439S2 X-Coremail-Antispam: 1UD129KBjvJXoW7uF18Cr1rCr4fJry7AF15twb_yoW8uF17pa 98tFWIyF1rXF4Yva1Yy3Z3ur13t3Z8CFyUGa9ak3WfWFy2vayUK34fJFy3trn7JrWI9ry3 K345t34fCF43JFUanT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnRJUUUBm14x267AKxVW5JVWrJwAFc2x0x2IEx4CE42xK8VAvwI8IcIk0 rVWrJVCq3wAFIxvE14AKwVWUJVWUGwA2ocxC64kIII0Yj41l84x0c7CEw4AK67xGY2AK02 1l84ACjcxK6xIIjxv20xvE14v26w1j6s0DM28EF7xvwVC0I7IYx2IY6xkF7I0E14v26r4U JVWxJr1l84ACjcxK6I8E87Iv67AKxVW0oVCq3wA2z4x0Y4vEx4A2jsIEc7CjxVAFwI0_Gc CE3s1le2I262IYc4CY6c8Ij28IcVAaY2xG8wAqx4xG64xvF2IEw4CE5I8CrVC2j2WlYx0E 2Ix0cI8IcVAFwI0_Jrv_JF1lYx0Ex4A2jsIE14v26r1j6r4UMcvjeVCFs4IE7xkEbVWUJV W8JwACjcxG0xvY0x0EwIxGrwACjI8F5VA0II8E6IAqYI8I648v4I1lFIxGxcIEc7CjxVA2 Y2ka0xkIwI1lw4CEc2x0rVAKj4xxMxkF7I0En4kS14v26r4a6rW5MxkIecxEwVCm-wCF04 k20xvY0x0EwIxGrwCFx2IqxVCFs4IE7xkEbVWUJVW8JwC20s026c02F40E14v26r1j6r18 MI8I3I0E7480Y4vE14v26r106r1rMI8E67AF67kF1VAFwI0_GFv_WrylIxkGc2Ij64vIr4 1lIxAIcVC0I7IYx2IY67AKxVWUJVWUCwCI42IY6xIIjxv20xvEc7CjxVAFwI0_Cr0_Gr1U MIIF0xvE42xK8VAvwI8IcIk0rVWUJVWUCwCI42IY6I8E87Iv67AKxVWUJVW8JwCI42IY6I 8E87Iv6xkF7I0E14v26r4j6r4UJbIYCTnIWIevJa73UjIFyTuYvjTRNSdgDUUUU X-CM-SenderInfo: x2kd0wpvhquxxxdqqvxvzl0uprps33xlqjhudrp/ Content-Type: text/plain; charset="utf-8" From: Senchuan Zhang The ESWIN EIC7700 SoC lacks hardware support for the L2/L3 low-power link states. It cannot enter the L2/L3 ready state through the PME_Turn_Off/PME_To_Ack handshake protocol. To address this, add a no_pme_handshake flag skip PME_Turn_Off broadcast and link state check code, other driver can reuse this flag if meet the similar situation. Signed-off-by: Yu Ning Signed-off-by: Yanghui Ou Signed-off-by: Senchuan Zhang --- drivers/pci/controller/dwc/pcie-designware-host.c | 4 ++++ drivers/pci/controller/dwc/pcie-designware.h | 1 + 2 files changed, 5 insertions(+) diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pc= i/controller/dwc/pcie-designware-host.c index 372207c33a85..8302bc7a6cbf 100644 --- a/drivers/pci/controller/dwc/pcie-designware-host.c +++ b/drivers/pci/controller/dwc/pcie-designware-host.c @@ -1168,6 +1168,9 @@ int dw_pcie_suspend_noirq(struct dw_pcie *pci) if (dw_pcie_readw_dbi(pci, offset + PCI_EXP_LNKCTL) & PCI_EXP_LNKCTL_ASPM= _L1) return 0; + if (pci->no_pme_handshake) + goto stop_link; + if (pci->pp.ops->pme_turn_off) { pci->pp.ops->pme_turn_off(&pci->pp); } else { @@ -1194,6 +1197,7 @@ int dw_pcie_suspend_noirq(struct dw_pcie *pci) */ udelay(1); +stop_link: dw_pcie_stop_link(pci); if (pci->pp.ops->deinit) pci->pp.ops->deinit(&pci->pp); diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/con= troller/dwc/pcie-designware.h index 31685951a080..e8057db303d0 100644 --- a/drivers/pci/controller/dwc/pcie-designware.h +++ b/drivers/pci/controller/dwc/pcie-designware.h @@ -549,6 +549,7 @@ struct dw_pcie { * use_parent_dt_ranges to true to avoid this warning. */ bool use_parent_dt_ranges; + bool no_pme_handshake; }; #define to_dw_pcie_from_pp(port) container_of((port), struct dw_pcie, pp) -- 2.25.1